JP2002229653A - Reference voltage generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reference voltage generating circuit capable of reducing a resistance value forming a time constant for setting the time required for stabilization of the output voltage without requiring a time more than necessity and capable of improving the noise resistant characteristic. SOLUTION: A capacitor C1 is charged at a power source voltage VDD higher than the reference voltage VREF by a constant current circuit unit 6 till the voltage output from a SMUTE terminal reaches the reference voltage VREF. When the capacitor C1 is charged to the reference voltage VREF, an impedance converting circuit unit 3 constantly holds the voltage of the SMUTE terminal at the reference voltage VREF.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a reference voltage generation circuit formed on a semiconductor integrated circuit, and more particularly to a reference voltage generation circuit for realizing a stable voltage supply.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing an example of a conventional reference voltage generating circuit. Reference voltage generating circuit 1 shown in FIG.
00 is a resistor R0 and a capacitor C with respect to a predetermined reference voltage VREF generated and output by the reference voltage generator 101.
At 0, the rise time is to be controlled. Reference voltage VREF output from reference voltage generator 101 via a voltage follower formed by operational amplifier 102
Is controlled by the resistor R0 and the capacitor C0 to control the rise time, and is output from the output terminal SMUTE.

On the other hand, a predetermined sleep signal SL
P, for example, a sleep signal SLP at a high level
Is input, the reference voltage generator 101 outputs the reference voltage V
The output of the REF is stopped, the output terminal goes to a low level, the operational amplifier 102 is deactivated, and the output terminal is opened. Further, the switch 103 is turned on to be in a conductive state, and the SMUTE terminal is grounded. Thus, the reference voltage VR is supplied to the reference voltage generation circuit 100.
The high-level sleep signal SLP is input at the time of power-down for stopping the output of the EF, and the low-level sleep signal SLP is input at the time of power-down release for outputting the reference voltage VREF.

FIG. 5 shows the reference voltage generating circuit 1 shown in FIG.
6 is a timing chart showing a waveform example of each unit at 00. 4 and 5, the negative power supply terminal VSS
Is connected to the ground (GND).
As can be seen from FIG. 5, when the sleep signal SLP falls from the high level to the low level when the power down is released, the switch 103 is turned off to be in the cutoff state, and the reference voltage generation unit 101 outputs the reference voltage VREF and performs the calculation. The amplifier 102 is activated and operates as a voltage follower. Therefore, the SMUTE terminal is connected to the resistor R
It rises from the ground level to the reference voltage VREF over a time determined by the time constant of 0 and the time constant of the capacitor C0.

If it is desired to increase the time constant of the resistor R0 and the capacitor C0 in order to secure a predetermined period for the rise of the output voltage from the SMUTE terminal, the resistor R0
Alternatively, one of the capacitors C0 may be increased. On the other hand, in an electronic circuit board or the like on which a large number of semiconductor integrated circuits are mounted, it is desirable to design the physical size of each component as small as possible. From this,
The time constant is increased by increasing the resistance R0, which is easy to integrate, without increasing the size of the capacitor C0.

[0006]

However, if the resistance R0 is too large, the impedance of the SMUTE terminal increases, the output voltage from the SMUTE terminal becomes unstable due to external noise, and the thermal noise due to the resistance R0 itself increases. There was a problem that would be. In addition, as shown in FIG. 5, the power supply voltage VDD is applied to VDD.
In some cases, diodes for preventing electrostatic breakdown must be inserted as protective circuits between the terminal and the SMUTE terminal and between the SMUTE terminal and the ground.

In such a protection circuit, the power supply voltage VDD
A problem has arisen that the voltage at the SMUTE terminal deviates from a desired voltage value due to the leakage current of the diode D0 connected between the SMUTE terminal and the SMUTE terminal. Further, the voltage charged in the capacitor C0 is VREF ·
Since it increases following an asymptote such as {1- ^{et / (C0 · R0)} }, and the ultimate voltage at the time of completion of charging of the capacitor C0 becomes a desired voltage at the SMUTE terminal,
There is a problem that it takes more time than necessary to reach the desired voltage.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and charges a capacitor having a time constant higher than a predetermined reference voltage to be output. Then, by lowering the impedance of the output terminal, it is possible to reduce the resistance value forming a time constant for setting the time without requiring an unnecessary time until the output voltage is stabilized, and to reduce noise resistance. It is an object of the present invention to obtain a reference voltage generation circuit capable of improving characteristics.

[0009]

According to the present invention, there is provided a reference voltage generating circuit for generating and outputting a predetermined reference voltage in response to a predetermined signal input from the outside. A reference voltage generating unit for generating and outputting a predetermined reference voltage according to the following; a CR circuit unit for charging an input voltage to a capacitor via a resistor and outputting the charged voltage from an output terminal; An impedance conversion circuit unit that receives a reference voltage from the unit at a high input impedance and sends it out at a low impedance and outputs it to the CR circuit unit, and outputs a constant current larger than the reference voltage to the CR circuit unit. A constant current circuit unit that detects the voltage of the output terminal, and, according to the detected voltage, either one of the impedance conversion circuit unit and the constant current circuit unit. An output voltage detecting unit for operating the constant current circuit unit when the voltage of the output terminal is lower than the reference voltage, and an impedance conversion circuit when the voltage of the output terminal becomes the reference voltage. The part is operated.

Specifically, when the voltage at the output terminal is lower than the reference voltage, the output voltage detector generates a comparison reference voltage by dividing the reference voltage and outputs the same. Then, a comparison reference voltage generator for outputting a reference voltage as the comparison reference voltage, a comparison between the voltage of the output terminal and the comparison reference voltage from the comparison reference voltage generator, and an impedance conversion circuit unit according to the comparison result. And a voltage comparison unit for controlling the operation of the constant current circuit unit.

Further, the comparison reference voltage generator may switch the comparison reference voltage according to the comparison result of the voltage comparator.

On the other hand, the constant current circuit section includes a constant current source that supplies a predetermined constant current using a voltage higher than the reference voltage as a power supply, and outputs a current corresponding to the current from the constant current source to the CR circuit section. And a control circuit for controlling the operation of the current mirror circuit in accordance with the operation control from the output voltage detection unit.

The constant current circuit section includes a resistance circuit for supplying a predetermined constant current using a voltage higher than the reference voltage as a power supply, and an output from the resistance circuit in accordance with operation control from an output voltage detection section. And a control circuit for controlling the supply of the current to the CR circuit unit.

Further, the power supply circuit is provided between the output terminal and the positive power supply terminal to which the positive power supply voltage is applied, and between the negative power supply terminal to which the negative power supply voltage is applied and the output terminal.
A protection circuit unit including diodes for preventing reverse voltage from being applied may be provided.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. FIG. 1 is a circuit diagram showing an example of a reference voltage generation circuit according to an embodiment of the present invention. FIG. 1 shows an example in which the negative power supply terminal VSS is grounded. 1, a reference voltage generation circuit 1 generates and outputs a predetermined reference voltage VREF, and an impedance that performs impedance conversion of the reference voltage VREF input from the reference voltage generation unit 2 and outputs the result. Conversion circuit unit 3 and CR circuit unit 4
A protection circuit 5, a constant current circuit 6 for supplying a constant current to the CR circuit 4, and an output voltage for controlling the operations of the impedance conversion circuit 3 and the constant current circuit 6 according to the detected output voltage. And a detection unit 7.

The reference voltage generating section 2 receives a predetermined sleep signal SLP from the outside, for example, a high-level sleep signal SL.
When P is input, the output of the reference voltage VREF is stopped and the output terminal goes to low level. When the low-level sleep signal SLP is input, the reference voltage VREF is output from the output terminal. The impedance conversion circuit unit 3 includes an operational amplifier 11 that forms a voltage follower and an OR circuit 12 that generates and outputs an activation signal for the operational amplifier 11. The operational amplifier 11 includes a reference voltage generator 2
Operates as a voltage follower with respect to the reference voltage VREF output from

That is, the operational amplifier 11 outputs the reference voltage V
An operation of receiving REF with high input impedance and sending out with low output impedance is performed. The OR circuit 12
Performs activation control of the operational amplifier 11 according to the signal level of the input sleep signal SLP and the detection result of the output voltage detection unit 7. When a high-level signal is input from the OR circuit 12, the operational amplifier 11 is inactivated and the output terminal is in a high-impedance state.
When a low-level signal is input from the device, it is activated and operates as a voltage follower.

The CR circuit section 4 includes a resistor R1 and a capacitor C
1 and a switch SW1, a resistor R1 and a capacitor C1 are connected in series between an output terminal of the operational amplifier 11 and the ground, and a connection between the resistor R1 and the capacitor C1 is Is a SMUTE terminal. Further, a switch SW1 is connected in parallel with the capacitor C1, and the switching of the switch SW1 is controlled by a sleep signal SLP. For example, the switch SW1
Are turned on when the sleep signal SLP is at a high level and are turned on, and turned off when the sleep signal SLP is at a low level and are turned off. The protection circuit unit 5
VDD which is a positive power supply terminal to which the power supply voltage VDD is applied
It comprises a diode D1 connected in the forward direction between the terminal and the SMUTE terminal, and a diode D2 connected in the forward direction between the SMUTE terminal and the ground.

Next, the constant current circuit section 6 supplies a constant current to the CR circuit section 4, and includes P-channel MOS transistors (hereinafter referred to as PMOS transistors) Tr1 and Tr2 forming a current mirror circuit; PMOS transistor Tr3 for controlling the operation of the current mirror circuit
And a constant current source 15 for generating a constant current Iref. The gates of the PMOS transistors Tr1 and Tr2 are connected to each other, and the connection is connected to the drains of the PMOS transistors Tr1 and Tr3, respectively. In addition, each source of the PMOS transistors Tr1 to Tr3 is connected to the VDD terminal, respectively.
A constant current source 15 is connected between the drain of the transistor Tr1 and the ground, and a PMOS transistor Tr
The drain of 2 is connected to the resistor R1.

On the other hand, the output voltage detecting section 7 includes the voltage comparator 2
1, an inverter circuit 22, resistors R2 and R3, and a switch SW2. The activation of the voltage comparator 21 is controlled by the sleep signal SLP. When a high-level sleep signal SLP is input, the voltage comparator 21 is in an inactive state, the output terminal is at a low level, and the low-level sleep signal SLP is attained.
When LP is input, it is activated and outputs a comparison result.

The series circuit of the resistors R2 and R3 and the switch SW2 is connected between the output terminal of the reference voltage generator 2 and the ground. In the voltage comparator 21, the inverting input terminal is
Connection between the resistor R1 and the capacitor C1, ie, SMUT
The non-inverting input terminal is connected to the E terminal, and the non-inverting input terminal is connected to a connection portion between the resistors R2 and R3. Further, an output terminal of the voltage comparator 21 is connected to a control signal input terminal of the switch SW2, one input terminal of the OR circuit 12, and PM
Each is connected to the gate of the OS transistor Tr3.

In such a configuration, when the high-level sleep signal SLP is input, the reference voltage generating circuit 1 enters the inactive state, that is, the power down state, and the reference voltage generating circuit 1 enters the power down state.
When the UTE terminal goes to a low level and a low-level sleep signal SLP is input, the active state, that is, the SMU
The TE terminal becomes constant at the reference voltage VREF. FIG. 2 is a timing chart showing a waveform example of each part of the reference voltage generation circuit 1 shown in FIG. 1. The operation of the reference voltage generation circuit 1 will be described with reference to FIG. In FIG. 2, OP
SLP indicates the waveform at the output terminal of the OR circuit 12, CPOUT indicates the waveform at the output terminal of the voltage comparator 21, and CPREF indicates the waveform at the non-inverting input terminal of the voltage comparator 21.

When the high-level sleep signal SLP is input, the reference voltage generator 2 and the voltage comparator 21 are inactivated, and the output terminal of the voltage comparator 21 becomes low level, and the PMOS transistor Tr3 is turned off. When the switch is turned on, the switch SW2 is turned on to ground the resistor R3.
When the PMOS transistor Tr3 is turned on, each gate voltage of the PMOS transistors Tr1 and Tr2 increases,
The PMOS transistors Tr1 and Tr2 are turned off and turned off.

For this reason, the constant current circuit section 6 stops supplying current to the resistor R1. Further, since the sleep signal SLP is at a high level, the output terminal of the OR circuit 12 is at a high level, and the operational amplifier 11 is in an inactive state.
The output terminal of the operational amplifier 11 becomes high impedance.
Further, when the sleep signal SLP becomes high level, the switch SW1 is turned on, and the SMUTE terminal is grounded and becomes low level.

Next, when the sleep signal SLP falls from the high level to the low level, the switch SW1 is turned off and cut off, and the reference voltage generator 2 and the voltage comparator 2 are turned off.
1 are activated, and a predetermined reference voltage VREF is output from the output terminal of the reference voltage generator 2. At the same time, since the voltage of the non-inverting input terminal of the voltage comparator 21 is higher than the voltage of the inverting input terminal, the output terminal of the voltage comparator 21 becomes high level, and the switch SW2 is turned off to be in the cutoff state. When the switch SW2 is turned off, the voltage comparator 21
The reference voltage VREF is applied to the non-inverting input terminal, the voltage of the non-inverting input terminal becomes higher than that of the inverting input terminal, and the output terminal of the voltage comparator 21 becomes high level.

Further, when the output terminal of the voltage comparator 21 goes high, the PMOS transistor Tr3 is turned off and cut off.
Is supplied with a current i corresponding to the constant current Iref. At this time, since the output terminal of the OR circuit 12 is at a high level, the output terminal of the operational amplifier 11 is in a high impedance state. Therefore, the capacitor C1 is supplied with the current i from the constant current circuit section 6 via the resistor R1, and the reference voltage V
The battery is charged with the power supply voltage VDD higher than REF. Therefore, the voltage of the SMUTE terminal rises with a gradient of dV / dt = i / C1 (C1 indicates the capacitance of the capacitor C1), and the output terminal of the operational amplifier 11 is in a high impedance state even at this time. .

When the voltage at the SMUTE terminal rises and exceeds the reference voltage VREF, the output terminal of the voltage comparator 21 changes from high level to low level, turning on the PMOS transistor Tr3 and turning on the constant current circuit section 6. Supply of the current i from the switch is stopped, and the switch SW2 is turned on to turn on the resistor R.
3 is grounded. Further, the output terminal of the OR circuit 12 becomes low level, and the operational amplifier 11 is activated and outputs the reference voltage VREF from the output terminal.

When the switch SW2 is turned on, a voltage obtained by dividing the reference voltage VREF by the resistors R2 and R3 is input to the non-inverting input terminal of the voltage comparator 21. That is, CPREF = VREF × R3 / (R2 + R3) (R2 and R3 indicate the resistance values of the corresponding resistors R2 and R3), and the voltage applied to the non-inverting input terminal of the voltage comparator 21 is equal to the reference voltage. This prevents the voltage comparator 21 from becoming lower than the voltage VREF and inverting again.

In this way, the rising period of the output voltage from the SMUTE terminal ends, and the holding period of the output voltage from the SMUTE terminal ends.
Outputs a predetermined reference voltage VREF from the SMUTE terminal. Next, when the sleep signal SLP rises to a high level and enters the power down state again, the switch SW1
Is turned on to be in a conductive state, the electric charge charged in the capacitor C1 is discharged, the voltage of the SMUTE terminal decreases, and the SMUTE terminal eventually becomes the ground level.

The impedance of the SMUTE terminal was high during the charging period of the capacitor C1, but after completion of charging the capacitor C1, the resistance of the resistor R1 is high.
And the capacitor C1 to realize a low output impedance. For example, assuming that the capacitor C1 is equal to the capacitor in the conventional reference voltage generation circuit, in the present embodiment, it is only necessary to set the current i in the present embodiment, even if a time constant requiring a resistance of several MΩ is set in the present embodiment. This can be realized by setting the resistance value to several kΩ.

Although FIG. 1 shows an example in which the constant current circuit section 6 uses a constant current source and a current mirror circuit, a fixed resistor for limiting the current from the VDD terminal to make it constant is used. A constant current circuit section may be formed by using a reference voltage generating circuit in this case.
Shown in 3 differs from FIG. 1 in that the constant current circuit section 6 in FIG. 1 is formed by a PMOS transistor Tr4, an inverter circuit 31, and a resistor R4.

In the constant current circuit section 6 shown in FIG. 3, a series circuit of a resistor R4 and a PMOS transistor Tr4 is connected between the VDD terminal and the resistor R1.
1 is connected to the gate of the PMOS transistor Tr4 via the inverter circuit 31. The output terminal of the PMOS transistor Tr4 is connected to the resistor R from the VDD terminal in accordance with the operation of the PMOS transistor Tr4.
4 flows through the resistor R1. 3, the configuration of the constant current circuit unit 6 can be simplified and the cost can be reduced.
Since the value of the current i varies more than in the case of FIG. 1, the effect of cost reduction can be obtained when the variation is acceptable.

As described above, the reference voltage generating circuit according to the present embodiment uses the constant current circuit section 6 to supply the power supply voltage higher than the reference voltage VREF until the voltage output from the SMUTE terminal reaches the predetermined reference voltage VREF. The capacitor C1 was charged at VDD, and when the capacitor C1 was charged to the reference voltage VREF, the voltage of the SMUTE terminal was made constant by the impedance conversion circuit unit 3 at the reference voltage VREF. From this, it is possible to reduce the resistance value forming a time constant for setting the output voltage without taking an unnecessarily long time until the output voltage is stabilized. Terminal impedance can be reduced, and noise resistance can be improved.

Each switch S in FIGS. 1 and 2
W1 and SW2 indicate switch circuits formed of semiconductor elements, but may be switches having mechanical contacts. In the above description, the case where a MOS transistor is used has been described as an example. However, a bipolar transistor may be used instead of the MOS transistor.

[0035]

As is apparent from the above description, according to the reference voltage generating circuit of the present invention, when the voltage at the output terminal is lower than the reference voltage, the constant current circuit unit generates the CR at a voltage higher than the reference voltage. The capacitor in the circuit section is charged, and when the capacitor is charged to the reference voltage, the impedance conversion circuit section applies a reference voltage to the output terminal to lower the impedance. From this,
It is possible to reliably detect that the output voltage has reached the target voltage without lowering the output voltage from the output terminal to the target voltage, and reduce the impedance of the output terminal. Therefore, noise resistance can be improved. Furthermore, the resistance value of the resistor that forms a time constant with the capacitor in the CR circuit unit can be reduced, and thermal noise due to the resistor can be prevented.

More specifically, the output voltage detecting section compares a comparison reference voltage with a comparison reference voltage generation section that generates and outputs a comparison reference voltage corresponding to the voltage of the output terminal. Thus, a voltage comparison unit for controlling the operation of the impedance conversion circuit unit and the constant current circuit unit according to the comparison result is provided. Thus, it is possible to prevent malfunction of the voltage comparison unit due to noise, and to stabilize the output terminal voltage.

Further, since the comparison reference voltage generator switches the comparison reference voltage in accordance with the comparison result of the voltage comparator, it is possible to more reliably prevent the malfunction of the voltage comparison unit due to noise. As a result, the stability of the output terminal voltage can be improved.

On the other hand, the constant current circuit section specifically includes a constant current source for supplying a predetermined constant current using a voltage higher than the reference voltage as a power supply, and a current corresponding to the current from the constant current source as a CR. A current mirror circuit for outputting to the circuit unit and a control circuit for controlling the operation of the current mirror circuit according to the operation control from the output voltage detection unit are provided. Therefore, it is possible to eliminate the necessity of taking an unnecessarily long time until the voltage output from the output terminal is stabilized at the predetermined reference voltage.

Further, the constant current circuit section is, specifically,
A resistance circuit that supplies a predetermined constant current using a voltage higher than the reference voltage as a power supply, and a control that controls supply of an output current from the resistance circuit to the CR circuit unit according to operation control from the output voltage detection unit. And a circuit. Thus, the configuration of the constant current circuit unit can be simplified, cost can be reduced, and more time than necessary until the voltage output from the output terminal is stabilized at the predetermined reference voltage. It can eliminate the need.

Further, a protection circuit portion having diodes provided between the output terminal and the positive power supply terminal and between the negative power supply terminal and the output terminal is provided. Accordingly, it is possible to prevent the output terminal voltage from fluctuating due to the leakage current from the diode in the protection circuit unit, and to prevent electrostatic breakdown.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a reference voltage generation circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing a waveform example of each part of the reference voltage generation circuit shown in FIG.

FIG. 3 is a circuit diagram showing another example of the reference voltage generation circuit according to the embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional reference voltage generation circuit.

5 is a timing chart showing a waveform example of each part in the reference voltage generation circuit of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference voltage generation circuit 2 Reference voltage generation part 3 Impedance conversion circuit part 4 CR circuit part 5 Protection circuit part 6 Constant current circuit part 7 Output voltage detection part 11 Operational amplifier 21 Voltage comparator

Claims (6)

[Claims] 1. A reference voltage generating circuit for generating and outputting a predetermined reference voltage in response to a predetermined signal input from outside, and generating and outputting a predetermined reference voltage in response to the signal from outside. A reference voltage generating unit, a CR circuit unit that charges an input voltage to a capacitor via a resistor, and outputs the charged voltage from an output terminal, and receives a reference voltage from the reference voltage generating unit with a high input impedance. An impedance conversion circuit section for performing impedance conversion for sending out with low output impedance to output to the CR circuit section, and applying a constant current at a voltage higher than the reference voltage to the CR circuit section.
A constant current circuit unit for outputting to the circuit unit; and a voltage of the output terminal is detected, and one of the impedance conversion circuit unit and the constant current circuit unit is exclusively operated according to the detected voltage. An output voltage detection unit for operating the constant current circuit unit when the voltage of the output terminal is lower than the reference voltage, and an impedance conversion circuit when the voltage of the output terminal becomes the reference voltage. A reference voltage generating circuit for operating the unit. 2. The output voltage detecting section, when the voltage of the output terminal is less than a reference voltage, divides the reference voltage to generate and output a comparison reference voltage, and the voltage of the output terminal becomes a reference voltage. And a comparison reference voltage generation unit that outputs the reference voltage as the comparison reference voltage, and compares the voltage of the output terminal with the comparison reference voltage from the comparison reference voltage generation unit, and determines the impedance according to the comparison result. The reference voltage generation circuit according to claim 1, further comprising: a voltage comparison unit that controls operation of the conversion circuit unit and the constant current circuit unit. 3. The reference voltage generation circuit according to claim 2, wherein the comparison reference voltage generation section switches the comparison reference voltage according to a comparison result of the voltage comparison section. 4. The constant current circuit section supplies a predetermined constant current using a voltage higher than the reference voltage as a power supply, and outputs a current corresponding to a current from the constant current source to the CR circuit section. 4. The reference according to claim 1, further comprising: a current mirror circuit that outputs the current mirror circuit; and a control circuit that controls an operation of the current mirror circuit in accordance with an operation control from the output voltage detection unit. Voltage generation circuit. 5. The constant current circuit section includes: a resistance circuit that supplies a predetermined constant current using a voltage higher than the reference voltage as a power supply; and an operation control from the output voltage detection section. 4. The reference voltage generation circuit according to claim 1, further comprising: a control circuit that controls supply of the output current to the CR circuit unit. 6. A power supply provided between the output terminal and a positive power supply terminal to which a positive power supply voltage is applied and between a negative power supply terminal to which a negative power supply voltage is applied and the output terminal. 6. The reference voltage generation circuit according to claim 1, further comprising a protection circuit section including diodes for preventing application of a reverse voltage.