JP2002229444A - Block encryption and decryption circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of an easy tendency to cryptoanalysis of the 8-bit data at the top of ciphertext data heretofore in a cipher feeback mode (cipher CFB mode) of a block encryption (decryption) circuit using a common key. SOLUTION: The 8-bit data at the top of the plaintext (ciphertext) data is encrypted (decrypted) by the first encryption (decryption) circuit and the succeeding data of the 8-bit at the top is encrypted (decrypted) by the second encryption (decryption) circuit. Part of the encrypted (plaintext) data formed by the first encryption (decryption) circuit is set as the initial value of the second encryption (decryption) circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a block cipher technique using a common key.

[0002]

2. Description of the Related Art Conventionally, encryption technology has been contributing to society as an important basic technology for protecting various types of information, such as military confidentiality and trade secrets, as well as personal privacy information, and ensuring security. In recent years, the information infrastructure such as the Internet has been developed on a global scale and has entered a full-fledged advanced information society. It is well known that is being researched and developed.

[0003] Cryptographic techniques are broadly classified into a common key scheme and a public key scheme. Among them, the common key method uses a common key for encryption and decryption, and has the problem of having to manage the key and sharing the key secretly, but has the advantage of being able to encrypt or decrypt at high speed. Therefore, its application field is wide. Further, among the common key systems, a system called a block cipher system is widely adopted as a mainstream of commercial encryption. The block cipher is a cipher that divides a plaintext into character strings (blocks) of a fixed length and encrypts them with the same common key.

FIG. 3 shows a conventional block encryption circuit and a conventional decryption circuit defined in JIS X 5053, which is called an encryption feedback mode (encryption CFB mode). The block encryption circuit and the decryption circuit shown in FIG. 3 take in an input buffer 1 which takes in a plaintext data string input from a predetermined input means, extracts every 8 bits, and outputs plaintext data, and outputs every 8 bits from the input buffer 1. Encrypts the supplied plaintext data to 8
An encryption circuit 2 for outputting ciphertext data for each bit, and an output buffer 3 for sequentially storing and holding the ciphertext data output by the encryption circuit 2 and outputting the same as a ciphertext data string
And an input buffer 4 for taking in the ciphertext data string output from the output buffer 3 and extracting the ciphertext data every 8 bits and outputting the ciphertext data, and decrypting the ciphertext data supplied from the input buffer 4 every 8 bits. A decoding circuit 5 that outputs plaintext data for each bit, and an output buffer 6 that sequentially stores the plaintext data output by the decoding circuit 5 and outputs it as a plaintext data string.

The encryption circuit 2 has a key data register 7 for holding common key data having a predetermined bit length, and a 64-bit data fed back based on the common key data supplied from the key data register 7. A block encryption circuit 8 for generating a 64-bit block cipher by encrypting the data, a register 9 for holding the 64-bit block cipher output from the block encryption circuit 8, and a higher-order 64-bit block cipher held by the register 9. A register 10 for extracting and holding 8 bits, and a register 1 for holding 8 bits of plaintext data transferred from the input buffer 1
An exclusive OR operation is performed by performing an exclusive OR operation for each bit on the 8-bit plaintext data held by the register 11 and the 8-bit block cipher held by the register 10 to generate and output 8-bit ciphertext data. An OR circuit 12, a register 13 for holding the 8-bit ciphertext data from the exclusive OR circuit 12 and supplying the same to the output buffer 3, and storing the 8-bit ciphertext data supplied from the register 13; A shift register 14 (feedback buffer) that holds the 72-bit ciphertext data while sequentially shifting the stored 8-bit ciphertext data upward, and the upper 64 bits of the 72-bit ciphertext data held by the shift register 14. Register 1 that holds bits
The 64-bit data held in the register 15 is supplied to the block encryption circuit 8 as feedback data.

Further, the decryption circuit 5 decrypts 64-bit encrypted data, which will be described later, based on a key data register 16 for storing common key data having a predetermined bit length and the common key data supplied from the key data register 16. A block decoding circuit 17 for generating 64-bit block decoded data;
A register 18 for holding the 64-bit block decoded data output from the block decoding circuit 17;
A register 19 for extracting and holding bits; a register 20 for holding 8-bit ciphertext data transferred from the input buffer 4; and a 8-bit ciphertext data held by the register 20 and 8 held by the register 19. An exclusive OR circuit 21 that performs an exclusive OR operation on the bit block decoded data for each bit to decode and output 8-bit plaintext data, and holds the plaintext data supplied from the exclusive OR circuit 21. A register 22 for supplying to the output buffer 6, storing the 8-bit ciphertext data supplied from the register 20, and shifting the stored 8-bit ciphertext data upward in order to convert the 72-bit ciphertext data. The shift register 23 held therein and the upper 64 bits of the 72-bit ciphertext data held by the shift register 23. And a register 24 for holding,
The 64-bit encrypted data held by the register 24 is supplied to the block decryption circuit 17.

The conventional encryption / decryption circuit shown in FIG. 3 operates as follows. First, the operation of the encryption circuit 2 will be described. When the encryption circuit 2 starts, the upper 64 bits of the shift register 14 are set to a predetermined initial value.
Next, the upper 64 data initially set in the shift register 14 are stored.
Transfer the bits to register 15. Block encryption circuit 8
Encrypts the 64-bit data held in the register 15 with key data of a predetermined bit length supplied from the key data register 7 to generate a 64-bit block cipher and transfer it to the register 9. Then, the register 9 stores the
And extracts and holds the upper 8 bits of the 64-bit block cipher held.

On the other hand, 8 bits of plaintext data are input to the input buffer 1 from input means not shown in FIG. Then, the input buffer 1 transfers this to the register 11 by 8 bits and deletes it. Therefore, the exclusive OR circuit 12
Performs an exclusive OR operation on each of the 8-bit plaintext data transferred to the register 11 and the 8-bit block cipher held in the register 10 to generate 8-bit ciphertext data. This is held in the register 13 and transferred to the output buffer 3. Output buffer 3
Supplies the 8-bit ciphertext data to the output means and deletes it.

Next, the register 13 transfers the 8-bit ciphertext data to the lower 8 bits of the shift register 14. Then, the shift register 14 shifts the transferred 8-bit ciphertext data upward by 8 bits. Here, as a result of shifting the upper 64 bits of the shift register 14 by 8 bits in the upper direction, the upper register 64 changes from the initial value to a new value. This is held in a register 15, block-encrypted by a block encryption circuit 8, held in a register 9, and the upper 8 bits are held in a register 10. When new 8-bit plaintext data is input from the input means to the input buffer 1 and transferred to the register 11, similarly,
The exclusive OR circuit 12 operates on 0 and the 8-bit data of the register 11 to generate and output 8-bit ciphertext data.

The register 13 transfers the 8-bit ciphertext data supplied from the exclusive logic circuit 12 to the output buffer 3 again and to the shift register 2. The output buffer 3 outputs the 8-bit ciphertext data again to the output means and deletes it. The shift register 14 shifts the transferred 8-bit ciphertext data upward by 8 bits again. By sequentially repeating the above-described operations, the plaintext data input from the input unit is sequentially encrypted every 8 bits, and the output buffer 3 supplies the 8-bit encrypted data to the output unit.

Next, the operation of the decoding circuit 5 will be described. When the decoding circuit 5 starts, the upper 64 bits of the shift register 23 are set to a predetermined initial value. Here, the initial value is the same value as the initial value set in the shift register 23. Therefore, the upper 64 bits initially set in the shift register 23 are transferred to the register 24. Then, the block decoding circuit 17 stores the 64
The bit data is decrypted with key data of a predetermined bit length supplied from the key data register 16 to output 64-bit block decrypted data. The key data held in the key data register 16 is exactly the same as the key data held in the key data register 7, and the block decryption circuit 17 performs the same operation as the block encryption circuit 8.

On the other hand, the ciphertext data generated by the encryption circuit 2 is supplied to the input buffer 4 via the input means. Then, the input buffer 4 deletes the data after transferring it to the register 20 by 8 bits. Therefore, the exclusive OR circuit 21 performs an exclusive OR operation for each bit of the 8-bit ciphertext data transferred to the register 20 and the 8-bit block decrypted data held in the register 19, and performs an 8-bit operation. Generate and output plaintext data. This is held in the register 22 and transferred to the output buffer 6. The output buffer 6 deletes the 8-bit plaintext data after supplying it to the output means separately.

Next, the register 20 transfers the 8-bit ciphertext data to the lower 8 bits of the shift register 23. Then, the shift register 23 shifts the transferred 8-bit ciphertext data upward by 8 bits. Here, as a result of shifting the upper 64 bits of the shift register 23 by 8 bits in the upper direction, the upper 64 bits are further changed to a new value. This is held in the register 24, block-decoded by the block decoding circuit 17, held in the register 18, and held in the register 19 in the upper 8 bits.
Then, when 8-bit ciphertext data is newly input from the input means to the input buffer 1 and transferred to the register 20, the 8-bit data of the register 19 and the register 20 is similarly operated by the exclusive OR circuit 21 to newly generate 8 bits. Generate and output plaintext data.

The register 22 supplies the 8-bit plaintext data supplied from the exclusive logic circuit 21 to the output buffer 22 again, and the output buffer 6 outputs the 8-bit ciphertext data to the output means again and deletes it. The shift register 23
Shifts the 8-bit ciphertext data transferred from the register 20 upward by 8 bits. When the above-described operations are sequentially repeated, the ciphertext data input from the input unit is sequentially decoded every 8 bits, and the output buffer 6 supplies the 8-bit plaintext data to the output unit.

[0015]

However, the conventional encryption / decryption circuit has the following problems. That is, when the encryption / decryption circuit is activated, the shift register 1
The upper 64 bits of 4 are preset to a predetermined initial value. Therefore, this is stored in the register 15 and encrypted by the block encryption circuit 8, so that the first 6
As for the 4-bit output data, only a certain fixed value is output. Therefore, the first 8-bit data held in the register 10 also has a certain value (hereinafter, referred to as the register 10 initial holding value), and the register 10 initial holding value and the plaintext held in the register 11 (input buffer 1) are stored. The result obtained by calculating the leading 8-bit data by the exclusive OR circuit 12 is obtained as the leading 8-bit ciphertext data. Therefore, immediately after the start of the encryption / decryption circuit, the first 8-bit data held in the input buffer 1 and the output buffer 1
By acquiring the leading 8-bit data output to 3,
The contents of the initial holding value of the register 10 can be obtained by a simple logical operation. As a result, there arises a problem that immediately after the activation of the encryption circuit, the first 8 bits of the ciphertext data string can be easily decrypted using the obtained initial holding value of the register 10.

In order to avoid this problem, preamble data of 8 bits is added to the head of the plaintext data string input from the input means so that there is no problem even if the head 8 bits are decoded, or 64 bits are used. Is encrypted by a separate means, and this is externally transferred to the shift register 14,
Alternatively, the key data held in the key data registers 7 and 16 may be updated at random, or the key data held in the key data registers 7 and 16 may be updated irregularly so that the initial held value of the register 10 differs depending on the time of encryption. Has been adopted.

However, the method of adding a preamble is such that unnecessary data is added to the head to change the data size, the method of encrypting 64-bit data and setting it to an initial value is also a method of storing 64-bit data. There is a problem that a problem occurs and the encryption circuit itself becomes considerably complicated. In addition, the method of updating the encryption key is also an effective method because the key data must be downloaded from the outside each time the update is performed, and another problem such as a method of storing the updated key data occurs separately. Absent.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. The present invention provides a block encryption / decryption circuit in a cryptographic feedback mode having a high cryptographic strength, which can prevent the first 8 bits of ciphertext data from being decrypted. The purpose is to provide.

[0019]

In order to solve the above-mentioned object, a block encryption / decryption circuit according to the present invention is characterized in that a predetermined bit is sequentially extracted from a plaintext data string and encrypted. A first encryption circuit, a second encryption circuit, an input switching unit, and an output switch in an encryption feedback mode (encryption CFB mode) of a common key block encryption circuit that generates and outputs a ciphertext data sequence for each predetermined bit. Means for selecting a predetermined bit at the head of the plaintext data string by the input switching means and encrypting the selected bit at the first encryption circuit; A bit string following a predetermined bit is selected by the input switching means and encrypted by the second encryption circuit, and the ciphertext data obtained by the first encryption circuit and the ciphertext data obtained by the second encryption circuit are obtained. And the ciphertext data selected and output by the output switching means, wherein the first encryption circuit includes a first key data register for generating common key data, and a first key data register based on the common key data. A first block encryption circuit for generating a block cipher having a predetermined bit length, and performing an exclusive OR operation on an upper predetermined bit extracted from the first block cipher and a predetermined bit extracted from the plaintext data string to perform encryption; A first exclusive logic circuit for generating and outputting text data, and storing and holding the ciphertext data supplied from the first exclusive logic circuit while sequentially shifting the ciphertext data by a predetermined bit to a higher order; A first shift register (feedback buffer) for feeding data back to the first block encryption circuit, wherein the second encryption circuit uses a common key A second key data register for generating a data, a second block encryption circuit for generating a block cipher of a predetermined bit length based on the second common key data, and upper predetermined bits extracted from the block cipher. A second exclusive-OR circuit for performing exclusive-OR operation on the data and a predetermined bit extracted from the plaintext data string to generate and output ciphertext data; and a cipher supplied from the second exclusive-OR circuit. A second shift register (feedback buffer) for storing and holding the sentence data while sequentially shifting the sentence data upward, and for feeding back the held ciphertext data to the second block encryption circuit;
Transferring the ciphertext data held in the first shift register to the second encryption circuit in the process of generating the ciphertext data in the first encryption circuit, Are set as the initial values of the shift register.

According to a second aspect of the present invention, there is provided a decryption circuit for decrypting a ciphertext data sequence obtained by the encryption circuit according to the first aspect of the present invention for each predetermined bit, The decryption circuit includes a first decryption circuit, a second decryption circuit, an input switching unit, and an output switching unit. The first predetermined bit of the ciphertext data string is selected by the input switching unit, and the first switching is performed. While decoding by the decoding circuit,
A bit string following a predetermined bit at the head of the ciphertext data string is selected by the input switching means and decrypted by the second decryption circuit, and the plaintext data obtained by the first decryption circuit and the second decryption are obtained. 2. The first key data register according to claim 1, wherein the plaintext data obtained by the circuit is selected and output by the output switching means, and wherein the first decryption circuit generates common key data. A first block decryption circuit for decrypting a block cipher having a predetermined bit length based on the common key data;
A first exclusive logic circuit for performing an exclusive OR operation on upper predetermined bits of the decrypted data decrypted from the first block decryption circuit and predetermined bits extracted from the ciphertext data string to generate and output plaintext data; A first shift register that stores and holds the ciphertext data sequence while shifting the ciphertext data sequence upward by a predetermined bit sequentially and supplies the held ciphertext data to the first block decryption circuit; 2. The second key data register according to claim 1, wherein the second decryption circuit generates common key data, and a second block decryption circuit that decrypts a block cipher having a predetermined bit length based on the second common key data. And exclusive OR operation of upper predetermined bits of the decrypted data decrypted from the block decryption circuit and predetermined bits extracted from the ciphertext data string to generate plaintext data. A second exclusive logic circuit for storing and holding the ciphertext data sequence while sequentially shifting the ciphertext data sequence upward by a predetermined bit, and supplying the held ciphertext data to the second block decryption circuit. A shift register, and transferring the ciphertext data held in the first shift register to the second decryption circuit in a process of generating plaintext data in the first decryption circuit;
This is set as the initial value of the second shift register.

According to a third aspect of the block encryption / decryption circuit according to the present invention, in the block encryption circuit according to the first aspect, the first block encryption circuit is replaced by the second block encryption circuit. It was used in combination. According to a fourth aspect of the block encryption / decryption circuit according to the present invention, in the block decryption circuit according to the second aspect, the second block decryption circuit is used in combination with the first block decryption circuit. .

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on illustrated embodiments. 1 and 2 show block diagrams of an embodiment of a block encryption / decryption circuit according to the present invention. FIG. 1 shows an encryption circuit, and FIG.
Shows a block diagram of a decoding circuit. The block cipher circuit shown in FIG. 1 includes an input buffer 1 which takes in a plaintext data sequence input from a predetermined input means, extracts every 8 bits, and outputs plaintext data, an input terminal, a first output terminal, and a first output terminal. Input switching means 25 having two output terminals for selectively outputting the plaintext data supplied from the input buffer 1
A shift register 26 which takes in and holds the first 8 bits of the plaintext data selectively supplied from the first output terminal of the input switching means 25 one bit at a time, and a first 8 bits of the plaintext data held by the shift register 26. A first encryption circuit 27 for encrypting one bit at a time, and a second encryption circuit for encrypting the subsequent eight bits of the first eight bits of the plaintext data supplied from the second output terminal of the input switching means 25 at a time. An encryption circuit 28 and the first encryption circuit 27;
The shift register 29 stores the ciphertext data output by the first bit by one bit and holds the 8-bit ciphertext data, and outputs the 8-bit ciphertext data held by the shift register 29 and the second encryption circuit 28. An output switching unit 30 for selecting and outputting 8-bit ciphertext data, an output buffer 3 for holding the ciphertext data supplied from the output switching unit 30, an output switching unit 28 and an input switching unit 25. A control unit 31 for controlling the switching operation.

The first encryption circuit 27 includes a key data register 32 for holding common key data having a predetermined bit length,
Based on the common key data supplied from the key data register 32, a block encryption circuit 33 for encrypting 64-bit data fed back, which will be described later, to generate a 64-bit block cipher, and outputs the block encryption circuit 33. Register 34 for holding 64-bit block cipher
A register 35 for extracting and holding the upper 1 bit of the 64-bit block cipher held by the register 34; a register 36 for holding plaintext data supplied bit by bit from the shift register 26; 1-bit plaintext data and 1 held by the register 35
An exclusive OR circuit 37 that performs an exclusive OR operation on the bit block cipher data and outputs 1-bit ciphertext data, and holds the 1-bit ciphertext data output by the exclusive OR circuit 37. A register 38 to be supplied to the shift register 29, and a shift for storing the 1-bit ciphertext data output from the register 38 and holding the 65-bit ciphertext data while sequentially shifting the stored 1-bit ciphertext data upward. A register 39 (feedback buffer); and a register 40 for storing upper 64 bits of the 65-bit ciphertext data held by the shift register 39. The 64-bit data held by the register 40 is stored in the block encryption circuit 33. As feedback data.

Further, the second encryption circuit 28 has a key data register 41 for storing common key data having a predetermined bit length,
Based on the common key data supplied from the key data register 41, a block encryption circuit 42 for encrypting feedback 64-bit data, which will be described later, to generate a 64-bit block cipher, and outputs the block encryption circuit 42. Register 43 for holding 64-bit block cipher
A register 44 for extracting and holding the upper 8 bits of the 64-bit block cipher held by the register 43; a register 45 for holding the 8-bit plaintext data supplied from the input switching means 25; The exclusive-OR operation is performed on the 8-bit plaintext data to be performed and the 8-bit block cipher data held by the register 44 to obtain
Exclusive OR circuit 46 for outputting bit ciphertext data
And a register 47 for holding the 8-bit ciphertext data output from the exclusive OR circuit 46 and supplying it to the output switching means 30; and storing and storing the 8-bit ciphertext data output from the register 47. A shift register 48 (feedback buffer) for holding the 72-bit ciphertext data while sequentially shifting the 8-bit ciphertext data in the upper direction;
A register 49 for holding upper 64 bits of the 2-bit ciphertext data;
The bit data is supplied to the block encryption circuit 42 as feedback data.

The upper 64 bits of data held by the shift register 39 are transferred to the upper 64 bits of the shift register 48 via the control section 31. The timing and the switching timing of the input switching means 25 and the output switching means 30 are controlled.

On the other hand, the block decoding circuit shown in FIG.
An input buffer 1 for taking in a ciphertext data string input from a predetermined input means, extracting the ciphertext data every 8 bits, and outputting ciphertext data, and having an input terminal, a first output terminal, and a second output terminal. An input switching means 50 for selectively outputting the ciphertext data supplied from the input buffer 1; a shift register 51 for holding the leading 8-bit ciphertext data selectively supplied from the first output terminal of the input switching means 50; A first decryption circuit 52 that decrypts the leading 8-bit ciphertext data held by the shift register 51 bit by bit;
A second decryption circuit 53 for decrypting the subsequent data of the 8-bit ciphertext data supplied from the second output terminal of the input switching means 51 in 8-bit units, and the first decryption circuit 52 outputs. Stores plaintext data one bit at a time
A shift register 54 holding bit plaintext data;
Output switching means 55 for selecting and outputting 8-bit plaintext data held by the shift register 54 and 8-bit plaintext data output by the second decoding circuit 53, and plaintext supplied from the output switching means 55 An output buffer 6 for holding data and a control unit 56 for controlling the switching operation of the output switching means 55 and the input switching means 50 are provided.

The first decryption circuit 52 decrypts 64-bit data described later on the basis of the key data register 57 for storing common key data of a predetermined bit length and the common key data supplied from the key data register 57. A block decoding circuit 58 for generating 64-bit decoded data, a register 59 for holding the 64-bit decoded data output from the block decoding circuit 58,
A register 60 for extracting and holding the upper one bit of the 4-bit decrypted data, a register 61 for holding the ciphertext data supplied bit by bit from the shift register 51, and a 1-bit ciphertext data held by the register 61 An exclusive-OR circuit 62 for performing an exclusive-OR operation on the 1-bit decoded data held by the register 60 and outputting 1-bit plaintext data; and a 1-bit plaintext output by the exclusive-OR circuit 62 Shift register 5 for holding data
4 for storing the 1-bit ciphertext data held by the register 61,
A shift register 64 for holding 65-bit plaintext data while sequentially shifting the bit ciphertext data upward.
And a register 65 for holding the upper 64 bits of the 65-bit ciphertext data held by the shift register 64. The 64-bit data held by the register 65 is supplied to the block decryption circuit 58.

Further, the second decryption circuit 53 decrypts 64-bit data described later based on the key data register 66 for storing common key data of a predetermined bit length and the common key data supplied from the key data register 66. A block decoding circuit 67 for generating 64-bit decoded data, a register 68 for holding 64-bit decoded data output from the block decoding circuit 67,
A register 69 for extracting and holding the upper 8 bits of the 4-bit decrypted data, a register 70 for holding the 8-bit ciphertext data supplied from the input switching means 50, and an 8-bit ciphertext data held by the register 70 And an exclusive OR circuit 71 for performing an exclusive OR operation on the 8-bit decoded data held in the register 69 and outputting 8-bit plaintext data, and 8 output from the exclusive OR circuit 71.
A register 72 for storing bit plaintext data and supplying it to the output switching means 55; and a 72-bit ciphertext for storing the 8-bit ciphertext data held by the register 70 and sequentially shifting the stored 8 bits upward. Shift register 73 for holding the sentence data, and the upper 6 bits of the 72-bit ciphertext data held by the shift register 73.
A register 74 for holding 4 bits, and the 64-bit data held by the register 74 is supplied to a block decoding circuit 67.

The upper 64 bits of data held by the shift register 64 are transferred to the upper 64 bits of the shift register 73 via the controller 56, and the controller 56 transfers the data of the shift register 51 to the upper 64 bits. The timing and the switching timing of the input switching means 50 and the output switching means 55 are controlled.

Here, the key data register 32 and the key data register 57 have exactly the same key data, and the key data register 41 and the key data register 66 have exactly the same key data. Further, the block encryption circuit 33 and the block decryption circuit 58 perform exactly the same operation, and the block encryption circuit 42 and the block decryption circuit 67 perform exactly the same operation.

The operation of the block encryption / decryption circuit according to the present invention shown in FIGS. 1 and 2 will be described below. First, the operation of the encryption circuit of FIG. 1 will be described. When the encryption circuit starts, the upper 64 bits of the shift register 39 in the first encryption circuit 27 are set to a predetermined initial value. Next, the upper 64 bits initially set in the shift register 39 are transferred to the register 40. The block encryption circuit 33 encrypts the 64-bit data held in the register 40 with key data having a predetermined bit length supplied from the key data register 32, outputs a 64-bit block cipher, and transfers the block cipher to the register. And the register 34
Transfers the upper 8 bits of the held 64-bit block cipher to the register 35.

On the other hand, the first 8 bits of the plaintext data are input to the input buffer 1 from input means not shown in FIG.
Then, the input buffer 1 deletes the first 8 bits after transferring them to the input switching means 25. Input switching means 25
Selects the transmitted 8-bit ciphertext data, and
And output to the shift register 26. Further, the shift register 26 transfers the least significant one bit of the 8-bit plaintext data held by the control unit 31 to the register 36 and shifts the held eight bits by one bit in the lower direction. The exclusive OR circuit 37 performs an exclusive OR operation on the 1-bit plaintext data held in the register 36 and the 1-bit block cipher held in the register 35 to generate and output 1-bit ciphertext data. . This is held in the register 38 and transferred to the most significant bit of the shift register 29. Then, the shift register 29 shifts this by one bit in the lower direction and holds it.

Next, the 1-bit ciphertext data held in the register 38 is transferred to the least significant bit of the shift register 39. Then, the shift register 39 shifts this one bit upward. Here, as a result of shifting the upper 64 bits of the shift register 39 by one bit in the upper direction, the upper 64 bits are changed from the initial value to a new value. This is held in the register 40 and the block encryption circuit 3
Supply 3 The block encryption circuit 33 encrypts this based on the key data supplied from the key data register 32 to generate a 64-bit block cipher. Then, it is held in the register 34 and the upper one bit is held in the register 35.
Further, when the next plaintext data for one bit is input from the least significant bit of the shift register 26 and transferred to the register 36,
Similarly, the exclusive OR circuit 37 operates the 1-bit data held in the registers 35 and 36, respectively, and
Generates and outputs bit ciphertext data.

The register 38 converts the 1-bit ciphertext data supplied from the exclusive logic circuit 37 into the shift register 2 again.
9 and the shift register 3
9 to the least significant bit. The shift register 29 shifts this by one bit in the lower direction and stores and holds it, and the shift register 39 shifts it by one bit in the upper direction and stores and holds it. Up to this point, the shift register 29 holds the ciphertext data of the first two bits.

When the above-described operations are sequentially repeated, the plaintext data supplied bit by bit from the shift register 26 is encrypted bit by bit, and the shift register 2
Reference numeral 9 stores and holds 8-bit ciphertext data. Then, this is output to the output buffer 3 via the output switching means 30.
To hold. So far, the process of sequentially encrypting the first 8 bits of the plaintext data one bit at a time has been described.

Next, a process of encrypting the subsequent data of the first 8 bits will be described. First, the first encryption circuit 2
7, the encryption of the head 8-bit plaintext data is completed, the head 8-bit ciphertext data is output from the output buffer 3 to the output means, and the data held in the output buffer 3 is deleted. Next, the upper 6
The 4-bit data is transferred to the upper 64 bits of the shift register 48 via the control unit 31 and set as an initial value. And
The input means supplies the subsequent 8-bit plaintext data to the input buffer 1. The input buffer 1 uses this as input switching means 2
5 and then deleted. The input switching means 25 transfers the supplied 8-bit plaintext data from the second output terminal to the register 4.
Transfer to 5.

On the other hand, the initial value of the upper 64 bits held in the shift register 48 is held in the register 49, and this is input to the block encryption circuit 42 and is inputted to the key data register 41.
Is encrypted based on the key data held by. Then, the generated 64-bit block cipher is held in the register 43, and the upper 8 bits are extracted and held in the register 44. The exclusive-OR circuit 46 performs an exclusive-OR operation on the 8-bit block cipher held in the register 44 and the 8-bit plaintext data held in the register 45 for each bit, thereby obtaining 8-bit ciphertext data. Is output to the register 47.

The register 47 outputs the 8-bit ciphertext data supplied from the exclusive OR circuit 46 to the output switching means 30.
To supply. The output switching means 30 selects this according to the control unit 31 and supplies it to the output buffer 3. Then, the output buffer 3 supplies the held 8-bit ciphertext data to the output unit and deletes it. Next, the register 47 transfers the held 8-bit ciphertext data to the shift register 48. The shift register 47 stores and holds this while shifting it by 8 bits in the upper direction. This is stored in the register 49 and the block encryption circuit 42 performs block encryption. This is held in the register 43, and the upper 8 bits are held in the register 44.

Then, new 8-bit plaintext data is supplied from the input means to the input buffer 1 and transferred to the register 45 from the second output terminal of the input switching means 25.
The exclusive OR circuit 46 stores the 8-bit plaintext data newly stored in the register 45 and the 8-bit plaintext data newly stored in the register 44.
The exclusive OR operation is performed on the bit block cipher, and 8-bit ciphertext data is output and supplied to the register 47. The register 47 holds this, supplies it to the output buffer 6 via the output switching circuit 30, and transfers it to the shift register 48. After outputting this to the output means, the output buffer 3 deletes the held data.

By repeating the above processing, the plaintext data following the first 8 bits encrypted by the first encryption circuit 27 and the subsequent plaintext data are sequentially encrypted by the second encryption circuit 28 in units of 8 bits. The ciphertext data string is output from the buffer 3 to the output means.

Next, the process of decrypting the ciphertext data generated in FIG. 1 will be described. The decrypting process is similar to the encrypting process in that the leading 8-bit ciphertext data supplied from the input means to the input buffer 4 in FIG.
The signal is supplied to the first decoding circuit 52 via the "0" and is decoded bit by bit. Further, the succeeding data of the ciphertext data of the first 8 bits is supplied to the second decryption circuit 53 via the input switching means 50, and the second decryption circuit 53 decrypts the data by 8 bits. As described above, the ciphertext data input from the input means is processed by the first decryption circuit 52 and the second decryption circuit 53, and the decrypted plaintext data is supplied from the output buffer 6 to the output means. Note that the first decoding circuit 52 and the second decoding circuit 5
The operation 3 is exactly the same as the first encryption circuit 27 and the second encryption circuit 28 except that data is transferred from the registers 61 and 70 to the shift registers 64 and 73, respectively. Detailed description is omitted.

As described above, the first 8 bits of the plaintext data are encrypted one bit at a time by the first encryption circuit 27, and the encrypted data generated by the first encryption circuit 27 is encrypted by the second encryption circuit 28. Is set as a part of the initial value of the shift register 48, the first 8-bit data encrypted by the second encryption circuit 28 becomes different data every time. Obtaining information makes it impossible to decode the first 8 bits. In the first encryption circuit 27, a fixed value is set as an initial value in the upper 64 bits of the shift register 39, and encryption is performed one bit at a time. Can be decoded, but the subsequent 7 bits cannot be decoded, so that a sufficient effect can be obtained to solve the problem that the first 8 bits could be decoded conventionally.

In the block encryption / decryption circuit described above, the plaintext data is encrypted one bit at a time in the first encryption circuit 27, and the plaintext data is decrypted one bit at a time in the first decryption circuit 52. The invention is not limited to this. For example, the first encryption circuit 27 and the first
In the decryption circuit 52, encryption and decryption may be performed in units of 2 bits or 4 bits. In this case, the encrypted first 8
Of the bits, the first two bits or four bits are more likely to be decrypted, so the encryption strength is lower than in the embodiment described above. However, the leading eight bits are encrypted two or four bits at a time. You could save time.

Further, in the second encryption circuit 28 and the second decryption circuit 53, 8 bits are processed at a time.
The present invention is not limited to this, and the number of bits to be processed can be further increased. In consideration of the interface with the input means or the output means, the method of processing every 8 bits (1 byte) or a multiple thereof is the easiest to handle in data processing.

Further, the first encryption circuit and the second encryption circuit may be shared by any one of the encryption circuits. For example, even if the register 39 is changed to a 72-bit register in the first encryption circuit 27, the first 8 bits can be encrypted in the same manner. Therefore,
In the second encryption circuit, first, the first 8 bits are encrypted one bit at a time, and the subsequent data are encrypted eight bits at a time. At this time, the shift amount of the shift register 48 is set so that it can be set to either 1 bit or 8 bits. This eliminates the need to transfer the upper 64 bits from the shift register 39 of the first encryption circuit 27 to the second encryption circuit 28. Further, it goes without saying that peripheral circuits such as the input switching means 25 and the output switching means 30 are not required, and the circuit scale can be considerably reduced. Similarly, the first decoding circuit 52 and the second decoding circuit 53 can be shared by any one decoding circuit.

[0046]

As described above, according to the present invention, the first eight bits of the plaintext data are encrypted by the first encryption circuit in the encryption feedback mode (encryption CFB mode) of the block encryption circuit using the common key. And the second encryption circuit encrypts the leading 8-bit subsequent data, and sets a part of the encrypted data generated by the first encryption circuit as an initial value of the second encryption circuit. The setting makes it possible to solve the problem that the leading 8-bit data of the plaintext data is easily deciphered, and to provide a block encryption / decryption circuit using a common key system having a high encryption strength.

[0047]

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a block encryption circuit according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a block decoding circuit according to the present invention.

FIG. 3 is a block diagram showing an embodiment of a conventional block encryption / decryption circuit.

[Explanation of symbols]

1, 4 ... input buffer 2 ... encryption circuit 3, 6 ... output buffer 5 ... decryption circuit 7, 16, 32, 41, 57, 66 ... key data register 8, 33, 42 ... Block encryption circuit 9, 10, 11, 13, 15, 18, 19, 20, 2
2, 24, 34, 35, 36, 38, 40, 43, 4
4, 45, 47, 49, 59, 60, 61, 63, 6
5, 68, 69, 70, 72, 74 ... registers 12, 21, 37, 46, 62, 71 ... exclusive OR circuits 14, 23, 26, 29, 39, 48, 64, 73・ ・
Shift register 17, 58, 67 ... block decryption circuit 25, 50 ... input switching means 27 ... first encryption circuit 28 ... second encryption circuit 30, 55 ... output switching Means 31, 56 Control unit 52 First decoding circuit 53 Second decoding circuit

Claims (4)

[Claims] In a cryptographic feedback mode (encryption CFB mode) of a common key type block encryption circuit for sequentially extracting and encrypting a predetermined bit from a plaintext data string and generating and outputting a ciphertext data string for each predetermined bit. A first encryption circuit, a second encryption circuit, an input switching unit, and an output switching unit, wherein the input switching unit selects a predetermined bit at the head of the plaintext data string, and While encrypting by the first encryption circuit, a bit string following a predetermined bit at the head of the plaintext data string is selected by the input switching means and encrypted by the second encryption circuit,
The ciphertext data obtained by the first encryption circuit and the ciphertext data obtained by the second encryption circuit are selected and output by the output switching means, respectively, An encryption circuit configured to generate a first key data register that generates common key data, a first block encryption circuit that generates a block cipher having a predetermined bit length based on the common key data, and A first exclusive logic circuit for performing an exclusive OR operation on the extracted upper predetermined bits and the predetermined bits extracted from the plaintext data string to generate and output ciphertext data; and a first exclusive logic circuit. The first cipher data is stored and held while sequentially shifting the cipher text data to be shifted upward by a predetermined bit, and the held cipher text data is fed back to the first block encryption circuit. A second key data register for generating common key data; and a block cipher having a predetermined bit length based on the second common key data. A second block encryption circuit that performs an exclusive OR operation on upper predetermined bits extracted from the block cipher and predetermined bits extracted from the plaintext data string to generate and output ciphertext data An OR circuit and storing and holding the ciphertext data supplied from the second exclusive OR circuit while sequentially shifting the ciphertext data upward, and feeding back the held ciphertext data to the second block encryption circuit. And a second shift register (feedback buffer) for supplying ciphertext data in the first encrypting circuit. Transfer the encrypted data held in the shift register to said second encryption circuit, block encryption, characterized in that it has been set as the initial value of the shift register of the second, decoding circuit. 2. A decryption circuit for decrypting a ciphertext data sequence obtained by the encryption circuit according to claim 1 for each predetermined bit, wherein said decryption circuit has a first decryption circuit, a second decryption circuit, and an input. Switching means and output switching means, wherein the input switching means selects a predetermined bit at the head of the ciphertext data string, decrypts the selected bit at the first decryption circuit, and sets a predetermined bit at the head of the ciphertext data string. Is selected by the input switching means and decoded by the second decoding circuit, and the plaintext data obtained by the first decoding circuit and the plaintext data obtained by the second decoding circuit are The first decryption circuit is selected and output by an output switching unit, and the first decryption circuit generates common key data.
A first key data register, a first block decryption circuit for decrypting a block cipher having a predetermined bit length based on the common key data, and upper predetermined bits of decrypted data decrypted from the first block decryption circuit And a first exclusive logical circuit for generating and outputting plaintext data by performing an exclusive OR operation on the predetermined bits extracted from the ciphertext data sequence and a predetermined exclusive bit. And a first shift register that stores and holds the ciphertext data and supplies the held ciphertext data to the first block decryption circuit, wherein the second decryption circuit generates common key data.
And a second key data register for decrypting a block cipher having a predetermined bit length based on the second common key data.
And a second exclusive OR operation for performing an exclusive OR operation on upper predetermined bits of the decrypted data decrypted from the block decryption circuit and predetermined bits extracted from the ciphertext data string to generate and output plaintext data A logic circuit, and a second shift register that stores and holds the ciphertext data sequence while shifting the ciphertext data sequence upward by a predetermined bit sequentially and supplies the held ciphertext data to the second block decryption circuit. Transferring the ciphertext data held in the first shift register to the second decryption circuit in the process of generating the plaintext data by the first decryption circuit, and transferring the encrypted data to the initial value of the second shift register; A block encryption / decryption circuit characterized by being set as: 3. The block encryption circuit according to claim 1, wherein said second block encryption circuit is used in combination with said first block encryption circuit. Decoding circuit. 4. The block encryption / decryption circuit according to claim 2, wherein said second block decryption circuit is used in combination with said first block decryption circuit. .