JP2002228723A - Semiconductor integrated circuit and inspecting method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform an inspection with one test pattern in the case where flip-flop circuits to be operated with a positive phase clock and a negative phase clock exist together. SOLUTION: This semiconductor integrated circuit is provided with a selector circuit 421 for selecting any one of a clock signal and a reverse clock signal obtained by reversing the clock signal to supply it to a flip-flop circuit. When the selector circuit 421 selects the clock signal, a logic circuit 412 connected to a former stage of the flip-flop circuits 401, 403 to be operated by the positive phase clock is inspected. When the selector circuit 421 selects the reverse clock signal, a logic circuit 411 connected to a former stage of the flip-flop circuits 402 and 404 to be operated by the negative phase clock is inspected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method for inspecting a semiconductor integrated circuit, and more particularly, to a method for testing a semiconductor integrated circuit.
The present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit inspection method capable of reducing the number of inspection steps and inspection time in a scan-designed semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a process of manufacturing a semiconductor integrated circuit, a method of inputting a test pattern prepared in advance and diagnosing whether a predetermined output is obtained or not is known as a method for inspecting a defect in the circuit. ing. When this method is used, scan design is performed in which part or all of the flip-flop circuit is replaced with a scan flip-flop circuit in order to externally set or read the value of the flip-flop circuit in the circuit. I have.

In a scan-designed semiconductor integrated circuit,
Each scan flip-flop circuit is connected by a scan chain. In the scan test, a clock is simultaneously supplied to each scan chain, and scan-in / scan-out of a test pattern is performed for diagnosis.

On the other hand, in a semiconductor integrated circuit, in order to reduce power consumption, clock supply to unused circuits is stopped, and power consumption is reduced by reducing the number of circuit blocks that operate simultaneously. In such a semiconductor integrated circuit, when the above-described scan test is performed, circuit destruction or the like occurs due to an increase in power consumption.
An inspection method described in JP-197603-A is performed. In other words, group scan chains,
By selectively supplying a shift operation clock for each group, the number of scan flip-flop circuits that operate simultaneously can be reduced.

[0005]

However, a semiconductor integrated circuit is designed by combining a flip-flop circuit that operates with a positive-phase clock and a flip-flop circuit that operates with a negative-phase clock. Therefore, when a scan test using a scan chain is performed, two types of test patterns corresponding to the phase of the clock are required, and there is a problem that the number of inspection steps and the inspection time increase.

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit using a conventional scan chain. The flip-flop circuits 101 and 103 that operate on the positive-phase clock are Scan
An example is shown in which In1-ScanOut1 is connected to the same scan chain as flip-flop circuits 102 and 104 operated by the opposite phase clock to ScanIn0-ScanOut0.

The outputs PP0 and PP1 of the flip-flop circuits 101 and 103 are connected to a logic circuit 111, and the outputs of the logic circuit 111 are output to the flip-flop circuits 102 and 1 respectively.
04 is connected to the input. Flip-flop circuit 1
Outputs NN0 and NN1 of the logic circuits 112 and
The output of the logic circuit 112 is fed back and connected to the inputs of the flip-flop circuits 101 and 103.

[0008] The flip-flop circuits 101 to 104
When the signal ScanE for performing the scan operation = 1, a serial data string is input for each ScanCLK from the ScanIn input, and desired data is set in a flip-flop circuit of a scan chain connected like a shift register. this,
It is called shift operation. When ScanE = 0, normal operation is performed by ScanCLK input.

FIG. 2 is a time chart showing a conventional method for testing a flip-flop circuit operated by a normal phase clock of a semiconductor integrated circuit. Figure 2 shows that during ScanE = 0,
This is a case where the clock signal CLK changes in the order of rising and falling.
It is called S pattern.

When ScanE = 1, "A", "B" from ScanIn1
Scan pattern, and flip-flop circuits 103, 1 each operating with a positive-phase clock
Set to 01. When ScanE = 0, the rising edge of the clock signal CLK causes “A” and “B” to be set in the subsequent logic circuit 11.
1, the output “M” of the preceding logic circuit 112,
“N” is set to the outputs PP1 and PP0 of the flip-flop circuits 103 and 101. When ScanE = 1 again, the outputs “M” and “N” of the logic circuit 112 are scanned out, and the next test patterns “E” and “F” are scanned in. Thus, the POS pattern is
Used for testing the logic circuit 112.

FIG. 3 is a time chart showing a method for testing a flip-flop circuit of a conventional semiconductor integrated circuit which operates with an inverted clock. Fig. 3 shows that ScanE = 0
This is a case where the clock signal CLK changes in the order of falling and rising, and the test pattern at this time is NE
It is called G pattern.

When ScanE = 1, "C", "D" from ScanIn0
Scan pattern, and flip-flop circuits 104, 1 each operating with an opposite phase clock
Set to 02. When ScanE = 0, the falling edge of the clock signal CLK causes “C” and “D” to go to the logic circuit 11 in the subsequent stage.
2, the output “P” of the preceding logic circuit 111,
“Q” is set to the outputs NN1 and NN0 of the flip-flop circuits 104 and 102. When ScanE = 1 again, the outputs “P” and “Q” of the logic circuit 111 are scanned out, and the next test patterns “G” and “H” are scanned in. Thus, the NEG pattern is
Used for testing the logic circuit 111.

As described above, the POS pattern and the NEG
The pattern is used when the phase relationship between the clock signal CLK and the signal ScanE for performing the scanning operation is different, and thus cannot be unified into one test pattern.

The present invention has been made in view of such a problem, and an object of the present invention is to use a single test pattern when flip-flop circuits operating on a normal phase clock and a reverse phase clock are mixed. An object of the present invention is to provide a semiconductor integrated circuit capable of performing an inspection and a method of inspecting the semiconductor integrated circuit.

[0015]

SUMMARY OF THE INVENTION In order to achieve the above object, according to the present invention, a test of a logic circuit is performed by using flip-flop circuits connected by a scan chain. In the semiconductor integrated circuit to be performed, there is provided a selection circuit that selects one of a clock signal and an inverted clock signal obtained by inverting the clock signal and supplies the clock signal to the flip-flop circuit, and the selection circuit selects the clock signal. In the case, the logic circuit connected to the previous stage of the flip-flop circuit that operates on the positive phase clock is inspected,
When the inversion clock signal is selected by the selection circuit, a logic circuit connected to a preceding stage of the flip-flop circuit that operates with an inversion clock is inspected.

According to a second aspect of the present invention, in the semiconductor integrated circuit inspection method for inspecting a logic circuit using flip-flop circuits connected by a scan chain, a clock signal is supplied to the flip-flop circuit. Inspecting a logic circuit connected to a preceding stage of the flip-flop circuit operated by the normal phase clock, and supplying an inverted clock signal obtained by inverting the clock signal to the flip-flop circuit, and operating by the inverted phase clock Inspecting the logic circuit connected to the preceding stage of the above.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 4 is a circuit diagram showing a semiconductor integrated circuit according to one embodiment of the present invention. The flip-flop circuits 401 and 403 operating on the positive-phase clock are ScanIn1-Sc
An example is shown in which an out1 is connected to the same scan chain as the flip-flop circuits 402 and 404 operated by the opposite phase clock, respectively, to ScanIn0 to ScanOut0.

The outputs PP0 and PP1 of the flip-flop circuits 401 and 403 are connected to a logic circuit 411, and the output of the logic circuit 411 is connected to the flip-flop circuits 402 and 4
04 is connected to the input. Flip-flop circuit 4
Outputs NN0 and NN1 of the logic circuits 412 and 02
The output of the logic circuit 412 is fed back and connected to the inputs of the flip-flop circuits 401 and 403.

The clock signal CLK is supplied to the selector 42
1 and outputs an internal clock signal ICLK having a positive phase or a negative phase according to the clock selection signal Mode.

The flip-flop circuits 401 to 404
When the signal ScanE for performing the scan operation = 1, a serial data string is input for each ScanCLK from the ScanIn input, and desired data is set in a flip-flop circuit of a scan chain connected like a shift register. this,
It is called shift operation. When ScanE = 0, normal operation is performed by ScanCLK input.

FIG. 5 is a time chart showing a method for inspecting a semiconductor integrated circuit according to one embodiment of the present invention.
First, with the clock selection signal Mode = 0, the internal clock signal ICLK outputs a positive-phase clock. This is a case where the internal clock signal ICLK changes in the order of rising and falling during the period of ScanE = 0. At this time, P shown in FIG.
A test pattern similar to the OS pattern is input.

When ScanE = 1, "A", "B" from ScanIn1
Scan pattern, and flip-flop circuits 403 and 4 each operating with a positive-phase clock
Set to 01. When ScanE = 0, internal clock signal ICLK
With the rise of “A”, “A” and “B” are input to the subsequent logic circuit 411, and the outputs “M” and “N” of the previous logic circuit 412 are output to the flip-flop circuits 403 and 40.
1 are set to the outputs PP1 and PP0. ScanE = 1 again
Then, the outputs “M” and “N” of the logic circuit 412 are scanned out, and the next test patterns “E” and “F” are scanned in. Thus, the inspection of the logic circuit 412 is performed.

Next, as the clock selection signal Mode = 1, the internal clock signal ICLK outputs an opposite-phase clock. Scan
During the period of E = 0, the internal clock signal ICLK falls,
This is a case where it changes in the order of rising. At this time, FIG.
A test pattern similar to the NEG pattern shown in FIG.

When ScanE = 1, "C", "D" from ScanIn0
Scan pattern, and flip-flop circuits 404 and 4 each operating with an opposite-phase clock
Set to 02. When ScanE = 0, internal clock signal ICLK
As a result, “C” and “D” are input to the subsequent logic circuit 412, and the outputs “P” and “Q” of the preceding logic circuit 411 are output to the flip-flop circuits 404 and 40.
2 are set to the outputs NN1 and NN0. ScanE = 1 again
Then, the outputs “P” and “Q” of the logic circuit 411 are scanned out, and the next test patterns “G” and “H” are scanned in. Thus, the inspection of the logic circuit 411 is performed.

As described above, the clock signal CLK and the signal ScanE for performing the scanning operation are controlled by the clock selection signal Mode.
Can be selected, the inspection can be performed with one test pattern when flip-flop circuits operating on the normal phase clock and the reverse phase clock are mixed.

According to the present embodiment, since the inspection can be performed with one test pattern, the inspection man-hour and the inspection time can be reduced in the semiconductor integrated circuit inspection apparatus.

[0028]

As described above, according to the present invention,
A flip-flop that includes a selection circuit that selects one of a clock signal and an inverted clock signal obtained by inverting the clock signal and supplies the clock signal to the flip-flop circuit, and operates with a positive-phase clock when the selection circuit selects the clock signal. Inspecting the logic circuit connected to the preceding stage of the flip-flop circuit, and, when the inverted clock signal is selected by the selection circuit, inspecting the logic circuit connected to the preceding stage of the flip-flop circuit that operates on the inverted clock. Therefore, when the flip-flop circuits that operate with the normal phase clock and the negative phase clock are mixed, the inspection can be performed with one test pattern.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit using a conventional scan chain.

FIG. 2 is a time chart showing a conventional method for testing a flip-flop circuit operated by a normal phase clock of a semiconductor integrated circuit.

FIG. 3 is a time chart showing a conventional method for testing a flip-flop circuit of a semiconductor integrated circuit which operates on an inverted clock.

FIG. 4 is a circuit diagram showing a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 5 is a time chart showing a method for testing a semiconductor integrated circuit according to one embodiment of the present invention.

[Explanation of symbols]

101 to 104, 401 to 404 Flip-flop circuit 111, 112, 411, 412 Logic circuit 421 Selector

Claims (2)

[Claims] In a semiconductor integrated circuit for inspecting a logic circuit using flip-flop circuits connected by a scan chain, a clock signal and an inverted clock signal obtained by inverting the clock signal are selected. A selection circuit for supplying the flip-flop circuit, wherein when the clock signal is selected by the selection circuit,
The logic circuit connected to the preceding stage of the flip-flop circuit operated by the normal phase clock is inspected, and if the inverted clock signal is selected by the selection circuit, the logic circuit is connected to the preceding stage of the flip-flop circuit operated by the opposite phase clock. A semiconductor integrated circuit characterized by inspecting a completed logic circuit. 2. A semiconductor integrated circuit inspection method for inspecting a logic circuit using flip-flop circuits connected by a scan chain, comprising: supplying a clock signal to the flip-flop circuit and operating with a positive-phase clock; Inspecting a logic circuit connected to a preceding stage of the flip-flop circuit, supplying an inverted clock signal obtained by inverting the clock signal to the flip-flop circuit, and connecting a logic circuit connected to a preceding stage of the flip-flop circuit operating with an inverted phase clock. Inspecting the circuit.