JP2002221929A - Flat panel display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, when the number of data wirings for transmitting pixel data to respective source drivers of a flat panel display device is increased, unwanted radiation due to the mutual coupling among signal wirings which are arranged by being accompanied by the complication and the high density of traces is generated. SOLUTION: In a plural of data wirings extending from a driver controller 6B to source drivers 2, data lines of odd numbered pixels and even numbered pixels are arranged side by side in this display device. When pixel data of the odd numbered pixel data coincide with pixel data of the even numbered pixels data in adjacent pixels, the driver controller 6B applies either pixel data of the odd numbered pixels or the even numbered pixels to the source drivers 2. The display device can reduce unwanted radiation from the flat panel of the device by suppressing noise by high-frequency coupling while making the data wirings of one side act as guard rings with respect the data wirings of the other side in such a way.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display (LCD), a plasma display, an EL (Electroluminescence) display,
The present invention relates to a flat panel display device using a flat display panel such as an FED (Field Emission Display).

[0002]

2. Description of the Related Art As a flat display panel used for a display of a computer or the like, a TFT liquid crystal display panel is known. FIG. 7 is a configuration diagram of a TFT liquid crystal display panel which is one of the conventional flat panel display devices. This flat panel display device includes a liquid crystal display panel 1, a source bus board 3A on which a plurality of source drivers 2 are mounted as column drivers, a gate bus board 5 on which a plurality of gate drivers 4 are mounted as row drivers, and a driver controller 6A. It is comprised including.

The source driver 2 is an IC for driving a source electrode line (column electrode line) of the liquid crystal display panel 1. The source bus board 3A is arranged on the long side of the outer periphery of the liquid crystal display panel 1, and a number of data wirings are traced from the driver controller 6A to the plurality of source drivers 2, and the plurality of source drivers 2 are mounted. Substrate. The gate bus substrate 5 is a substrate which is disposed on a short side of the outer periphery of the liquid crystal display panel 1 and on which a plurality of gate drivers 4 are mounted. The gate driver 4 is an IC that scans a gate electrode line, which is a row electrode line of the liquid crystal display panel 1, in units of rows.

The driver controller 6A is mounted on the control board 7 and outputs a data signal (pixel data) to the source driver 2 and a line selection signal to the gate driver 4 when an input signal from a display controller (not shown) is given. IC that performs

[0005]

In such a configuration, pixel data for one display line is sequentially supplied from the driver controller 6A to the plurality of source drivers 2,
Thereafter, the pixel data is simultaneously output from all the source drivers 2 and supplied to the respective liquid crystal cells positioned on the respective source electrode lines of the liquid crystal display panel 1 to display images, characters, and the like.

At this time, each source driver 2 has
The clock signal and n-bit pixel data of each color of RGB are supplied in parallel from the driver controller 6A. n =
6, that is, when the pixel data has a 6-bit width, 18 data lines are required for each of the R, G, and B liquid crystal cells per pixel. In recent years, as the definition of the liquid crystal display panel 1 increases and the number of simultaneously displayed colors increases, the amount of RGB data increases, and the frequency of the clock signal tends to increase.

As means for lowering the frequency of the clock signal, for example, as disclosed in Japanese Patent Application Laid-Open No. H10-207434, there is a method of dividing the frequency of a clock signal or outputting RGB data signals to a plurality of ports. . These methods have resulted in increased complexity of traces due to an increase in the number of data wirings, higher wiring densities, and multi-layer substrates for separation of signal wiring layers, resulting in higher costs for flat panel display devices. I have. For example, FIG. 7 shows a case where pixel data represented by 6 bits is output from the driver controller 6A for each of R, G, and B and is input to the source driver 2.

FIG. 8 is a layout diagram of a part of the data wiring output from the driver controller 6A. As shown in FIG. 8, the data wiring of each pixel of R, G, B
The data lines of the odd-numbered pixels shown in (A) and the data lines of the even-numbered pixels shown in (B) are grouped. Specifically, on the right side of the outer periphery of the driver controller 6A, from the lower end to the upper end, R_even [0] (LSB of red data in even pixels)... R_even
[5] (MSB of red data in even pixels), G_
even [0] ... G_even [5], B_even
n [0]... B_even [5] are wired in this order.

Each source driver 2 has an odd input port corresponding to an odd pixel and an even input port corresponding to an even pixel. Assume that the bit width of the pixel data is n and the pixel data of the odd-numbered pixels is odd (a ₀ , a ₁ ,.
A _n-1 ), and the pixel data of the even-numbered pixel is even (b
₀ , b ₁ ,..., B _n-1 ), odd (a ₀ ,
a ₁ ,... a _n-1 ) are input to the odd input port,
Even (b ₀ , b ₁ ,..., b _n-1 ) is input to the even input port. Assuming that n = 6, the total number of data wirings per source driver is 36 (= 6 bits × R
GB × 2) required. For this reason, the data wirings are traced (arranged) close to each other and parallel to each other due to the limitation condition of the substrate area and the like.

In addition, due to the recent demand for a large screen of the display panel, a trace configuration having a long wiring length in the column direction of the display panel is required especially in the source bus substrate 3A to which a high-speed data signal is transmitted. It became so. For example, 1
In the 5-inch class, the wiring length of the data wiring may be 30 cm or more. Under such conditions, in signal wiring including data wiring and other wiring, unnecessary radiation (EMI: ElectroMagnetic) is caused by complicated coupling caused by capacitance and inductance between wirings.
Interference) could be a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and has been proposed in order to effectively suppress noise coupling due to coupling between signal wirings even when wiring density is high. Without using expensive means such as multi-layering, it is possible to reduce unnecessary radiation with a cheap and simple circuit configuration, increase the amount of RGB data expected in the future, increase the clock frequency, and further increase the screen size. It is another object of the present invention to provide a flat panel display device capable of coping with the above.

[0012]

According to a first aspect of the present invention, there is provided a display panel including a plurality of pixels arranged in a matrix of rows and columns, and a plurality of columns for driving column electrode lines of the display panel. A driver, a row driver that scans the plurality of row electrode lines of the display panel in row units, and pixel data for one display line transferred from the outside into bit data of odd-numbered pixel data and pixel data of even-numbered pixels. A driver controller that alternately divides the pixel data into units and applies the pixel data to the column driver in parallel via data wiring. The driver controller sets the bit width of each pixel data to n. When the number of bits is equal, the value of the i-th bit (i is an arbitrary number from 1 to n) of the pixel data of the odd-numbered pixel matches the value of the i-th bit of the pixel data of the even-numbered pixel Oite, and outputs either one only of the i-th bit value of i-th bit of value or the even pixels of the odd-numbered pixel as the actual bit values.

According to a second aspect of the present invention, in the flat panel display device according to the first aspect, the data wiring supplied from the driver controller to the column driver is:
The pixel data of the odd-numbered pixels is expressed as odd (a ₀ , a ₁ ,.
_n-1 ), and the pixel data of the even-numbered pixel is even (b ₀ ,
b ₂ ,... b _n-1 ), the bit value a _i-1 (i
Is characterized in that the data wiring of ₁ to n) and the data wiring of the bit value bi _-1 are alternately located.

According to a third aspect of the present invention, there is provided a display panel including a plurality of pixels arranged in a matrix of rows and columns;
A plurality of column drivers for driving the column electrode lines of the display panel; a row driver for scanning the plurality of row electrode lines of the display panel in units of rows; The pixel data of the pixel and the pixel data of the even-numbered pixel are alternately divided in bit units, and a driver controller which is provided in parallel to the column driver via a data wiring, and a bit value of an odd-numbered pixel and an even-numbered pixel which are adjacent to the driver controller. If either one is given as a real bit value, the other bit value is replaced with one bit and output.If both the bit values of adjacent odd and even pixels are given, the input bit value is given. And a neighboring pixel data control circuit that outputs the pixel data as it is. When the bit width of the pixel data is n bits, the value of the i-th bit (i is an arbitrary number from 1 to n) of the pixel data of the odd-numbered pixel and the value of the i-th bit of the pixel data of the even-numbered pixel match, In the case of the adjacent match, only one of the value of the i-th bit of the odd-numbered pixel or the value of the i-th bit of the even-numbered pixel is regarded as a real bit value. And providing the adjacent pixel data control circuit with both the value of the i-th bit of the odd-numbered pixel and the value of the i-th bit of the even-numbered pixel to the adjacent pixel data control circuit in the case of the adjacent mismatch. And

The invention of claim 4 of the present application is directed to claim 1 or 3
In the flat panel display device of (1), when the bit width of each pixel data is n bits, the driver controller sets the i-th bit (i is 1 to n) of the pixel data of the odd-numbered pixel.
Bit value comparing means for determining whether or not the value of (i.e., an arbitrary number) and the value of the i-th bit of the pixel data of the even-numbered pixel match.

The invention of claim 5 of the present application is directed to claim 1 or 3
In the flat panel display device of (1), when the bit width of each pixel data is n bits, the driver controller sets the i-th bit (i is 1 to n) of the pixel data of the odd-numbered pixel.
Is equal to the value of the i-th bit of the pixel data of the even-numbered pixel, and only the value of the i-th bit of the odd-numbered pixel or the value of the i-th bit of the even-numbered pixel Is provided to the column driver as an actual bit value, and the other bit value is held at the H level.

The invention of claim 6 of the present application is directed to claim 1 or 3
In the flat panel display device of (1), when the bit width of each pixel data is n bits, the driver controller sets the i-th bit (i is 1 to n) of the pixel data of the odd-numbered pixel.
Is equal to the value of the i-th bit of the pixel data of the even-numbered pixel, and only the value of the i-th bit of the odd-numbered pixel or the value of the i-th bit of the even-numbered pixel Is provided to the column driver as a real bit value, and the other bit value is held at the L level.

The invention of claim 7 of the present application is directed to claim 1 or 3
In the flat panel display device of (1), when the bit width of each pixel data is n bits, the driver controller sets the i-th bit (i is 1 to n) of the pixel data of the odd-numbered pixel.
Is equal to the value of the i-th bit of the pixel data of the even-numbered pixel, and only the value of the i-th bit of the odd-numbered pixel or the value of the i-th bit of the even-numbered pixel Is provided to the column driver as an actual bit value, and bit value conversion means for holding the other bit value to be transmitted this time the same as the other bit value transmitted last time is provided.

The invention of claim 8 of the present application is directed to claim 1 or 3
In the flat panel display device of (1), when the bit width of each pixel data is n bits, the driver controller sets the i-th bit (i is 1 to 1) of the pixel data of the odd-numbered pixel.
n) and the value of the i-th bit of the pixel data of the even-numbered pixel coincide with each other, the change is induced by a change between one of the bit values to be transmitted this time and the previously transmitted bit value. Bit value conversion means for changing the other bit value so that an induced magnetic field is generated in a direction for canceling the applied magnetic field.

[0020]

(Embodiment 1) A flat panel display device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a flat panel display device according to the present embodiment. The same parts as those of the conventional example shown in FIG. The flat panel display includes a liquid crystal display panel 1, a source bus substrate 3B on which a plurality of source drivers 2 and an adjacent pixel data control circuit 8 are mounted, and a plurality of gate drivers 4.
And a control board 7 on which a driver controller 6B is mounted. FIG.
FIG. 4 is a layout diagram of data wiring traced from the driver controller 6B to the adjacent pixel data control circuit 8.

When the bit width of each pixel data is n bits, the driver controller 6B sets the value of the i-th bit (i is an arbitrary number from 0 to n) of the pixel data of the odd-numbered pixel and the pixel data of the even-numbered pixel. Has a bit value comparing means for determining whether or not the value of the i-th bit matches or not, and a bit value converting means described later. When the bit width of each pixel data is set to n bits, the bit value comparing means determines the value of the i-th bit (i is an arbitrary number from 1 to n) of the pixel data of the odd-numbered pixel and the i-bit of the pixel data of the even-numbered pixel. This is a means for determining whether the eye value (hereinafter, simply referred to as pixel data) matches or does not match. The bit value comparing means outputs a coincidence signal (OxE) for notifying whether the pixel data of the odd-numbered pixel and the pixel data of the even-numbered pixel coincide or not. A case where the pixel data matches is called an adjacent match, and a case where the pixel data does not match is called an adjacent mismatch. If the bit value comparison means determines that the adjacent pixels coincide with each other, the driver controller 6B sets only one of the value of the i-th bit of the odd-numbered pixel or the value of the i-th bit of the even-numbered pixel as the actual bit value and sets the adjacent pixel data control circuit 8 When the bit value comparison unit determines that the adjacent pixels do not match, the bit values are output to the adjacent pixel data control circuit 8 as they are.

The data lines from the driver controller 6B toward the adjacent pixel data control circuit 8, the pixel data of the odd pixel _{odd (a 0, a 1,} ··· a n-1) and,
The pixel data of the even-numbered pixels is even (b ₀ , b ₁ ,...).
b _n-1 ), the data wiring for the bit value a _{i-1 and} the data wiring for the bit value b _i-1 are patterned so as to be located alternately.

The adjacent pixel data control circuit 8 is provided immediately before the data input terminal of each source driver 2. When an adjacent coincidence signal is supplied from the driver controller 6B, only one pixel data is input. Assuming that the same pixel data as the one pixel data is transmitted to the other data, the same pixel data is sent to the odd input port and the even input port of the source driver 2. Further, when an adjacent non-coincidence signal is supplied, the two-bit value supplied from the driver controller 6B is supplied to the source driver 2 as it is. Note that the coincidence signal (Ox
E) is at the H level in the case of adjacent coincidence, and is at the L level in the case of adjacent non-coincidence.

Various functions can be considered as the function of the bit value conversion means provided in the driver controller 6B. The function of the adjacent pixel data control circuit 8 differs depending on the function of the driver controller 6B. FIG. 3 is a configuration diagram of the adjacent pixel data control circuit 8 newly provided in the present embodiment. The adjacent pixel data control circuit 8 shown in FIG. 3 is configured such that when one of the bit values of the adjacent odd-numbered pixel and the even-numbered pixel, here the bit value of the odd-numbered pixel is given as the real bit value from the driver controller 6B, The bit value of the pixel is replaced with the bit value of the odd pixel and output, and when both the bit values of the adjacent odd and even pixels are given, the function of outputting the input bit value as it is is realized. is there.

The adjacent pixel data control circuit 8 having such a function includes an AND gate 81, an AND gate 82, an inverter 83, and an OR gate 84. When the pixel data of the odd-numbered pixel and the pixel data of the even-numbered pixel coincide with each other at two specific adjacent source electrode lines,
H level coincidence signal Ox from driver controller 6B
E is output and applied to AND gate 81 and inverter 83. If the two pixel data do not match, the L level match signal OxE is output from the driver controller 6B.
Is applied to an AND gate 81 and an inverter 83.
In addition, regardless of adjacent coincidence or adjacent non-coincidence, pixel data of an odd-numbered pixel is supplied to an AND gate 81, and pixel data of an even-numbered pixel is supplied to an AND gate. OR gate 8
4 outputs the logical sum of the output of the AND gate 81 and the output of the AND gate 82. Then, the pixel data of the odd-numbered pixel is unconditionally given to the odd input port of the source driver 2, and the output of the OR gate 84 is output from the source driver 2 even
n input ports.

FIG. 3A shows pixel data (o) of an odd pixel.
dd Data) and pixel data of an even pixel (even)
Adjacent pixel data control circuit 8 when Data) matches
3 shows the state of data output. FIG. 3B shows a data output state of the adjacent pixel data control circuit 8 when the pixel data of the odd-numbered pixel and the pixel data of the even-numbered pixel do not match. Here, an example has been described in which, when the pixel data of the odd-numbered pixels and the pixel data of the even-numbered pixels match, only the pixel data of the odd-numbered pixels is transmitted to the adjacent pixel data control circuit 8. That is, in FIG. 3A, the coincidence signal (OxE) becomes H level, and the pixel data (even Data) of the even-numbered pixel becomes O.
It is FF. In this case, the same pixel data as the odd-numbered pixel is output from the OR gate 84 and the source driver 2
Is given as pixel data of an even pixel.

By reversing the input of the odd-numbered pixel data and the even-numbered pixel data, if the odd-numbered pixel data and the even-numbered pixel data match, only the even-numbered pixel data is deleted. A configuration for transmission is also possible.

The flat panel display device shown in FIG.
This is an example in which pixel data of any color among R, G, and B of one pixel has a 6-bit width.
In two adjacent pixels (two sets of RGB), a data line for transmitting pixel data of odd pixels from the driver controller 6B to the source driver 2 and a data line for transmitting pixel data of even pixels are traced so as to be adjacent to each other. Have been. As shown in FIG. 2, with respect to the data wiring of each pixel of RGB data, the odd data wiring and ev
en data lines are adjacent to each other. In particular,
From the end, R_odd [0] (LSB of red data at odd pixels), R_even [0] (LSB of red data at even pixels), R_odd [1], R_even
[1],... B_even [4], B_odd
[5] and B_even [5].

FIG. 4 is an explanatory diagram showing a general function of the adjacent pixel data control circuit 8. The data signal (odd) of the odd-numbered pixel and the data signal (e) of the even-numbered pixel according to the present embodiment.
ven) and the output timing of a match signal (OxE) indicating whether or not the odd-numbered pixel data and the even-numbered pixel data match. FIG. 4A shows signals input to the driver controller 6B, and shows general timings of pixel data and a clock signal (CLK). Here, the odd-numbered pixel data (odd) and the even-numbered pixel data (even) are given at the same time at CLK1, and the odd-numbered pixel data (o) at CLK2.
dd) and even-numbered pixel data (even) are given at the same time, and odd-numbered pixel data (odd)
) And even-numbered pixel data (even) are given at the same time.

As described above, the driver controller 6B
Is provided with first bit value conversion means as one of the bit value conversion means. The first bit value conversion means includes:
When the value of the i-th bit of the pixel data of the odd-numbered pixel matches the value of the i-th bit of the pixel data of the even-numbered pixel, either the value of the i-th bit of the odd-numbered pixel or the value of the i-th bit of the even-numbered pixel Only one of the adjacent pixel data control circuits 8
, And the other bit value this time is kept the same as the previous bit value. As the second bit value conversion means, when the value of the i-th bit of the pixel data of the odd-numbered pixel matches the value of the i-th bit of the pixel data of the even-numbered pixel, the value of the i-th bit of the odd-numbered pixel or the even-numbered pixel Can be supplied to the adjacent pixel data control circuit 8 and the other bit value can be held at either the H or L level.

FIG. 4B shows the coincidence signal (Ox) with CLK2.
It is a timing chart which shows operation | movement when E) became H level. The driver controller 6B outputs odd-numbered pixel data (odd) and even-numbered pixel data (even) as shown in the figure. CL indicated by oblique lines
The even-numbered pixel data (even) at K2 is converted into the odd-numbered pixel data (odd) by the bit value comparing means.
And the first bit value conversion means holds the even-numbered pixel data (even) at the same level as the even-numbered pixel data (even). At this time, the adjacent pixel data control circuit 8 outputs pixel data as shown in FIG.

With such an operation, in the flat panel display device of the present embodiment, the data signal (odd) of the odd-numbered pixel and the data signal (even) of the even-numbered pixel in two adjacent sets of pixels coincide with each other. In other words, during the period in which the coincidence signal (OxE) is set to the H level, regardless of the state of the data signal (even) of the even pixel, the odd input pixel and the even input pixel of the source driver are connected to the odd input port and the even input port of the source driver. The data signal (odd) is input. Therefore, during the period when the coincidence signal (OxE) is set to the H level, the data wiring transmitting the data signal of the even-numbered pixel is not treated as a signal line where the data signal changes.

As described above, by setting the data wiring for transmitting the data signal of the even-numbered pixel to a constant potential which is the same as the data signal transmitted previously (for example, CLK1), the data signal of the adjacent odd-numbered pixel is obtained. Can function as guard ring wiring for data wiring to be transmitted. For example, R_odd [1] of an odd-numbered pixel is guard-ringed by adjacent R_even [0] and R_even [1], and R_odd [1] and the closest active data lines R_odd [0] and R_odd [ 2] can be suppressed.

As described above, during the period in which the coincidence signal (OxE) is set to the H level, the data line transmitting the data signal of the even-numbered pixel is used as a guard ring line for the adjacent line, and the odd-numbered pixel is not used. Crosstalk noise due to high-frequency coupling between wires transmitting data signals is suppressed. In addition, the power consumption of each driver can be reduced by reducing the number of pixel data that are simultaneously switched.

Embodiment 2 Next, a flat panel display according to Embodiment 2 of the present invention will be described with reference to the drawings. The configuration diagram of the flat panel display device according to the present embodiment is the same as FIG. 5 and 6 are timing charts showing the operations of the driver controller 6C and the adjacent pixel data control circuit 8 of the flat panel display device according to the present embodiment. The driver controller 6C is provided with third bit value conversion means as one of the bit value conversion means.

When the bit width of each pixel data is n bits, the third bit value conversion means outputs the value of the i-th bit (i is an arbitrary number from 0 to n) of the pixel data of the odd-numbered pixel, When the value of the i-th bit of the pixel data of the pixel matches, the induced magnetic field is directed in a direction to cancel the magnetic field induced by a change between one of the bit values to be transmitted this time and the previously transmitted bit value. Means to change the value of the other bit so that it occurs.

Specifically, in a period in which pixel data of an odd-numbered pixel and pixel data of an even-numbered pixel coincide in two adjacent sets of pixels, the data signal of the odd-numbered pixel transmitted and the data signal of the previously transmitted odd-numbered pixel are transmitted. Since the induced magnetic field is generated with respect to the change of the third pixel value, the third bit value converting means applies a new induced magnetic field to the data line of the odd-numbered pixel in the direction to cancel the induced magnetic field. The data signal of the data wiring of the even-numbered pixel is controlled.

FIG. 5A shows pixel data (odd) of odd-numbered pixels and pixel data (even) of even-numbered pixels which are supplied to the driver controller 6C and are two sets of adjacent pixels. In the pixel data of the odd-numbered pixels, the level of the pixel data of CLK1 and the level of the pixel data of CLK2 greatly change. The same applies to pixel data of even-numbered pixels. However, it is assumed that the levels of both pixel data are the same in CLK2. At this time, as shown in FIG. 5B, the bit value comparison means in the driver controller 6C outputs an H level coincidence signal (OxE), and makes the pixel data of the even-numbered pixels indefinite as shown by the shaded portions. . The uncertainty here refers to a state where the pixel data can be set to an arbitrary level.

It is assumed that pixel data as shown in FIG. 6C is output from the driver controller 6C to each data line. For example, when shifting from CLK1 to CLK2, odd [2] changes from H to L level. At this time, since even [2] is at the same level as odd [2] as shown in FIG. 5A, the driver controller 6C makes this pixel data indefinite. Therefore, the driver controller 6C intentionally changes even [2] from L to H.
The induction magnetic field 10 is generated in the direction as shown in FIG. In odd [2], an induced magnetic field 11 in a direction opposite to the induced magnetic field 10 due to a change in the original pixel data.
Has occurred. This induced magnetic field 11 is reduced by the induced magnetic field 10 of even [2].

As described above, when the pixel data of the odd pixel matches the pixel data of the even pixel, the third bit value conversion means intentionally generates differential data of the transmitted pixel data, By giving the signal to the other adjacent data line, an unnecessary induced magnetic field is canceled between the adjacent data lines. Thereby, the unnecessary magnetic field radiated from the flat panel display device can be reduced.

In a high-definition flat panel display device such as a recent high-resolution TFT liquid crystal display panel, the pixel pitch decreases as the number of pixels increases. For example, 15
The pixel pitch is about 23 for an inch SXGA display
0 μm. However, if the pixel pitch is too small for the resolution of human visual characteristics, pixel information for each pixel tends to be difficult to recognize. For example, about 300 μm is said to be optimal for displaying character information. In the case of displaying such character information, it can be said that there is almost no pixel data that changes for each pixel on the same gate electrode line.

Except for special cases such as those dealing with high-definition graphic data, when displaying screen information centered on characters in a monitor application of a general computer terminal, the spatial frequency is changed by one pixel. The required ratio is only a few percent of one horizontal line, ie one gate electrode line. Therefore, in most cases, adjacent pixels in the pixel data of one horizontal line have pixel data of the same information. As described above, in general use, the flat panel display device of the present invention includes:
Unnecessary radiation is greatly reduced, and with the advance of high definition,
The effect is greater.

In each of the above embodiments, an example in which 6-bit pixel data is input to the source driver has been described. , Unnecessary radiation can be reduced.

The present invention can be applied not only to TFT liquid crystal panels but also to other liquid crystal panels such as STN, and flat display panels other than liquid crystal such as plasma displays, EL displays, and FEDs. Further, various modifications are possible, such as providing the adjacent pixel data control circuit 8 of FIG. 1 inside the source driver 2.

[0045]

As described above, according to the first to eighth aspects of the present invention, when the pixel data of the odd-numbered pixel and the pixel data of the even-numbered pixel match, one of the adjacent data lines is replaced with the other data line. By acting as a guard ring on the data lines, high-frequency coupling between the data lines transmitting data signals can be suppressed. For this reason, a flat panel display device having a high-density pixel with reduced unnecessary radiation can be obtained with an inexpensive and simple circuit configuration without using expensive means such as a multilayer substrate.

According to the seventh aspect of the present invention, the number of simultaneously switched pixel data can be reduced, and a new effect of reducing power consumption can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a flat panel display device according to Embodiment 1 of the present invention.

FIG. 2 is a layout diagram of data wiring traced from a driver controller in the flat panel display device according to the present embodiment.

FIG. 3 is a schematic configuration diagram of an adjacent pixel data control circuit used in the present embodiment;

FIG. 4 is an output timing diagram of a data signal (odd) of an odd-numbered pixel, a data signal (even) of an even-numbered pixel, and a signal (OxE) indicating that both data signals match, in the flat panel display device of the first embodiment.

FIG. 5 is a diagram illustrating an output of a data signal (odd) of an odd-numbered pixel and a data signal (even) of an even-numbered pixel, and a signal (OxE) indicating that both data signals match, in the flat panel display device according to the second embodiment of the present invention. Timing diagram (1)

FIG. 6 is a diagram illustrating an output of a data signal (odd) of an odd-numbered pixel and a data signal (even) of an even-numbered pixel and a signal (OxE) indicating that both data signals match, in the flat panel display device according to the second embodiment of the present invention. Timing diagram (part 2)

FIG. 7 is a configuration diagram of a conventional flat panel display device.

FIG. 8 is a layout diagram of data wiring traced from a driver controller in a conventional flat panel display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal display panel 2 Source driver 3A, 3B Source bus board 4 Gate driver 5 Gate bus board 6A, 6B, 6C Driver controller 7 Control board 8 Adjacent pixel data control circuit 81, 82 AND gate 83 Inverter 84 OR gate

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/36 G09G 3/36 (72) Inventor Yukihiro Fukumoto 1006 Kazuma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. In-company (72) Inventor Osamu Shibata 1006 Kadoma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. DD12 JJ02 JJ03 JJ04

Claims (8)

[Claims] A display panel including a plurality of pixels arranged in a matrix of rows and columns; a plurality of column drivers for driving column electrode lines of the display panel; and a plurality of row electrode lines of the display panel. A row driver that scans in units of rows, and pixel data for one display line transferred from the outside are alternately divided into pixel data of odd-numbered pixels and pixel data of even-numbered pixels in bit units. A driver controller that supplies the pixel data to the driver in parallel, wherein the driver controller is configured such that when a bit width of each pixel data is n bits, i bits of pixel data of an odd pixel are Eyes (i is any number from 1 to n)
And the value of the i-th bit of the pixel data of the even-numbered pixel coincides with the value of the i-th bit of the odd-numbered pixel or the value of the i-th bit of the even-numbered pixel as a real bit value. A flat panel display device for outputting. 2. The method according to claim 2, wherein the driver controller is configured to control the row driver.
The data wiring supplied to the driver is configured to transfer pixel data of odd-numbered pixels to odd (a₀ , A₁ , ... a
_n-1 ), And the pixel data of the even-numbered pixel is even (b).₀ ,
b_Two , ... b_n-1 ), The bit value a _i-1 (I
Are the data wiring of 1 to n) and the bit value b_i-1 Data wiring
Wherein the and are alternately located.
2. The flat panel display device according to 1. A display panel including a plurality of pixels arranged in a matrix of rows and columns; a plurality of column drivers for driving column electrode lines of the display panel; and a plurality of row electrode lines of the display panel. A row driver that scans in units of rows, and pixel data of one display line transferred from the outside, wherein odd-numbered pixel data and even-numbered pixel data are alternately divided in bit units, and the column data is passed through data lines. A driver controller provided to the driver in parallel, and when one of bit values of adjacent odd-numbered pixels and even-numbered pixels is given as a real bit value from the driver controller, the other bit value is replaced with one bit and output. When both the bit values of the adjacent odd-numbered pixel and the even-numbered pixel are given, an adjacent pixel data control circuit that outputs the input bit value as it is A flat panel display device having a, the driver controller, the bit width of each pixel data is n bits, the value of i-th bit of the pixel data of the odd pixel (i is any number of 1 to n),
When the value of the i-th bit of the pixel data of the even-numbered pixel coincides with the value of the i-th bit of the odd-numbered pixel or the even number of the odd-numbered pixel, Only one of the values of the ith bit of the pixel is given to the adjacent pixel data control circuit as a real bit value, and in the case of the adjacent non-coincidence, the value of the ith bit of the odd pixel and the ith bit of the even pixel A flat panel display device wherein both values are given to the adjacent pixel data control circuit. 4. When the bit width of each pixel data is n bits, the driver controller sets an i-th bit (i is an arbitrary number from 1 to n) of pixel data of an odd-numbered pixel.
4. The flat panel display device according to claim 1, further comprising a bit value comparing unit that determines whether the value of the pixel data of the even pixel and the value of the i-th bit of the pixel data of the even-numbered pixel match. 5. When the bit width of each pixel data is n bits, the driver controller sets the i-th bit (i is an arbitrary number from 1 to n) of the pixel data of the odd-numbered pixel.
And the value of the i-th bit of the pixel data of the even-numbered pixel coincides with the value of the i-th bit of the odd-numbered pixel or the value of the i-th bit of the even-numbered pixel as a real bit value. 4. The flat panel display device according to claim 1, further comprising a bit value conversion unit that supplies the bit value to the column driver and holds the other bit value at an H level. 6. The i-th bit (i is an arbitrary number from 1 to n) of pixel data of an odd-numbered pixel when the bit width of each pixel data is n bits.
And the value of the i-th bit of the pixel data of the even-numbered pixel coincides with the value of the i-th bit of the odd-numbered pixel or the value of the i-th bit of the even-numbered pixel as a real bit value. 4. The flat panel display device according to claim 1, further comprising a bit value conversion unit that supplies the bit value to the column driver and holds the other bit value at an L level. 7. When the bit width of each pixel data is n bits, the driver controller sets the i-th bit (i is an arbitrary number from 1 to n) of the pixel data of the odd-numbered pixel.
And the value of the i-th bit of the pixel data of the even-numbered pixel coincides with the value of the i-th bit of the odd-numbered pixel or the value of the i-th bit of the even-numbered pixel as a real bit value. 4. A bit value conversion means according to claim 1, further comprising a bit value conversion means provided to the column driver and holding the other bit value to be transmitted this time the same as the other bit value transmitted last time. Flat panel display. 8. When the bit width of each pixel data is n bits, the driver controller sets the i-th bit (i is an arbitrary number from 1 to n) of the pixel data of the odd-numbered pixel.
Direction and the value of the i-th bit of the pixel data of the even-numbered pixel coincide with each other, the direction of canceling the magnetic field induced by the change between one of the bit values to be transmitted this time and the previously transmitted bit value 4. The flat panel display device according to claim 1, further comprising a bit value conversion means for changing the other bit value so that an induced magnetic field is generated.