JP2002218307A - Camera system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a camera system to make various corrections on digitalization processing by effectively utilizing a rapid large-capacity memory necessary for a snapshot, adopting a part of the memory as a memory for outputting noise, block-subtracting the noise from a signal output, and noise correcting the signal. SOLUTION: The camera system comprises a sensor, an amplifier, an A/D converter, and the memory. Outputs from the sensor are sequentially read in the order of the noise and the signal output, digitally processed through A/D conversion, and then stored at a frame unit in the memory. Thereafter, the noise correcting process, such as the subtracting process or the like, is executed by a CPU or the like for controlling a bus, and stored in the memory. The snapshot is a snapshot or a dynamic image and the large-capacity memory is used as a buffer, in the case of recording on a lower-speed medium.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a camera system capable of taking a quick photo.

[0002]

2. Description of the Related Art Conventionally, digital camera systems and the like include:
CCD image sensors that can be highly integrated in principle and have good noise characteristics have been used.

The CCD is, for example, an interline type CC.
In D, a photodiode for photoelectrically converting image light;
Pixels are constituted only by transfer paths for transferring photoelectric charges generated by the photodiodes. Therefore, high density and high integration are possible in principle, and a large number of pixels (up to 2 million pixels) required for the digital camera are required. ) Has been realized.

[0004] In addition, no noise is generated in the photocharges transferred in the transfer path in principle, and the CCD is basically called a quantum device in principle.

[0005] Noise generated in the CCD is mainly generated by a sense amplifier that senses the transferred photocharge.

The sense amplifier senses the transferred photocharge, and then performs a reset operation to transfer the next photocharge and perform sensing again. The main component of the noise is generated when the sense amplifier is reset. The reset noise is random noise and cannot be reduced although it may increase in subsequent processing. However, it is substantially possible to detect the photocharge with a reduced noise component. As a typical example of such a technology, for example, a CDS disclosed in Japanese Patent Application Laid-Open No. 10-164442.
There is a technique called (correlation double sampling). The above method is a method of first reading the output of the amplifier after resetting, then reading the output of the photoelectric charge by CCD transfer, and obtaining the difference between the two to obtain the net output of the photoelectric charge.

FIG. 6 shows a conventional camera system using the CDS. The image signal output from the image sensor 101 is subjected to noise removal by the CDS circuit 102, and A
The signal is input to an A / D converter 104 via a GC (auto gain control) circuit 103. A / D converter 10
4 is converted to a digital signal by the DSP 10
The data is stored in the memory 107 by the action of 6 or the like. or,
In addition to the typical camera system shown in FIG. 6, there is a conventional example as shown in FIG. For example, in a CMOS type sensor manufactured by HP, noise and signal output from the sensor 11 are separately passed through a PGA (programmable gain amplifier) circuit 113 and an A / D converter 114.
The difference is taken in buffer 116 in the form of a digital signal. The above method is also similar in principle to the CDS method described above.

The above-mentioned method using a plurality of A / D converters is also effective in improving the overall processing speed of a digital camera system having a large number of pixels. 9-224181.

In recent years, digital cameras have been widely used to increase the number of pixels in order to claim high image quality. With the increase in the number of pixels, it takes a long time to record data on a recording medium.
(Approximately several seconds), and in a multi-pixel digital camera, there is a situation where it is difficult to take a quick photograph of less than one second.

In order to enable the rapid shooting, that is, continuous shooting as typified by a past motor drive or moving image shooting, a high-speed memory such as a DRAM having a shorter access time than the recording medium is used. More than one image signal (field or frame unit) is provided. Such an example includes, for example,
328279.

[0011]

The existence of the high-speed memory increases the price of the camera system at the present time, and is not preferable. However, considering the Moore's rule of three years and four times, for example, it may become a burden in the future. It will not be. Rather, it is useful to develop a system that positively acknowledges the existence of the high-speed memory.

It is an object of the present invention to optimize the noise correction of the system in a diffractive optical element on the premise that a large amount of high-speed memory is included.

[0013]

According to the present invention, a signal output from the sensor to be corrected and a noise output used for the correction are fetched into the high-speed memory in the form of a digital signal. Thereafter, a net image signal is obtained from the signal output and the noise output by a known image processing technique, for example, a difference process by a DSP or a CPU.

The obtained image signal is stored again in the high-speed memory. The image signal in the memory is recorded on the recording medium at a relatively low speed during a time period that does not affect the rapid shooting operation.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a block diagram showing a digital camera (hereinafter referred to as digital camera) system according to a first embodiment of the present invention.

Reference numeral 11 denotes a CCD type color image sensor having 640 × 480 pixels. The sensor 11 can generate a maximum of 30 frame images per second.

Numeral 13 denotes an amplifier for adjusting the level of the CCD output to the input range of the A / D converter 14 at the subsequent stage. No particular gain adjustment is performed here. Therefore, the amplitude of the noise output output from the sensor 11 is
The amplification factor is not changed by the amplitude of the signal output. The A / D converter 14 converts a noise output and a signal output from the amplifier 13 into a digital signal.
Hz, 10 bits. Reference numeral 15 denotes a bus having a bit width of 16, and 10 bits of the output of the A / D converter are connected to the bus 15.

Reference numeral 16 denotes a 16-bit CPU for controlling the bus 15, which has two registers for storing 16-bit data, and two segment registers and offset registers for specifying two addresses. 17 is 32 megabit D
RAM.

The bus 15 is also connected with a smart medium 18 as a recording medium and an LCD 19. This system when the shutter 21 is not pressed is:
The control circuit 20 generates a control signal 15 times per second, and outputs 15 frame images from the sensor 11 to the amplifier 13 per second. The frame image is composed of a noise output and a signal output repeated for each pixel, and the total number is 640 × 480 = 307,200.

Each of the outputs is converted into a digital signal by the A / D converter 14. In this system, 10-bit data output to the 16-bit bus is managed as one word. Therefore, each of the 307 and 200 outputs has the same number of words.

The two segment registers indicating the addresses in the CPU 16 are 00000H and 05000H, respectively.
Indicates the address. The two offset registers are both at address 0. Each output output from the A / D converter 14 is stored in the two data registers of the CPU 16 for each pixel by an interrupt process by a clock output from the control circuit 20.

The CPU 16 subtracts the noise output from the signal output, and stores the result of the noise correction in the 0500 of the memory 17 by the function of the segment register indicating the address 05000H and the offset register indicating the address 0.
Store to address 0H.

Thereafter, the value of the offset register is incremented. Perform the process for the next pixel in the same way,
As a result, the area from address 05000H to address 09B00H of the memory 17 is occupied by noise-corrected frame image data.

After the noise-corrected frame image is formed in the memory 17, the CPU 16 stores the frame image in the L using the time between frames.
High-speed block transfer to CD19. By looking at the LCD 19, the user of the digital camera can view the output image of the sensor 11 at 15 frames per second.

Next, when the shutter 21 is pressed,
The digital camera system enters a continuous shooting mode. The instruction issued by the control circuit 20 is the same as that described above in the processing between the sensor 11 and the A / D converter 14, but the instruction to the CPU 16 differs as follows.

The CPU 16 directly writes the frame image after the shutter 21 is pressed into the memory 17 without performing the subtraction processing of the noise output and the signal output.
This is because the subtraction processing which is a burden on the CPU 16 is canceled to cope with a wide range of photographing conditions, apertures, and shutter speeds.

The noise output and the signal output of the first frame image after the shutter 21 is pressed are output by the CPU 16.
0000H each by the instruction of the segment register
The address is stored from address 05000H (FIG. 2). The next second frame image increases the value of the segment register by the address 8000H, and addresses 0A000H, 1
It is stored from the address 4000H. The same applies hereinafter.

Therefore, a total of three frames of image data can be stored in the 32-megabit, 2-megaword DRAM memory 17.

After the number of frame images that can be continuously shot (three) is stored in the memory 17, the CPU 1
6 no longer performs any scanning. As the shutter 21 is released and opened, the noise block and the signal block for each frame stored in the memory 17 are subjected to high-speed subtraction using the CPU 16 on a block-by-block basis in an early frame order. The obtained noise correction result is written in the signal block for each frame. Thereafter, the noise-corrected image frame data is transferred at high speed to the medium 18 to complete a series of processing. Thereafter, the shutter 21 returns to the state where the shutter 21 is not pressed.

According to this embodiment, the optimum noise correction can be realized with a simple and inexpensive system configuration.
In addition, since various processing uses high-speed block processing (calculation and transfer) realized by using an inexpensive memory configuration, each processing can be realized at a very high speed.

The image sensor used in this embodiment is C
It is not limited to the CD type, but may be, for example, a CMOS type. Also, the width of the bus may be any suitable for the system. Further, the CPU used for the calculation may be another DSP or hardware logic. Although a general-purpose DRAM memory is used as the memory 17, a memory such as a high-speed SRAM may be used. 1 word = 10 bits A / D
By using a memory adapted to the output, both bit saving and high-speed accessibility can be achieved.

In this embodiment, the frame rate is 15 frames per second even after the shutter 21 is pressed. However, these can be easily changed according to the photographing conditions.
The output to the LCD 19 can be variously devised other than the method of this embodiment. When the output of the sensor 11 is not a frame unit but a field unit, the unit of the block in the memory 17 may be a field.

FIG. 3 is a block diagram showing a digital camera according to a second embodiment of the present invention. 31 is the number of pixels 640 × 48
0 CMOS type color image sensor. The sensor has a built-in amplification-adjustable amplifier.

Reference numeral 34 denotes a 20 MHz, 8-bit A / D converter, and reference numeral 35 denotes an 8-bit width bus. An 8-bit CPU 36 controls the bus 35. The 8-bit CPU 36 has two registers for storing 8-bit data and four address registers each having an unusual segment register and offset register. It also has a direct block transfer instruction between memories. 37
Is a 32 megabit DRAM.

Reference numeral 42 denotes a compression circuit which realizes an MPEG4 compression format by using a DSP and a software program. Numeral 38 is a large-capacity smart media medium having a capacity of 32 megabytes, which enables long-time recording.

The present embodiment is a system mainly for moving images, and a still image can be photographed by pressing the shutter 41.

In the present system when the shutter 41 is not pressed, the control circuit 40 generates a control signal 15 times per second and the frame image is output from the sensor 31 at 15 times per second.
It is output to the A / D converter 34. In this system, 8-bit data output to the 8-bit bus is managed as one word. Accordingly, the 307 and 200 noise and signal outputs, which are the frame outputs from the sensor 31, have the same number of words.

Each output output from the A / D converter 34 is stored in the two data registers of the CPU 36 for each pixel by an interrupt process in accordance with a clock output from the control circuit 40.

The CPU 16 transfers the noise and signal data to a noise block and a signal block starting from 00000H and 05000H, respectively. Thereafter, the value of the offset register is incremented to prepare for the next data input.

When one frame of output data is stored in the memory 37, the CPU 36 sets the values of the two segment registers to 0A000H and 0F000H and prepares the two frame registers for the input of the next frame data. Change the value of the offset register to OH. Next, the data of the next frame is read. At the same time, the memory 37
The CPU 36 performs subtraction in the foreground between the signal block of the previous frame stored therein and the noise block, and stores the result of the noise correction in the noise block.

The correction data stored in the noise block is stored in the LCD by the CPU 36 in the next frame period.
The block is directly transferred to 39. Thus, the moving image captured by the sensor 31 is continuously displayed on the LCD 39. Next, the correction data is MPEG4 compressed by the compression circuit 42, and the result is written in the signal block of the corresponding frame in the memory 37.

Thereafter, the data is directly transferred to the medium 38 by the CPU 36. Since the amount of data written to the medium 38 by the MPEG4 is reduced to about 1/10, it is possible to sufficiently write data even on a low-speed medium 38 in a frame period (1/15 second).

The addresses indicated by the two segment registers in the CPU 36 are (00000H, 0
(5000H), (0A000H, 0F000H) (14
000H, 19000H) are sequentially repeated.

Next, when the shutter 41 is pressed, the control circuit 40 controls the CPU 36 to write a frame image immediately after the shutter 41 is pressed into each noise signal block, and then perform noise correction in the next frame period. The obtained result is written to both the noise block of the lower block and the noise block of the upper block 32000H.

In the next frame period, the data of the lower block is output to the LCD 39 and is subjected to MPEG4 compression. However, the data of the upper block is not subjected to the MPEG4 compression and is stored in a predetermined place in the medium 38 as it is. It is written by the direct block transfer command of the CPU 36. At this time, the writing data amount of the still image is about ten times larger than that of the moving image, and thus does not fit in the frame period, and the writing time spans several frames.

In the present embodiment, the reason why the data storage location is divided and the direct transfer command which does not bother the CPU 36 for the data transfer is used for the above reasons. According to this embodiment, a camera system capable of easily recording moving images and still images can be easily constructed by using the high-speed memory.

The noise correction used in the present invention is not limited to subtraction. For example, when an amplifier with variable gain in the sensor 1 is operated, noise correction of the output signal cannot always be achieved by subtraction. At this time, if a program operation is previously defined in the CPU 36 using (gain, noise output, signal output) as parameters, an optimum noise correction result can be obtained in any case. The transfer timing to the LCD is not limited to the timing described above, and may be any timing after the noise correction is completed.

Also, the circuit system for performing the above compression has no DS.
It does not need to be P, and may be a known method such as a CPU or hardware logic. Further, since the writing period to the medium requires time, it is preferable that the writing is performed during a frame in which an interrupt process from the A / D converter does not occur.

FIG. 5 is a block diagram of a digital camera system according to a third embodiment of the present invention. 51 is 160 × 1 pixels
Reference numeral 20 denotes a CMOS color image sensor, and reference numeral 62 denotes a one-chip A / D converter 54 and a memory 57 chip. The A / D converter 54 is a 10 MHz 8-bit memory, and the memory 57 is an 8-Mbit DRAM.
It is. Both are connected by a high-speed dedicated local bus in the chip.

The noise and signal output from the sensor 51 are similarly converted to a digital output by the A / D converter 51.

The converted noises and signal outputs are written to the noise blocks and signal blocks in the memory 57 in frame units. In the 8-megabit DRAM, there are three blocks, each having a total of six blocks.

The memory 57 is connected to a low-speed bus 55 existing on an external printed circuit board. The bus 5
The CPU 56 that controls the CPU 5 generates a noise-corrected image output by calculation from the noise and signal output stored in the memory 57 in block units, and stores the image output in the memory 57.

According to the present embodiment, since the output from the A / D converter 54 is performed by a dedicated high-speed local bus different from the bus 55, the occupation ratio of the external bus 55 becomes zero, and the use of the bus 55 Efficiency is improved. As a result, the degree of freedom in compression processing, recording processing, display processing, and the like connected to the bus 55 is improved, and system performance is also improved.

A CP for controlling the bus 55
Since no interrupt processing occurs in U56, the processing capability of the CPU 56 is also improved. The local bus used in the present invention does not need to be the fastest one in the chip;
5 may be in a high-speed hybrid IC package that does not interfere with the bus, or another bus on a printed circuit board.

[0055]

As described above, according to the present invention,
Noise can be corrected using a large-capacity high-speed memory required for quick shooting, and a desired high-performance system can be realized with a simple configuration.

Further, a CDS chip or the like conventionally used in a camera system is unnecessary, and a high-speed memory required for quick shooting and noise correction is monolithically integrated with another chip, for example, an A / D converter, so that the cost can be reduced. The system can be realized.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention.

FIG. 2 shows an embodiment of the present invention.

FIG. 3 shows an embodiment of the present invention.

FIG. 4 shows an embodiment of the present invention.

FIG. 5 shows an embodiment of the present invention.

FIG. 6: Conventional example

FIG. 7: Conventional example

[Explanation of symbols]

 11, 31, 51, 101, 111 Sensor 102 CDS circuit 13, 103, 113 Amplifier 14, 34, 54, 104, 114 A / D converter 15, 35, 55, 105, 115 Bus 16, 36, 56, CPU 17, 37, 57, 107 Memory 18, 38 Medium 19, 39 LCD 20, 40, 60 Control 21, 41, 61 Shutter 42 Compression circuit 62 Chip 106 DSP 116 Buffer

Claims (16)

[Claims] 1. A camera system having a high-speed memory for realizing a snapshot, wherein at least one memory is stored in the memory.
A noise block for inputting noise on a plane and a signal block for inputting a signal on at least one plane, wherein the memory has an A /
The A / D converter is connected to an image sensor, and an analog noise output output from the sensor is converted to a digital noise output by passing through the A / D converter. The signal output stored in the noise block and output at a subsequent timing is also stored in the signal block, and noise correction is performed using both of them, and the resulting image output is stored in any of the memories. Camera system characterized by storing in a place. 2. The camera system according to claim 1, wherein the memory is a DRAM or an SRAM. 3. The camera system according to claim 1, wherein the camera system can shoot a still image, a continuous shot of a still image, or a moving image. 4. The camera system according to claim 1, wherein the noise mainly comprises reset noise of a sense amplifier that senses a photoelectric charge. 5. The camera system according to claim 1, wherein the size of the block is in units of fields or frames of the sensor. 6. The camera system according to claim 1, wherein the number of the signal input blocks is equal to that of the number that can be continuously shot by the camera system. 7. The camera system according to claim 1, wherein a location where the image output is stored is the noise block. 8. The camera system according to claim 1, wherein a location where the image output is stored is the signal block. 9. The camera system according to claim 1, wherein a bus connecting the A / D converter and the memory is a local high-speed bus. 10. The camera system according to claim 1, wherein the noise correction is performed during a next frame period. 11. The camera system according to claim 1, wherein the camera system has a compression circuit for compressing the image.
2. The camera system according to 1. 12. The camera system according to claim 11, wherein the image compression is performed in a next next frame period stored in the memory. 13. The camera system according to claim 1, wherein the camera system has a low-speed medium for recording the image. 14. The camera system according to claim 13, wherein recording on a medium is performed between frames. 15. The camera system according to claim 1, wherein the camera system has a bus, and at least the A / D converter and the memory are connected to the bus. 16. The data processing apparatus according to claim 16, wherein the bus has a CPU or a DSP for controlling the bus, and data output from the A / D converter is performed by interrupt processing of the CPU or the DSP. 16. The camera system according to item 15.