JP2002217947A - Packet-processing device and packet-processing method using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a packet-processing device, which conduct high-speed packet switching processing and can implement sharing of information inputted from different input lines among packets, without using a shared memory. SOLUTION: A virtual packet-processing unit 14, which does not have input/ output lines to external equipment, is provided in a packet processing device 1. The packet processing device 1 is configured, so that stored program packets arrived at packet processing units 11 and 12 from external input lines 101 and 102 can reach the virtual packet processing unit 14 via a packet switch 13. Packets and stored program packets can share information among each other by processors placed inside the packet processing units 11 and 12 and the virtual packet processing unit 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet processing apparatus and a packet processing method used for the same, and more particularly to a method of configuring a packet processing apparatus for processing a packet in which a packet processing method is defined in a packet communication network. .

[0002]

2. Description of the Related Art In an IP (Internet Protocol) protocol, which is a typical example of a conventional packet communication system, a packet processing device does not need to maintain the state of each upper application to which each packet belongs with respect to packet processing. There is no need to achieve sharing.

[0003] D. Scott Alexander, W
illiam A. Arbaugh, Michael
W. Hicks, Pankaj Kakkar, Ang
elos D.E. Keromytis, Jonathan
T. Moore, Carl A .; Gunter, Sco
ttM. Nettles, and Jonathan
M. Smith, "The SwitchWare
Active Network Architect
re ”(IEEE Network Special)
Issue on Active and Contr
ollable Networks, vol. 12 n
o. 3, pp. In the technique described in (29-36), one packet processing unit is provided in the packet processing apparatus with a built-in program, and packets from all input lines are processed by one packet processing unit.

In order to speed up packet processing, it is necessary to mount a plurality of packet processing units in a packet processing apparatus and distribute the processing. In a packet processing device with a built-in program having a plurality of packet processing units, the packet processing units are distributed and arranged for each input line or output line.

[0005] In a packet processing device having a packet processing unit at the subsequent stage of the packet switch, the upper application to which the packet belongs is identified at the previous stage of the switch, and which packet processing unit is processed is determined. Information belonging to the same host application is shared between the packets by being processed by the same packet processing unit.

In the technique described in Hiroki Tagato, Yohei Hasegawa, Hiroshi Hino, "Implementation of Stream Code Engine for Active Network Using FPGA" (IEICE General Conference, 2000), a packet processing unit is provided for each input line. This enables information sharing between packets input from the same input line. FIG. 4 shows the configuration of this packet processing device.

In FIG. 4, a packet processing device 3 includes input lines 301 and 302 and packet processing units 31 and 32.
, A packet switch 33 and a packet output processing unit 3
4 and 35, output lines 307 and 308, and internal connection lines 303 to 306.

The inputs of the packet processing units 31 and 32 are connected to input lines 301 and 302, respectively.
The outputs of the first and the second 32 are connected to the inputs of the packet switch 33 via the internal connection lines 303 and 304, respectively.

The input of the packet switch 33 is connected to the packet processing units 31 and 32 via the internal connection lines 303 and 304, and the output of the packet switch 33 is connected to the input of the packet output processing units 34 and 35, respectively. 3
06.

The input of each of the packet output processing units 34 and 35 is connected to the output of the packet switch 33 via internal connection lines 305 and 306, respectively, and the output of each of the packet output processing units 34 and 35 is output to output lines 307 and 308. Connected to

In the packet processing units 31 and 32, programs in the packets stored in the packets input from the input lines 301 and 302 are executed. By mounting a memory (not shown) in the packet processing units 31 and 32, information sharing between packets passing through the same packet processing unit is realized. The packet output according to the processing result of the program in the packet is the internal connection line 3.
The data is output to the packet switch 33 via the first and second packets 03 and 304.

The packet switch 33 is provided with a packet switch element (not shown).
32, via the internal connection lines 303 and 304, respectively, according to the processing result of the program in the packet in the packet processing unit 31 or the packet processing unit 32, the packet is sent to one of the output lines 307 and 308 for the destination. After performing the exchange process, the internal connection lines 305,
The packet is sent to the packet output processing units 34 and 35 via 306.

The packet output processing units 34 and 35 convert the packets input from the packet switch 33 via the internal connection lines 305 and 306 to output lines 307 and 308, respectively.
Send to With the above configuration, the packet processing device 3
Realizes information sharing between packets input from the same input lines 301 and 302.

Decasper, D .; , Parulka
r, G .; Choi, S .; , DeHart, J .; , Wo
If, T .; Plattner, B .; , "A Scal
able, High Performance Ac
five NetworkNode ”(IEEE Ne
work, January / February 199
In the technique described in 9), by providing a packet processing unit at a stage after the input line and a stage before the output line, information is shared between a packet input from the same input line and a packet output from the same output line. .

[0015] Hiroki Tagato, Yohei Hasegawa, Takashi Egawa, Hiroshi Hino, "Prototype Active Network Hardware for Open Network Control" (IEICE Technical Report, SSSE99-9)
1, TM99-34, 1999), by providing a packet processing unit for each input line and a memory shared by all the packet processing units, information between packets input from different input lines is provided. Sharing is possible.

As described above, in the packet processing device having the packet processing unit in the preceding stage of the packet switch, by using the memory shared by all the packet processing units,
Information is shared by each packet processing unit.

[0017]

In the above-mentioned conventional packet communication system, in a packet processing apparatus having many input lines, high-speed packet processing is realized while sharing information between packets, especially input from different input lines. Various problems arise when realizing information sharing between the given packets.

First, it is difficult to speed up packet processing in a packet processing device having only one packet processing unit. By processing packets input from all input lines in one packet processing unit, information sharing among packets input from all input lines is realized, but the processing capability of the packet processing unit is improved. Is difficult. Also, in a packet processing device having a plurality of packet processing units, it is difficult to share information between packets processed by different packet processing units.

In a packet processing apparatus in which a packet processing unit is arranged only for each input line, if information cannot be exchanged between the respective packet processing units, information sharing between packets input from different input lines is not possible. It is possible. For example, when considering information sharing between packets used in a server-client type upper-level application, as long as each route is appropriately set, packets going from the server to the client and packets going from the client to the server are different. They do not pass through the same input line of one packet processing device.

In a packet processing apparatus having a packet processing unit at a stage after the packet switch, which packet processing unit is input at the stage before the packet switch is determined.
When a plurality of packet processing units are used in a multicast application or the like, information between packets cannot be shared.

The program stored in the packet is an independent process for each packet, and there is no similarity in the process between the preceding and succeeding packets. Therefore, it is not possible to expect a speed-up effect by a memory cache configuration or the like. Therefore, even when a dedicated high-speed memory is mounted in each packet processing unit, there is a high possibility that memory access becomes a bottleneck in packet processing with a built-in program.

In the method of preparing a memory shared by a plurality of packet processing units, access from the plurality of packet processing units concentrates on the shared memory, so that the access speed to the shared memory is reduced, and a bottleneck in packet processing. Become. In particular, when the memory is shared by a large number of packet processing units such as several tens to several hundreds, the performance may be seriously degraded.

Therefore, an object of the present invention is to solve the above-mentioned problems, perform high-speed packet switching processing, and realize information sharing between packets input from different input lines without using a shared memory. And a packet processing method used for the same.

[0024]

According to the present invention, there is provided a packet processing apparatus comprising: a plurality of input lines and an output line; a packet processing unit arranged for each of the input lines; and the plurality of outputs of the packet processing unit. A packet switch for performing a switching process to a line, and a packet output processing unit for outputting an output of the packet switch to the plurality of output lines, wherein a packet in which a processing method of the packet is described is described in the packet. A packet processing device of a built-in program type that performs processing based on a virtual packet processing unit that receives an output of the packet switch as an input instead of an external input line. It is configured to be able to reach the packet processing unit.

A packet processing method according to the present invention includes a plurality of input lines and an output line, a packet processing unit arranged for each of the input lines, and a process of exchanging an output of the packet processing unit for the plurality of output lines. And a packet output processing unit that outputs an output of the packet switch to the plurality of output lines, and includes a program that processes a packet in which a processing method of the packet is described in the packet based on the description. A packet processing method of a packet processing device of the system, wherein a packet with a program input from the outside can reach a virtual packet processing unit which receives an output of the packet switch as an input instead of an input line from the outside.

That is, the first packet processing device of the present invention is a packet processing device having a packet processing unit distributed and arranged for each external input line. It is characterized in that the input packet with a built-in program can reach the virtual packet processing unit in the same manner as the packet reaches the packet switch of the packet processing device.

According to a second packet processing device of the present invention, in a packet processing device having packet processing units distributed for each external input line, a plurality of routing tables are prepared for each packet processing unit, Can select a routing table to determine a route.

According to a third packet processing device of the present invention, in a packet processing device having packet processing units distributed for each external input line, a plurality of routing tables are prepared for each packet processing unit, By selecting a routing table and determining a route, it is possible to select whether to pass through the virtual packet processing unit.

According to a fourth packet processing device of the present invention, in the above-described packet processing device, the processor in each packet processing unit has a shared memory access management device, and virtualizes a packet when an access to the shared memory area occurs. It is characterized in that it is transmitted to a packet processing unit.

In the present invention, while realizing high-speed packet processing by the packet processing units distributed for each input line, the virtual packet processing unit can share information between packets input to the packet processing device from different input lines. It is possible.

Since only the packets that require information sharing pass through the virtual packet processing unit, the processing capacity required by the virtual packet processing unit can be reduced. Further, since the shared memory is not used, the speed of the packet processing unit does not decrease.

[0032]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a packet processing device according to one embodiment of the present invention. In FIG. 1, a packet processing apparatus 1 includes input lines 101,
102, packet processing units 11 and 12, a packet switch 13, a virtual packet processing unit 14, packet output processing units 15 and 16, output lines 109 and 110, and internal connection lines 103 to 108. I have.

Inputs of the packet processing units 11 and 12 are connected to input lines 101 and 102, respectively.
Outputs of the switches 1 and 12 are connected to inputs of the packet switch 13 via internal connection lines 103 and 104. The input of the packet switch 13 is the internal connection lines 103, 104, 1
The output of the packet switch 13 is connected to the input of each of the virtual packet processing unit 14 and the packet output processing units 15 and 16 via an internal connection line. 10
5, 107 and 108 are connected.

The input of the virtual packet processing unit 14 is connected to the output of the packet switch 13 via an internal connection line 105, and the output of the virtual packet processing unit 14 is connected to the input of the packet switch 13 via an internal connection line 106. You. The input of each of the packet output processing units 15 and 16 is connected to the output of the packet switch 13 via internal connection lines 107 and 108, respectively, and the output of each of the packet output processing units 15 and 16 is connected to output lines 109 and 110, respectively. Is done.

The packet processing units 11 and 12 execute the programs in the packets stored in the packets input from the input lines 101 and 102, respectively. By mounting a memory (not shown) in the packet processing units 11 and 12, information sharing between packets passing through the same packet processing unit is realized. The packet output according to the processing result of the program in the packet is the internal connection line 1.
The data is output to the packet switch 13 via the communication circuits 03 and 104.

One routing table (not shown) is prepared in the packet processing units 11 and 12, and the program in the packet determines the output line to which the packet is output by referring to the routing table.

Further, a plurality of routing tables (not shown) can be prepared in the packet processing units 11 and 12. In this case, the program in the packet can select and refer to one of the plurality of routing tables, and depending on the type of the routing table referred to by the program in the packet, whether or not to pass through the virtual packet processing unit 14 is determined. Is determined.

The packet switch 13 is provided with a packet switch element (not shown), and converts a packet input from the packet processing units 11 and 12 via the internal connection lines 103 and 104 into a packet of a program in the packet. Output lines 109 and 11 for the destination according to the processing result in the processing unit 11 or the packet processing unit 12.
0 or a packet switching process is performed on the virtual packet processing unit 14 so that the internal connection lines 105, 107,
8.

The virtual packet processing unit 14 executes a program in a packet stored in a packet input from the packet switch 13 via the internal connection line 105, and realizes functions equivalent to those of the packet packet processing units 11 and 12. Packets input to the packet processing apparatus 1 from different input lines pass through the virtual packet processing unit 14 so that information can be shared between the packets.

The packet output processing units 15 and 16 output the packets input from the packet switch 13 via the internal connection lines 107 and 108 to output lines 109 and 110, respectively.
Send to

FIG. 2 is a block diagram showing a configuration example of the packet processing units 11 and 12 and the virtual packet processing unit 14 of FIG. 2, the packet processing unit 2 shows a configuration example of the packet processing units 11, 12 and the virtual packet processing unit 14. The packet processing unit 2 includes a packet processing unit input line 201, a packet input processing unit 21,
2, the memory 23, and the packet processing unit output line 204
And internal connection lines 202 and 203.

The input lines 201 of the packet processing unit are the input lines 101 and 102 and the internal connection line 1 in the packet processing units 11 and 12 and the virtual packet processing unit 14, respectively.
05, which is connected to the input of the packet input processing unit 21. The input of the packet input processing unit 21 is connected to the packet processing unit input line 201,
Is connected to an input of the processor 22 via an internal connection line 202.

The input of the processor 22 is connected to the output of the packet input processing unit 21 via the internal connection line 202.
The output of the processor 22 is a packet processing unit output line 20.
4 and the processor 22 is connected to the memory 23 via an internal connection line 203 which is a memory access input / output line. The packet processing unit output lines 204 correspond to the internal connection lines 103, 104, and 106 in the packet processing units 11, 12 and the virtual packet processing unit 14, respectively, and are connected to the output of the processor 22.

In the packet input processing unit 21, the packet input from the packet processing unit input line 201 is output to the processor 22. In the processor 22, a program stored in a packet input from the packet input processing unit 21 via the internal connection line 202 is executed.

When a memory access instruction is executed in the program, the processor 22 accesses the memory 23. When a packet output instruction is executed in the program,
The packet is output to the packet switch 13. A part of the memory 23 has an area set as a shared memory. When a program accesses this space, the packet is transmitted via the packet processing unit output line 204 so as to pass through the virtual packet processing unit 14. Output to the switch 13.

The memory 23 stores various kinds of information referred to by the program in the packet. When a memory access instruction is executed by the processor 22, the internal connection line 20
3, the memory 23 is accessed in the form of reading and writing. The memory 23 stores a routing table, information on a host application, information on a packet processing device, information on a packet processing unit, and the like.

The memory 23 is provided with an area to which a program in a packet can write. A plurality of routing tables can be stored in the memory 23, and an area set as a shared memory can be prepared in a part of the routing table.

FIG. 3 is a flowchart showing an example of packet processing in the packet processing unit 2 of FIG. The packet processing in the packet processing unit 2 will be described with reference to FIGS.

The packet processing in the packet processing unit 2 is started when a packet arrives, and the packet is input from the packet processing unit input line 201 to the packet input processing unit 2.
1 (step S1 in FIG. 3). The packet input processing unit 21 outputs the packet to the processor 22 via the internal connection line 202 (Step S2 in FIG. 3).

The processor 22 interprets and executes the program stored in the packet (step S3 in FIG. 3). When the memory access instruction is included in the program (step S4 in FIG. 3), the processor 22 accesses the memory 23 via the internal connection line 203 (step S5 in FIG. 3).

When the packet output instruction is included in the program (step S6 in FIG. 3), the processor 22 outputs the packet to the packet processing unit output line 204 (step S7 in FIG. 3).

Further, when there is an instruction to access the shared memory area of the memory 23 in the program (step S8 in FIG. 3), the processor 22 sets the packet to pass through the virtual packet processing unit 14, and Is output to the packet processing unit output line 204 (step S9 in FIG. 3). When all packet processing ends, the packet processing unit 2 ends the processing.

As described above, while realizing high-speed packet processing, it is possible to share information between packets input to the packet processing apparatus 1 from different input lines. Since the packet processing units 11 and 12 operate almost independently, a high-speed packet processing device can be realized without depending on the number of input lines and the number of packet processing units.

In the configuration of the packet processing apparatus 1, a virtual packet processing unit 14 is arranged via a packet switch 13, and the respective packet processing units 11 and 12 operate almost independently. It is easy to do. Also, each packet processing unit 1
Since packets 1 and 12 are realized with the same configuration, the packet processing device 1 can be realized at low cost.

[0055]

As described above, according to the present invention, a plurality of input lines and output lines, a packet processing unit arranged for each input line, and switching of the output of the packet processing unit to a plurality of output lines. A packet switch for processing;
A packet output processing unit that outputs an output of the packet switch to a plurality of output lines, and a packet processing device of a built-in program type that processes a packet in which a processing method of the packet is described in the packet based on the description. By enabling a packet with a program built in from the outside to reach a virtual packet processing unit that receives the output of a packet switch instead of an input line from the outside, high-speed packet switching processing can be performed.
There is an effect that information sharing between packets input from different input lines can be realized without using a shared memory.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a packet processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a packet processing unit and a virtual packet processing unit in FIG. 1;

FIG. 3 is a flowchart illustrating an example of packet processing in a packet processing unit in FIG. 2;

FIG. 4 is a block diagram showing a configuration of a conventional packet processing apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Packet processing apparatus 2, 11, 12 Packet processing unit 13 Packet switch 14 Virtual packet processing unit 15, 16 Packet output processing unit 21 Packet input processing unit 22 Processor 23 Memory 101, 102 Input line 103-108, 202, 203 Internal connection Line 109, 110 Output line 201 Packet processing unit input line 204 Packet processing unit output line

Claims (8)

[Claims] A plurality of input lines and an output line; a packet processing unit arranged for each of the input lines; a packet switch for performing an exchange process of an output of the packet processing unit to the plurality of output lines; A packet output processing unit that outputs an output of a packet switch to the plurality of output lines, and a packet processing device of a built-in program type that processes a packet in which a processing method of the packet is described in the packet based on the description. A virtual packet processing unit that receives the output of the packet switch in place of an external input line, and is configured so that a packet with a built-in program input from the outside can reach the virtual packet processing unit. A packet processing device characterized by the above-mentioned. An output line that includes a plurality of routing tables provided in the packet processing unit, and outputs a packet when a program described in the packet selects one of the plurality of routing tables. 2. The method according to claim 1, wherein the determination is made.
The packet processing device according to claim 1. 3. The packet processing apparatus according to claim 2, wherein the program is configured to select whether or not the packet passes through the virtual packet processing unit when determining the output line. apparatus. 4. The packet processing unit according to claim 1, further comprising means for transmitting the packet to the virtual packet processing unit when detecting access to a preset shared memory area. The packet processing device according to any one of the above. 5. A plurality of input lines and output lines, a packet processing unit arranged for each of the input lines, a packet switch for performing an exchange process of an output of the packet processing unit to the plurality of output lines, A packet output processing unit that outputs an output of a packet switch to the plurality of output lines, and a packet processing device of a built-in program type that processes a packet in which a processing method of the packet is described in the packet based on the description. A packet processing method, wherein an externally input packet with a built-in program can reach a virtual packet processing unit that receives an output of the packet switch instead of an input line from the outside. . 6. A program described in the packet selects one of a plurality of routing tables provided in the packet processing unit to determine an output line to which the packet is output. The packet processing method according to claim 5, wherein 7. The program according to claim 6, wherein when the program determines the output line, it is possible to select whether or not the packet passes through the virtual packet processing unit.
The described packet processing method. 8. The packet processing unit according to claim 5, further comprising a step of transmitting the packet to the virtual packet processing unit when detecting access to a preset shared memory area. The packet processing method according to any one of the above.