JP2002217709A - Programmable logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a programmable logic circuit that can build up a logic circuit without causing waste of cells and global wires. SOLUTION: A cell 10 is configured with a logic block 13 that conducts N-bit input logical arithmetic operations, a switching module 11 where inter- wires N, E, S, W and global wires GH, GV are used for the connection to the logic block 13, and a controller 12 that controls the switching module 11 and the logic block 13. The switching module 11 comprises a 1st switching matrix that connects the logic block included in the cell to other cell and a 2nd switching matrix that interconnects other cells.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a programmable logic circuit, and more particularly to a programmable logic circuit that allows a user to realize various functions by a program.

[0002]

2. Description of the Related Art Programmable logic circuits, such as PLDs (Programmable Logic Devices) and FPGAs (Field Programmable Gate Arrays), which allow users to realize various functions by programs, have been rapidly developed in recent years. By increasing the degree of integration and the speed of such a programmable logic circuit, the hardware configuration can be changed according to the application as well as the simulation at the time of the conventional ASIC (application-specific integrated circuit) design and simple replacement of peripheral circuits. It is being considered for use on reconfigurable computers.

FIG. 5 is a diagram showing a configuration of a conventional cell array type programmable logic circuit, and shows a state where they are arranged in a two-dimensional array. In FIG. 5, each cell can be connected to an adjacent cell using an internal wiring. Here, the term “adjacent” means that adjacent cells are adjacent one by one, and one cell is adjacent to four cells. For example, cell 50 is composed of cells 51-5
Adjacent to 4. At this time, the cell 50 is connected to the adjacent cell 51.
To 54 through the inter-adjacent wires 55 to 58. In addition, the connection with cells other than the adjacent cells 51 to 54 is often made via global wirings 59 and 60 and the like.

FIG. 6 is a conceptual diagram showing an example of the internal structure of the cell 50 shown in FIG. In FIG. 6, a cell 50 has a logic block 63 for performing a logical operation of an N-bit input,
5 and the global wirings 59 and 6 in FIG.
And a controller 62 for controlling the switching module 61 and the logic block 63.
It is composed of In the switching module 61, what kind of connection is made is programmable, and is determined based on configuration data stored in a configuration memory (not shown).
1 is provided with connection information.

For example, assuming that the logic block 63 is a three-input one-output logic block, a conceptual diagram showing the internal structure of the switching module 61 is as shown in FIG. In this case, the switching modules 61 are arranged in a matrix of 4 rows and 6 columns, and the adjacent wires N, E,
S, W and global wirings GH, GV are logical blocks 63
Acts as a switching matrix for input / output wiring to
The connection between the wirings is arbitrary, and the controller 62 supplies connection information to the switching module 61.

FIG. 8 shows an example using a programmable logic circuit.
FIG. 3 is a diagram illustrating an example in which a certain circuit configuration is arranged. In FIG. 8, a logic block 90 of a cell 80 receives a signal from a cell 81 via a wiring 95, receives a signal via two global wirings 93 and 94, and outputs an operation output through a wiring 96. It is supplied to the cell 85. A constant “1” is supplied to the global wiring 93. At this time, the output of the logic block 91 in the cell 82 is output to the cell 8
It is assumed that data is supplied to the input section of the logic block 92 in 3. The output of the logic block 91 in the cell 82 is once supplied to the cell 84 via the wiring 97. Next, data is supplied to the cell 86 via the global wiring 98, and data is supplied from the cell 86 to the logic block 92 in the cell 83 via the wiring 99.

FIG. 9A shows a connection example of the cells 80 included in FIG. The logic block 90 included in the cell 80 receives the global wirings GH, GV and the wiring N as inputs and outputs an operation output to the wiring S. At this time, the wiring state of the switching module 61 in the cell 80 is shown in FIG. The switching module 61 is connected to the global wirings GH, GV, and wiring N as inputs,
Are output as shown in FIG. 9B to output to the wiring S.

[0008]

FIG. 9 (a)
As shown in the figure, when the cell 80 functions as a three-input one-output arithmetic unit that receives the global wirings GH and GV and the wiring N and outputs an operation output to the wiring S,
Cannot directly connect the wiring W and the wiring E.
For this reason, as shown in FIG. 8, in order to supply data from the output of the logic block 91 in the cell 82 to the input of the logic block 92 in the cell 83, when the global wiring 93 is used, Data must be exchanged through a route that avoids Therefore, the cell 84
A cell for wiring purpose such as a cell or a cell 86 is generated. This causes a waste of cells and global wiring in the programmable logic circuit, which is one of the causes of reducing the degree of freedom in cell arrangement.

In the above-described cell 80, when the logic block 90 requests a constant “0” or a constant “1” as a data input, as shown in FIG.
Must be supplied with constant "0" or constant "1" as data from another cell through the global wiring 93 or the like. This also causes waste of cells and global wiring in programmable logic circuits,
This is one factor that reduces the degree of freedom in cell arrangement.

[0010] Therefore, a main object of the present invention is to provide a programmable logic circuit capable of constructing a logic circuit without wasting cells and global wiring.

[0011]

According to the present invention, there are provided a plurality of cells each having a storage block therein and having a logic block for realizing a desired logical operation by the storage section and a switching matrix for determining a connection state of a wiring group. A switching matrix included in a certain cell, a first switching matrix for connecting a logic block included in the cell to another cell, and a second switching matrix for connecting a plurality of other cells. 2 switching matrices.

Thus, adjacent cells can be directly connected to each other while performing a logical operation in the same cell, so that the degree of freedom in cell arrangement can be increased and cells and global wiring are not wasted. A logic circuit can be constructed.

The second switching matrix is:
It is characterized in that a connection between a plurality of cells, a power supply line, a ground line, and a logic block is performed.

Further, the programmable logic circuit is constituted by a semiconductor device.

[0015]

FIG. 1 is a conceptual diagram of a cell showing an example of the internal structure of a cell array type programmable logic circuit according to an embodiment of the present invention. In FIG. 1, a cell 10 includes a logic block 13 for performing a logical operation of an N-bit input;
Adjacent wires N, E, S, W and global wires GH, GV
A switching module 11 capable of connecting to a logic block 13 and a switching module 1
1 and a controller 12 for controlling the logic block 13. In the switching module 11, what kind of connection is made is programmable, is determined based on configuration data stored in a configuration memory (not shown), and the controller 12 supplies connection information to the switching module 11.

FIG. 2 is a conceptual diagram showing an internal configuration of a switching module 11 formed in a cell 10 of a programmable logic circuit according to an embodiment of the present invention. FIG.
1, the switching module 11 includes a first switching matrix 21 and a second switching matrix 22. Assuming that the logic block 13 shown in FIG. 1 is a three-input one-output logic block, the first switching matrix 21 is arranged in a matrix of four rows and six columns, and the external wirings N, E, S, W, GH, GV and input / output wirings In1, In2, In3, O to logic block 13
It works as a switching matrix with ut.

The connection between the wirings is arbitrary, and the controller 12 supplies connection information to the first switching matrix 21. The second switching matrix 22 is arranged in a matrix crossing only the wirings N, E, S, W, GH, and GV. Therefore, it is possible to directly connect between adjacent cells or between global wirings. Also,
The second switching matrix 22 has a ground line representing a constant “0” and a power supply line representing a constant “1” serving as a switching matrix for input / output wiring to the logic block 13. The connection between each wiring is optional, and the controller 1
2 to the second switching matrix 22.

FIG. 3 is a diagram showing an example in which a circuit configuration is arranged using a programmable logic circuit according to an embodiment of the present invention. In FIG. 3, a signal supplied from the cell 31 via the wiring 45 and a signal supplied via the global wiring 44 are input to the logic block 40 in the cell 30. In one embodiment of the present invention, since the cell 30 can supply the constant "1" or the constant "0" by itself, the constant value is not supplied from another cell via the global wiring 43 or the like.

The operation output of the logic block 40 is supplied to the cell 35 via the wiring 46. Here, it is assumed that the output of the logic block 41 in the cell 32 is supplied to the input of the logic block 42 in the cell 33 at the same time. First, the output of the logic block 41 in the cell 32 is supplied to the cell 30 via the wiring 47. Next, the data signal of the wiring 47 is supplied to the wiring 48 because the cell 30 can directly connect between adjacent cells or between global wirings.

Finally, data is supplied to the cell 33 via the wiring 48, and data is supplied to the input of the logic block 42 in the cell 33. This means that the cells 84 and 86 and the global wiring 98 required for the wiring shown in FIG. 8 are not required, and a logic circuit can be constructed without wasting cells and global wiring. .

According to the connection example shown in FIG. 3, the global wiring 43 is not used. Therefore, other data signals not shown in the connection example of FIG.
And the degree of freedom for wiring can be further increased.

FIG. 4 is a diagram showing a connection example of the cells 30 in one embodiment of the present invention. In FIG. 4, cell 30
4A, the data supplied from the global wiring GV and the wiring N and the constant "1" from the cell 30 itself are supplied to the logic block 40 in FIG. The calculation output is supplied to the wiring S. At the same time, the wiring W and the wiring E are connected.

FIG. 4B shows the wiring status of the switching module 11 at this time. FIG.
As shown in (b), the first switching matrix 2
Numeral 1 supplies data to the logic block 63 via the global wiring GV and the wiring N. In addition, connection for outputting the operation result to the wiring S is performed. At the same time, in the second switching matrix 22, the power supply line VDD indicating the constant "1"
Is supplied to the logic block 40. Further, the wiring W and the wiring E can be connected, and the wiring W and the wiring E which are not related to the operation exchange data via the cell 30.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0025]

As described above, according to the present invention, adjacent cells can be directly connected while performing a logical operation in the same cell, so that the degree of freedom in cell arrangement can be increased. Therefore, a logic circuit can be constructed without wasting cells and global wiring. Further, since the cell itself requiring the constant “1” or the constant “0” can supply the constant “1” or the constant “0” on its own, the degree of freedom in cell arrangement can be further increased. . Therefore, a logic circuit can be constructed without causing waste of cells and global wiring.

[Brief description of the drawings]

FIG. 1 is a diagram showing one example of a cell structure of a programmable logic circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a switching module of a programmable logic circuit according to an embodiment of the present invention.

FIG. 3 is an overall view showing a connection example of a programmable logic circuit according to an embodiment of the present invention.

FIG. 4 is a diagram showing one connection example using a switching module of a programmable logic circuit.

FIG. 5 is an overall view for explaining a conventional programmable logic circuit.

FIG. 6 is a diagram showing an example of one cell structure of a conventional programmable logic circuit.

FIG. 7 is a diagram showing a conventional switching module of a programmable logic circuit.

FIG. 8 is an overall view showing one connection example of a conventional programmable logic circuit.

FIG. 9 is a diagram illustrating a connection example using a conventional switching module of a programmable logic circuit.

[Explanation of symbols]

10, 30 to 36 one cell of a programmable logic circuit, 11 switching modules, 12 controllers, 13, 40 to 42 logic blocks, 21 first switching matrix, 22 second switching matrix, 43, 44, 49 global wiring, 45-48
Wiring with adjacent cells as viewed from cell 30.

Claims (3)

[Claims] 1. A programmable logic circuit having a plurality of cells having a storage unit therein, and a plurality of cells having a logic block for realizing a desired logical operation by the storage unit and a switching matrix for determining a connection state of a wiring group. A first switching matrix in which a switching matrix included in a certain cell connects a logic block included in the cell to another cell; a second switching matrix in which a plurality of other cells are connected to each other; A programmable logic circuit, comprising: 2. The second switching matrix according to claim 1, wherein:
2. The programmable logic circuit according to claim 1, wherein a connection between a plurality of cells, a power supply line, and a ground line is connected to the logic block. 3. The programmable logic circuit according to claim 1, wherein said programmable logic circuit comprises a semiconductor device.