JP2002217408A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately control impurity concentration at the end of a drain region in an MIS transistor with groove type gate electrode structure and to cope also with a shorter channel. SOLUTION: An element splitting area 2 is formed on a semiconductor substrate 1 to form a semiconductor region as a source area and a drain region in an element region, and then an interlayer insulation film 10 is formed on the entire surface of the substrate. An opening 11 is formed therein, and the interlayer insulation film 10 is etched through the opening 11, until the substrate 1 is exposed, and a groove 5 having a reverse-trapezoidal cross section is formed and then the semiconductor region is divided into a source region 3 and a drain region 4. After an insulation film 6 is formed on the bottom and sidewall of the groove 5, impurity ions are implanted in the direction inclining with respect to the main surface of the substrate 1, while using the interlayer insulation film 10 as a mask. Thus, a diffusion layer 9, whose impurity concentration is lower than the drain region 4, is formed integrally together with the drain region 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a MIS transistor having a so-called trench-type gate electrode structure.

[0002]

2. Description of the Related Art In order to form a high-performance MOS transistor, it is necessary to make a gate insulating film thinner and a gate electrode finer (shorter gate length). The decrease in the reliability of the gate insulating film due to the increase in leakage current due to direct tunneling, but for the latter, the height of the gate electrode is increased to suppress the increase in the resistance of the gate electrode as the gate electrode width is reduced. An increase in the step of the gate electrode due to the necessity to make it happen has become a problem.

As a solution to these problems, a high dielectric film such as a tantalum oxide film is adopted as a gate insulating film for the former problem, and low-resistance tungsten (W) is used as a gate electrode material for the latter problem. The adoption of metals such as these has been studied. However,
When a high dielectric film is applied to the gate insulating film, silicon (Si) is formed by a high-temperature heat treatment step (for example, 800 to 1000 ° C.) necessary for forming a source region and a drain region.
An interface reaction between the substrate and the gate insulating film or an interface reaction between the gate insulating film and the gate electrode occurs, which causes a failure. On the other hand, the gate electrode made of metal (metal gate electrode) also has heat resistance (400 to 50).
0 ° C.) and cannot withstand high-temperature heat treatment. For these reasons, it has been difficult in the conventional manufacturing process to obtain a MOS transistor having good electrical characteristics.

One of the solutions is to use a so-called trench type gate electrode structure (also called a buried gate electrode structure).
OS transistors have been proposed (see, for example,
-5855). FIG. 7 schematically shows the structure.

As shown in FIG. 7, in a conventional MOS transistor having a trench type gate electrode structure, an element isolation oxide film 102, an n ⁺ type source region 103 and a drain region 104 are provided on a p type Si substrate 101. , Having a rectangular cross-sectional shape extending in the channel width direction at a portion between source region 103 and drain region 104.
5 are provided. An interlayer insulating film 1 is formed on the element isolation oxide film 102, the source region 103 and the drain region 104.
06 is provided. The groove 1 is formed in the interlayer insulating film 106.
An opening 107 is provided on the opening 05. A gate electrode 109 is embedded in the trench 105 and the opening 107 via a gate insulating film 108. On the interlayer insulating film 106, an interlayer insulating film 110 is provided so as to cover the gate electrode 109. Openings 111 and 112 are provided in predetermined portions of the interlayer insulating films 106 and 110 above the source region 103 and the drain region 104. Inside these openings 111 and 112, wiring connection layers 11 are respectively provided.
3 and 114 are embedded, and these wiring connection layers 1
Wiring layers 115 and 116 are connected on 13 and 114, respectively.

The feature of the MOS transistor having the trench type gate electrode structure is that the MOS transistor has n and n regions serving as source and drain regions.
After forming the ⁺ type semiconductor layer, a groove 1 is formed in the gate electrode forming portion.
The gate insulating film 10 is formed inside the trench 105.
8 is used to embed the gate electrode 109 via the manufacturing process flow. In this manufacturing process flow, the source region 103 and the drain region 1
By forming the gate insulating film 108 and the gate electrode 109 after the formation of the gate insulating film 04, a high dielectric film such as a tantalum oxide film can be applied to the gate insulating film 108, or a metal such as W can be used as a material of the gate electrode 109. Even so, there is an advantage that there is no adverse effect due to the high-temperature heat treatment step required for forming the source region 103 and the drain region 104.

On the other hand, in order to form a high-performance MOS transistor, drain engineering is important. The drain engineering is a technique for improving the performance while maintaining the reliability of the transistor by controlling the impurity concentration at the end of the drain region by, for example, an ion implantation technique.

[0008]

However, in the above-mentioned conventional MOS transistor having the trench type gate electrode structure, since the source region and the drain region are formed before the gate electrode is formed, the impurity concentration at the end of the drain region may be delicate. It is difficult to control. Further, it is necessary to further shorten the channel in order to further improve the performance of the MOS transistor. However, in order to shorten the gate length, the width of the bottom surface of the trench 105 must be reduced. In addition, it becomes difficult to perform drain engineering, and it becomes difficult to bury a gate electrode material in the trench 105.

Therefore, the problem to be solved by the present invention is to control the impurity concentration at the end of the drain region of a MIS transistor having a trench-type gate electrode structure with high accuracy, and to sufficiently cope with a short channel. And a method of manufacturing the same.

[0010]

According to a first aspect of the present invention, a gate electrode is buried in a groove provided in a semiconductor substrate via a gate insulating film. A semiconductor device having a MIS transistor having a groove-type gate electrode structure in which a source region and a drain region are provided in a semiconductor substrate on both sides in a shallower depth than a groove, wherein the groove has an inverted trapezoidal cross-sectional shape. A diffusion layer having the same conductivity type as the drain region and a lower impurity concentration than the drain region is provided integrally with the drain region on the semiconductor substrate in a portion adjacent to the lower portion of the side wall on the drain region side. .

According to a second aspect of the present invention, a step of forming an element isolation region in a semiconductor substrate, a step of forming a semiconductor region serving as a source region and a drain region in an element region surrounded by the element isolation region, A step of forming an interlayer insulating film so as to cover the region, a step of forming an opening in a predetermined portion of the interlayer insulating film, and forming a groove having an inverted trapezoidal cross section reaching the semiconductor substrate in the opening, Forming a source region and a drain region by dividing the semiconductor region by the groove, forming a gate insulating film at least on the bottom surface of the groove, and ion-implanting impurities from a direction inclined with respect to the main surface of the semiconductor substrate Accordingly, at least the portion of the semiconductor substrate adjacent to the lower portion of the side wall of the trench on the drain region side has the same conductivity type as the drain region and a lower impurity than the drain region Forming a diffusion layer of the concentration integrally with the drain region, a method of manufacturing a semiconductor device characterized by a step of embedding the gate electrode through a gate insulating film in the trench.

In the present invention, the angle formed between the main surface of the semiconductor substrate and the side wall of the groove is generally selected from 89 to 75 degrees, preferably from 88 to 80 degrees. Typically, for example, the thickness of the interlayer insulating film provided so as to cover the source region and the drain region is 100 to 300 nm, the depth of the source region and the drain region is 100 to 800 nm, and the source region, the drain region, and the trench are formed. Depth difference is 10-50n
m. Further, the ratio of the width of the bottom surface of the groove to the projection width of the side wall of the groove on the main surface of the semiconductor substrate is preferably approximately 2, specifically, for example, 2 ± 0.2: 1, and more preferably. 2 ± 0.1:
Selected as 1. The width of the bottom surface of the groove corresponds to the channel length and is selected as needed, but is, for example, 10 to 50 nm.
Ion implantation of impurities for forming a diffusion layer having a lower impurity concentration than the drain region in the semiconductor substrate in a portion adjacent to the lower portion of the side wall on the drain region side of the trench is typically performed.
This is performed from a direction inclined by 89 to 84 degrees with respect to the main surface of the semiconductor substrate.

According to the present invention constructed as described above, the groove provided between the source region and the drain region has an inverted trapezoidal cross section, so that the side wall of the groove is formed on the main surface of the semiconductor substrate. And the angle of the impurity ion implantation performed after the formation of the groove, the impurity can be accurately implanted to an arbitrary concentration only at the end of the drain region below the side wall of the groove. Further, the channel length can be determined by the width of the bottom surface of the groove. Furthermore, since the groove has a shape extending from the lower part to the upper part, even if the channel is shortened, in other words, even if the width of the bottom surface of the groove is reduced,
Embedding with a gate electrode material can be easily performed. In addition, since the amount of the gate electrode material embedded in the trench can be sufficiently increased, the resistance of the gate electrode can be suppressed low.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

FIG. 1 shows a semiconductor device according to one embodiment of the present invention. As shown in FIG. 1, in this semiconductor device, an element isolation oxide film 2 made of, for example, an SiO ₂ film is selectively provided on a p-type semiconductor substrate 1 such as a p-type Si substrate. Have been done. The p-type semiconductor substrate 1 contains 1 × 10 boron (B) as a p-type impurity, for example.
Doped at a concentration of ¹¹ cm ^-3 . Here, the p-type semiconductor substrate 1 includes a p-well formed on the semiconductor substrate. The thickness of the element isolation oxide film 2 is, for example, 30
0 nm. For example, an n ⁺ -type source region 3 and a drain region 4 are formed in an element region surrounded by the element isolation oxide film 2.
Is provided. The depth (thickness) of these source region 3 and drain region 4 is, for example, 300 nm. These source region 3 and drain region 4 are doped with, for example, phosphorus (P) as an n-type impurity at a concentration of 5 × 10 ¹⁵ cm ⁻³ .

A groove 5 having an inverted trapezoidal cross section extends between the source region 3 and the drain region 4 in the channel width direction. A gate insulating film 6 is provided on the bottom and side walls of the groove 5. As the gate insulating film 6, for example, a tantalum oxide film is used. Since tantalum oxide has a higher dielectric constant than silicon oxide, the thickness of this tantalum oxide film is set to, for example, 3 nm in terms of a silicon oxide film. Groove 5 via gate insulating film 6
, A gate electrode 7 made of, for example, W is buried. Here, the gate electrode 7 made of W does not react with the tantalum oxide film used as the gate insulating film 6,
In addition, the sheet resistance of W is 1 Ω / □, which is much smaller than the typical sheet resistance of 50 Ω / □ of polycrystalline Si usually used as a gate electrode material, so that the gate resistance can be sufficiently reduced. . On the p-type semiconductor substrate 1 in a portion adjacent to the gate insulating film 6 below both side walls of the trench 5, for example, n ⁻ -type low impurity concentration layers 8 and 9 having a lower impurity concentration than the source region 3 and the drain region 4 are provided. Have been. These low impurity concentration layers 8 and 9 are doped with, for example, arsenic (As) as an n-type impurity.
These low impurity concentration layers 8 and 9 correspond to the source region 3 respectively.
And a part of the source region 3 and the drain region 4. In this case, the channel length of the MOS transistor is equal to the width of the bottom of groove 5 parallel to the main surface of semiconductor substrate 1. The width of the bottom surface of the groove 5, that is, the channel length is determined as necessary, but can be set to, for example, 10 to 50 nm.

On the element isolation oxide film 2, the source region 3 and the drain region 4, an interlayer insulating film 10 such as a SiO ₂ film is provided. An opening 11 is provided in a portion of the interlayer insulating film 10 above the groove 5, and an upper portion of the gate electrode 7 is buried in the opening 11. An interlayer insulating film 12 such as a SiO ₂ film is provided on the interlayer insulating film 10 so as to cover the gate electrode 7. Openings 13 and 14 are provided in predetermined portions of the interlayer insulating film 12 and the interlayer insulating film 10 above the source region 3 and the drain region 4, respectively. These openings 13,
Wiring connection layers 15 and 16 made of, for example, W are buried in the wirings 14, and aluminum (A) containing copper (Cu), for example, is
l) Wirings 17 and 18 are connected.

Next, a method of manufacturing the semiconductor device configured as described above will be described. 2 to 6 show this manufacturing method. First, as shown in FIG. 2A, an element isolation oxide film 2 such as a SiO ₂ film is formed on the entire surface of a p-type semiconductor substrate 1 by, for example, a chemical vapor deposition (CVD) method.

Next, as shown in FIG. 2B, a portion of the device isolation oxide film 2 corresponding to the device region of the MOS transistor is removed by etching, and the device isolation oxide film 2 is left only in the device isolation region. Specifically, for example, after forming a resist pattern (not shown) having a predetermined shape with an opening corresponding to the element region on the element isolation oxide film 2 by lithography, the element isolation oxide film is used as a mask. The film 2 is etched. Next, an n ⁺ -type amorphous Si film 19 doped with, for example, P at a concentration of 5 × 10 ¹⁵ cm ⁻³ is formed on the entire surface of the substrate by, for example, a CVD method. The thickness of the n ⁺ type amorphous Si film 19 is, for example, 600
nm.

Next, as shown in FIG. 2C, the n ⁺ type amorphous Si film 19 is polished by, for example, a chemical mechanical polishing (CMP) method until the element isolation oxide film 2 is exposed. This n is applied only to the element region surrounded by oxide film 2.
^{The +} type amorphous Si film 19 is left. Next, as shown in FIG. 3A, an interlayer insulating film 10 such as an SiO ₂ film is formed on the entire surface of the substrate by, for example, a CVD method, and a resist pattern 20 having a predetermined shape is formed on the interlayer insulating film 10 by lithography. After that, the opening 11 is formed by etching the interlayer insulating film 10 using the resist pattern 20 as a mask.

Next, after the resist pattern 20 is removed, as shown in FIG. 3B, the n ⁺ -type amorphous Si film 19 and the p
The mold semiconductor substrate 1 is etched. At this time, by performing etching so as to form a taper at a predetermined angle with the main surface of the n ⁺ -type amorphous Si film 19, the groove 5 having an inverted trapezoidal cross-sectional shape can be formed. The trench 5 divides the n ⁺ type amorphous Si film 19 into two, one of which becomes the source region 3 and the other becomes the drain region 4.

Next, as shown in FIG. 3C, a gate insulating film 6 made of a tantalum oxide film is formed by, for example, a reactive sputtering method. Here, in this reactive sputtering, the target of tantalum is argon (A
r) Sputtering is performed in a mixed gas atmosphere of oxygen (O ₂ ) and tantalum oxide is deposited on the substrate. At this time, since the substrate is exposed to the plasma atmosphere, the substrate is easily damaged. Therefore, in order to solve the problem caused by this damage, heat treatment is performed in an oxygen atmosphere after forming the gate insulating film 6 made of a tantalum oxide film, and the gate insulating film 6, the p-type semiconductor substrate 1, the source region 3, and the drain region are formed. Then, a thin SiO ₂ film (not shown) is formed at the interface with the substrate 4.

Next, as shown in FIG. 4A, the interlayer insulating film 1 is formed.
By using 0 as a mask, an n-type impurity such as As is ion-implanted from a direction A and a direction B inclined at a predetermined angle with respect to the main surface of the p-type semiconductor substrate 1 in a plane perpendicular to the channel width direction. Thereby, n ⁻ -type low impurity concentration layers 8 and 9 are formed integrally with source region 3 and drain region 4 only in p-type semiconductor substrate 1 in portions adjacent to gate insulating film 6 below both side walls of trench 5. Form.

Here, conditions required for forming the low impurity concentration layers 8 and 9 only on the p-type semiconductor substrate 1 in a portion adjacent to the gate insulating film 6 below the side walls of the trench 5 will be considered. . FIG. 5 is an enlarged view of a portion near the groove 5 before ion implantation, and the illustration of the gate insulating film 6 is omitted. In FIG. 5, D ₁ is the thickness of the interlayer insulating film 10, D ₂ is the source region 3 and the depth of the drain region 4 (thickness), D ₃ is the depth of the source region 3 and drain region 4 and the groove 5 difference, L is equal to the channel length by the width of the bottom surface of the groove 5, X ₁ is equal to the width of the opening 11 of the interlayer insulating film 10 at the top of the opening width of the groove 5, X ₂ is the p-type semiconductor substrate 1 Is the projected width of the side wall of the groove 5 and θ ₁ is
The angle θ ₂ between the main surface of the semiconductor substrate 1 and θ ₂ is set so that the low impurity concentration layers 8 and 9 are formed only on the p-type semiconductor substrate 1 in portions adjacent to the gate insulating film 6 below the side walls of the groove 5. Shows the angle of ion implantation necessary for the above. The following equation holds between these parameters.

L = X ₁ −2X ₂ (1) θ ₁ = arctan [(D ₂ + D ₃ ) / X ₂ ] (2) θ ₂ = arctan [(D ₁ + D ₂ + D ₃ ) / (L + X ₂ )] (3)

In this case, for example, D ₁ , D ₂ , D ₃ , X
₁ is determined first, X ₂ is determined so as to obtain a desired L from equation (1), θ ₁ is determined from equation (2), and θ ₂ is determined from equation (3).

D ₁ and D ₂ facilitate the formation of the groove 5,
In order to easily embed the gate electrode 7 in the trench 5, it is desirable that the gate electrode 7 is small. However, if D ₂ is too small, the resistance of the source region 3 and the drain region 4 becomes too high. , D ₁ is too small, electrical insulation cannot be performed sufficiently. Therefore, from these viewpoints, D ₁ is preferably 10
From 0 to 300 nm, D ₂ is the 100 to 800 nm. D ₃ is preferably set to 10 to 50 nm for the purpose of effectively reducing the electric field at the end of the drain region 4 by the low impurity concentration layer 9.

The relationship between X ₂ and L is preferably L: X ₂ ≒ 2: 1. In this case, equation (1), (2)
The equation and the equation (3) are as shown in the following equations (4), (5) and (6). L = (1/2) X ₁ (4) θ ₁ = arctan [2 (D ₂ + D ₃ ) / L] (5) θ ₂ = arctan [2 (D ₁ + D ₂ + D ₃ ) / 3L] (6)

Next, the optimum conditions of the inclination angle of the side wall of the groove 5 and the ion implantation angle will be considered. Basically,
Since the inclination angle of the side wall of the groove 5 affects the concentration of the electric field at the vertex, it is desirable that the inclination angle be large in order to reduce the electric field. On the other hand, the thickness of the source region 3 and the drain region 4 and the thickness of the interlayer insulating film 10 are desirably smaller from the viewpoint of easily processing the groove 5 and filling the groove 5 with the gate electrode 7. However, among these, in particular, the source region 3 and the drain region 4
However, there is a limit to the thickness of the thin film because it is necessary to keep their resistance below a certain value.

Within the above range of conditions, the optimum value of each parameter is as follows when the channel length L is 10 to 50 nm.
For example, it is as follows. D ₁ = 200 nm D ₂ = 200 nm D ₃ = 20 nm X ₂ ≒ (1/2) L = 5 to 25 nm θ ₁ = 88 to 80 degrees θ ₂ = 89 to 84 degrees

Therefore, the above-described ion implantation is performed, specifically, at θ ₂ = 89-84 degrees, for example, in the directions A and B in FIG.
By performing the process twice in total from the direction, the low impurity concentration layers 8 and 9 are respectively formed only in the p-type semiconductor substrate 1 in a portion adjacent to the gate insulating film 6 below the both side walls of the trench 5.
And the drain region 4. The conditions for the two ion implantations are, for example, that As is used as an n-type impurity, the energy is ¹⁵ keV, and the dose is 1 × 10 ¹⁵ c.
m ^-2 .

Next, as shown in FIG. 4B, a W film 21 is formed as a gate electrode material on the entire surface of the substrate by, for example, a CVD method. The thickness of the W film 21 is, for example, 600 nm. Next, as shown in FIG. 4C, the W film 21 is
Unnecessary portions of the W film 21 on the interlayer insulating film 10 are removed by polishing by the P method until the interlayer insulating film 10 is exposed. As a result, a gate electrode 7 made of W embedded in the trench 5 and the opening 11 of the interlayer insulating film 10 is formed.

Next, as shown in FIG. 6A, after an interlayer insulating film 12 such as an SiO ₂ film is formed on the entire surface of the substrate by, eg, CVD, the source of the interlayer insulating film 12 and the interlayer insulating film 10 is formed. Openings 13 and 14 are formed by etching away predetermined portions on the region 3 and the drain region 4.

Next, W is formed on the entire surface of the substrate by, for example, the CVD method.
After forming the film to a thickness enough to fill the openings 13 and 14,
The W film is polished by, eg, CMP until the interlayer insulating film 12 is exposed. As a result, as shown in FIG. 6B, wiring connection layers 15 and 16 made of W embedded in the openings 13 and 14 are formed.

Next, an Al film containing, for example, Cu is formed on the entire surface of the substrate by, for example, a sputtering method.
Is patterned into a predetermined shape by etching to form wiring layers 17 and 18. Thus, the intended semiconductor device is manufactured.

According to this embodiment, the following various advantages can be obtained. That is, by setting the angle of inclination of the side wall of the groove 5 and the angle of ion implantation for forming the low impurity concentration layers 8 and 9 to the optimum angle, only the end of the drain region 4 below the side wall of the groove 5 is formed. The low impurity concentration layer 9 can be formed by ion-implanting n-type impurities with high precision, and delicate drain engineering becomes possible. Further, since the groove 5 has a tapered shape, even if the upper opening width of the groove 5 is substantially increased to a certain extent, an ultra-short channel can be achieved. It is possible to make the margin for filling the groove 5 sufficiently large. Further, since the amount of the gate electrode material embedded in the groove 5 can be increased, the resistance of the gate electrode 7 can be sufficiently suppressed even if the channel is shortened.

The semiconductor device according to this embodiment has an MO
SLSI, CMOS LSI, Bipolar-CMOSLS
It can be applied to various semiconductor devices using MOS transistors such as I, and can be used for various applications such as semiconductor memories and logic LSIs.

As described above, one embodiment of the present invention has been specifically described. However, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible. .

For example, the numerical values, structures, shapes, processes, and the like mentioned in the above-described embodiment are merely examples, and different numerical values, structures, shapes, and the like may be used as necessary.
A process or the like may be used.

In the above-described embodiment, the case where the n-channel MOS transistor is formed on the p-type semiconductor substrate 1 has been described. However, the present invention relates to the case where the p-channel MOS transistor is formed on the n-type semiconductor substrate. Of course, the present invention can be applied to a case where a complementary MOS transistor is formed.

[0041]

As described above, according to the present invention, an inverted trapezoidal groove for embedding a gate electrode is provided between a source region and a drain region.
At least a diffusion layer having the same conductivity type as the drain region and a lower impurity concentration than the drain region is provided integrally with the drain region on the semiconductor substrate in a portion adjacent to a lower portion of the side wall of the trench on the drain region side, so that the impurity at the end of the drain region is provided. The concentration can be controlled with high precision, and delicate drain engineering can be performed. In addition, it is possible to sufficiently cope with a short channel.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a cross-sectional view showing a conventional MOS transistor having a trench-type gate electrode structure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p-type semiconductor substrate, 2 ... element isolation oxide film, 3
... Source region, 4 ... Drain region, 5 ...
Groove, 6 gate insulating film, 7 gate electrode, 8,
9 ... low impurity concentration layer, 10, 12 ... interlayer insulating film

Claims (16)

[Claims] 1. A gate electrode is buried in a groove provided in a semiconductor substrate via a gate insulating film, and a source region and a drain region are provided in the semiconductor substrate on both sides of the gate electrode so as to be shallower than the groove. A semiconductor device having a MIS transistor having a groove-type gate electrode structure, wherein the groove has an inverted trapezoidal cross-sectional shape, and at least a portion of the semiconductor substrate adjacent to a lower portion of a side wall on the drain region side of the groove. A diffusion layer having the same conductivity type as the drain region and having a lower impurity concentration than the drain region is provided integrally with the drain region. 2. The semiconductor device according to claim 1, wherein an angle formed between a main surface of said semiconductor substrate and a side wall of said groove is 89 to 75 degrees. 3. The semiconductor device according to claim 1, wherein an angle formed between a main surface of said semiconductor substrate and a side wall of said groove is 88 to 80 degrees. 4. An interlayer insulating film having an opening having the same shape as the uppermost portion of the groove at a portion corresponding to the groove, and provided so as to cover the source region and the drain region. 2. The semiconductor device according to 1. 5. The interlayer insulating film having a thickness of 100 to 300.
2. The semiconductor according to claim 1, wherein the depth of the source region and the drain region is 100 to 800 nm, and the difference between the depth of the source region and the drain region and the groove is 10 to 50 nm. apparatus. 6. The semiconductor device according to claim 1, wherein a ratio of a width of a bottom surface of the groove to a projection width of a side wall of the groove on a main surface of the semiconductor substrate is 2 ± 0.2: 1. Semiconductor device. 7. The semiconductor device according to claim 1, wherein a ratio of a width of a bottom surface of the groove to a projection width of a side wall of the groove on a main surface of the semiconductor substrate is 2 ± 0.1: 1. Semiconductor device. 8. The semiconductor device according to claim 1, wherein a width of a bottom surface of said groove is 10 to 50 nm. 9. A step of forming an element isolation region in a semiconductor substrate, a step of forming a semiconductor region serving as a source region and a drain region in an element region surrounded by the element isolation region, and a step of covering the semiconductor region. Forming an interlayer insulating film; forming an opening in a predetermined portion of the interlayer insulating film; forming a groove having an inverted trapezoidal cross-sectional shape reaching the semiconductor substrate in the opening portion; Forming a source region and a drain region by dividing the semiconductor region, forming a gate insulating film at least on the bottom surface of the trench, and ion-implanting impurities from a direction inclined with respect to the main surface of the semiconductor substrate. By implanting, at least a portion of the semiconductor substrate at a portion adjacent to a lower portion of the lower portion of the side wall of the trench on the drain region side has the same shape as the drain region. Forming a diffusion layer of one conductivity type with a lower impurity concentration than the drain region integrally with the drain region; and burying a gate electrode inside the groove via the gate insulating film. Semiconductor device manufacturing method. 10. The method according to claim 9, wherein the angle formed between the main surface of the semiconductor substrate and the side wall of the groove is 89 to 75 degrees. 11. The method according to claim 9, wherein the angle formed between the main surface of the semiconductor substrate and the side wall of the groove is 88 to 80 degrees. 12. The interlayer insulating film has a thickness of 100 to 30.
10. The semiconductor according to claim 9, wherein a depth of the source region and the drain region is 100 to 800 nm, and a depth difference between the source region and the drain region and the groove is 10 to 50 nm. Device manufacturing method. 13. A ratio of a width of a bottom surface of the groove to a projection width of a side wall of the groove onto a main surface of the semiconductor substrate is 2 ± 0.2: 1.
The method for manufacturing a semiconductor device according to claim 9, wherein: 14. A ratio of a width of a bottom surface of the groove to a width of projection of a side wall of the groove onto a main surface of the semiconductor substrate is 2 ± 0.1: 1.
The method for manufacturing a semiconductor device according to claim 9, wherein: 15. The method according to claim 9, wherein a width of a bottom surface of the groove is 10 to 50 nm. 16. A semiconductor device comprising:
10. The method of manufacturing a semiconductor device according to claim 9, wherein impurities are ion-implanted from a direction inclined by 84 degrees.