JP2002215080A - Voltage controller and image forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage controller which prevents impression of an excessive voltage by performing desired voltage control, and to provide an image forming device. SOLUTION: A CPU(central processing unit) 1 applies such a setting value that a D/A converter 2 outputs a voltage in which a control voltage is subtracted from the maximum allowable voltage to the D/A converter 2 as to the control voltage. Moreover, the maximum allowable voltage from a potentiometer 4 is inputted to the CPU 1 through an A/D converter 3 and at the same time it becomes the input of an analog subtracter 5 to act as a limiter. As a result, even though the CPU 1 runs away out of control and sets an abnormal setting value to the convert 2, a control voltage to be inputted to a power source circuit 11 never exceeds the maximum allowable voltage and the desired voltage control is performed in this voltage controller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage control device for outputting a control voltage. As an application, a cold cathode electron-emitting device is used as an electron beam source, and these electron-emitting devices are arranged in a matrix. This is applied to the image forming apparatus described above.

[0002]

2. Description of the Related Art FIG. 17 is a block diagram of a typical voltage control device. In FIG. 1, a control circuit 10 includes a CPU 1, which is a microcomputer as a processing means, a D / A converter 2, and an A / D converter 3.
Is configured. The control voltage output from the control circuit 10 is input to the power supply circuit 11 that supplies the output power supply voltage.

The CPU 1 sets a target voltage from outside by means (not shown), and outputs a command value to the D / A converter 2 to output a control voltage corresponding to the target voltage from the D / A converter 2.
/ A converter 2.

The control voltage output from the control circuit 10 is applied to a power supply circuit 11, and the corresponding output voltage is supplied as a power supply voltage to a target (not shown).
Also, the voltage monitor value linked to the output voltage is
1 and is input to the A / D converter 3.

[0005] The A / D converter 3 converts the voltage monitor value into a digital value and outputs the digital value to the CPU 1. CP
U1 performs feedback control so that the A / D result of the voltage monitor value becomes equal to the target voltage.

Here, in order to prevent application of an overvoltage to the target, there is also a method of providing a potentiometer 4 for setting a maximum allowable voltage as voltage defining means as shown in FIG.

[0007] The potentiometer 4 has a volume or the like inside and can set a desired voltage. The maximum allowable voltage set by potentiometer 4 is A /
The data is converted into digital data by the D
Input to PU1.

The CPU 1 performs feedback control so that the A / D result of the voltage monitor value becomes equal to the target voltage in a range where the target voltage does not exceed the maximum allowable voltage.

On the other hand, in FIG. 19, the control voltage and
In this method, a diode is inserted between the maximum allowable voltage and when the control voltage exceeds the maximum allowable voltage, the diode operates to prevent application of an overvoltage.

[0010]

However, in the case of the above-described prior art, the following problems have occurred.

In a normal operation state, the output voltage does not exceed the maximum allowable voltage. However, when the CPU 1 enters an abnormal state such as a runaway, an abnormal set value is output from the CPU 1 to D.
/ A converter 2 and cannot absolutely prevent application of overvoltage.

When a diode is provided as shown in FIG. 19, when a forward voltage of 0.6 V or more, which exceeds the maximum allowable voltage, is applied, the diode operates, and a control voltage higher than that is applied to the power supply circuit 11. Nothing, but 0.6V
The following overvoltages cannot be prevented. Further, the temperature characteristics of the forward voltage drop of the diode are poor, and the stability becomes a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a voltage control device and an image forming apparatus which perform desired voltage control and prevent application of overvoltage. Is to do.

[0014]

In order to achieve the above object, a voltage control apparatus according to the present invention is a voltage control apparatus for outputting a control voltage, comprising: a processing means for setting an instruction voltage; Voltage defining means for setting a voltage;
Analog operation means for generating a control voltage by subtracting an instruction voltage set by the processing means from the maximum allowable voltage output from the voltage defining means.

It is preferable that the processing means sets the command voltage by subtracting a target voltage from the input maximum allowable voltage.

A power supply unit for supplying a power supply voltage corresponding to the input control voltage as an output, and for outputting a voltage monitor value interlocked with the power supply voltage, wherein the processing unit receives the power supply voltage from the power supply unit; It is preferable that the command voltage is set so that the voltage monitor value and the target voltage are equal.

It is preferable that the maximum value of the command voltage is generally a value obtained by subtracting a minimum value of the control voltage corresponding to the target voltage from the maximum allowable voltage.

According to the image forming apparatus of the present invention, an image includes an electron-emitting device, a phosphor that emits light by electrons emitted from the electron-emitting device, and a driving unit that drives the electron-emitting device. A forming device, wherein a control unit for outputting a control voltage for giving a driving condition to the driving unit is provided, the control unit includes a processing unit for setting an instruction voltage, and a voltage defining unit for setting a maximum allowable voltage. Analog operation means for subtracting the instruction voltage set by the processing means from the maximum allowable voltage output from the voltage defining means to generate a control voltage.

A plurality of the electron-emitting devices are provided in a simple matrix wiring, and the driving means applies a driving voltage corresponding to a control voltage output by the control means to a wiring to which the selected electron-emitting elements are connected. Preferably, electrons are generated from the selected electron-emitting device.

A plurality of the electron-emitting devices are provided in a simple matrix wiring, and the driving unit applies a current to the selected electron-emitting device in accordance with a control voltage output from the control unit, and selects the selected electron-emitting device. It is preferable to generate electrons from the device.

An electron-emitting device, a phosphor that emits light by electrons emitted from the electron-emitting device, an anode electrode to which an anode voltage is applied, and that accelerates electrons emitted from the electron-emitting device to the phosphor; A power supply voltage applying unit for applying the anode voltage to the anode electrode, wherein the control unit outputs a control voltage for giving the application condition of the anode voltage to the power supply voltage applying unit. The control means includes processing means for setting an instruction voltage, voltage specifying means for setting a maximum allowable voltage, and an instruction voltage set by the processing means from the maximum allowable voltage output from the voltage specifying means. Analog operation means for generating the control voltage by subtraction.

It is preferable that the apparatus further comprises detecting means for detecting an average luminance level from the input image signal, and the control means changes the control voltage according to the average luminance level output from the detecting means.

It is preferable that the maximum value of the command voltage is substantially a value obtained by subtracting the control voltage such that an average luminance becomes a target value when the image signal is at a peak level from the maximum allowable voltage. It is.

[0024] Storage means for storing a set value for each of the arranged electron-emitting devices is provided, and the control means reads the set value of the selected electron-emitting device from the storage means and changes the control voltage. Is preferred.

It is preferable that the maximum value of the command voltage is generally a value obtained by subtracting the minimum value of the control voltage from the maximum allowable voltage.

[0026]

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, the dimensions of the components described in this embodiment,
The materials, shapes, relative arrangements, and the like are not intended to limit the scope of the present invention only to them unless otherwise specified.

(First Embodiment) A first embodiment will be described with reference to FIGS.

FIG. 1 is a block diagram for explaining a voltage control device according to the present invention. In the figure,
The control circuit 10 includes a CPU 1, which is a microcomputer as processing means, a D / A converter 2, an A / D converter 3, a potentiometer 4 as voltage specifying means, and an analog subtractor 5 as analog arithmetic means. It is configured. The control voltage output from the control circuit 10 is input to the power supply circuit 11 that supplies the output power supply voltage.

The analog subtractor 5 includes a potentiometer 4
Is obtained by subtracting the output of the D / A converter 2 from the maximum allowable voltage output by the power supply circuit 1 as a control voltage.
Output for 1

For this reason, the CPU 1 sets the control voltage set to output from the power supply circuit 11 the target voltage calculated by the information given from the outside or inputted from the outside, from the maximum allowable voltage to the control voltage. By giving the D / A converter 2 a set value that causes the D / A converter 2 to output a voltage obtained by subtracting the above, desired voltage control becomes possible.

Therefore, the maximum value of the output voltage of the D / A converter 2 is generally sufficient up to the value obtained by subtracting the minimum value of the control voltage from the maximum allowable voltage, so that the D having such an output range (dynamic range) is obtained. / A converter 2 is used. It should be noted that “approximately” means that the operation range required when setting the output range of the D / A converter 2 has some margin, and that there are generally several types of D / A converters. This is because it is difficult to obtain a material that matches the desired range.

The maximum permissible voltage from the potentiometer 4 is input to the CPU 1 through the A / D converter 3 and at the same time becomes the input to the analog subtractor 5 and functions as a limiter.

Therefore, even if CPU 1 runs away and sets an abnormal voltage to D / A converter 2,
Since the output voltage value of the A / A converter 2 is approximately within the output range of the maximum value obtained by subtracting the minimum value of the control voltage from the maximum allowable voltage and the minimum value of zero, the power supply circuit 11
Does not exceed the maximum allowable voltage. Therefore, desired voltage control can be performed.

In the present embodiment, the analog subtractor 5 is used. However, an analog operation means for inverting the output of the D / A converter 2 with an operational amplifier and adding the result to the maximum allowable voltage may be used. A negative voltage may be output from the A converter 2 and added by an analog adder as analog arithmetic means.

FIG. 2 is a block diagram showing an example in which the voltage control device according to the present embodiment is applied to ABL control in a drive circuit of an image display device as an image forming device.

In FIG. 1, an image display panel 101 using a surface conduction electron-emitting device is connected to an external electric circuit via terminals Dx1 to Dxm and terminals Dy1 to Dyn. Also, the anode terminal Da on the image display panel 101
Is connected to an external anode power supply and accelerates emitted electrons with the supplied anode voltage Va. The detailed configuration of the image display panel 101 will be described later.

The terminals Dx1 to Dxm are connected to the multi-electron beam source provided in the image display panel 101 described above.
That is, a scanning signal is applied to sequentially drive the surface conduction electron-emitting elements arranged in a matrix of M rows and N columns (simple matrix wiring) line by line. on the other hand,
To the terminals Dy1 to Dyn, a modulation signal for controlling an output electron beam of each element of the surface conduction electron-emitting device in one row selected by the scanning signal is applied.

Next, the scanning circuit 102 as a driving means will be described. The scanning circuit 102 includes m switching elements inside. Each switching element selects one of the selection voltage Vs and the non-selection voltage Vsn, and is electrically connected to the terminals Dx1 to Dxm of the image display panel 101. The selection voltage Vs and the non-selection voltage Vsn are supplied from an external power supply. Each switching element includes a timing signal generation circuit 104 (described later)
Operates based on a scan start signal and a scan clock output by the switch, but in practice, it can be easily configured by combining switching elements such as FETs.

In this embodiment, the selection voltage Vs is not scanned based on the characteristics of the surface conduction electron-emitting device illustrated in FIG. 3 (the electron emission threshold voltage is 8 [V]). The constant voltage of -7 [V] is set to be output so that the drive voltage applied to the element is equal to or lower than the electron emission threshold voltage, and the non-selection voltage Vsn is set to 0 [V] (ground level).
Set as

Next, the flow of an image signal will be described.
The decoder 103 converts the input composite image signal into 3
Primary color (RGB) luminance signal and horizontal and vertical synchronization signals (H
SYNC, VSYNC).

In the timing signal generation circuit 104, HS
Various timing signals such as a sampling clock, a scan start signal, a scan clock, and a pulse width clock are generated in synchronization with the YNC and VSYNC signals.

The RGB luminance signal is sampled by the sampling clock generated by the timing signal generating circuit 104 in the S / H circuit 105, and is supplied as a digital signal to an APL detecting circuit 106 as detecting means.

The APL detection circuit 106 converts the input luminance signal into a serial / parallel (S / P) conversion circuit 1 as it is.
07, the average luminance level in the vertical cycle is calculated based on the vertical synchronization signal (VSYNC) from the timing signal generation circuit 104 and the sampling clock.

Serial / parallel (S / P) conversion circuit 10
In 7, the luminance signal is converted into parallel signals arranged in the corresponding order of each phosphor of the image display panel 101.

Subsequently, the pulse width modulation circuit 108 generates a pulse having a pulse width corresponding to the image signal intensity.

In the voltage driving circuit 109 as a driving means, the pulse width clock output from the timing signal generation circuit 104 is used to control the modulation side supplied from the power supply circuit 11 only during the period of the pulse output from the pulse width modulation circuit 108. The drive voltage Vd is applied to the terminal Dy of the image display panel 101.
The voltage is applied to the surface conduction electron-emitting device in the image display panel 101 through 1 to Dyn.

The control circuit 10 as a control means is provided with a vertical synchronizing signal (VSY) generated by the timing signal generating circuit 104.
NC) and the average luminance level signal generated by the APL detection circuit 106, and controls the modulation-side drive voltage Vd.

FIG. 4 is a block diagram showing the inside of the control circuit 10. As shown in FIG. In the figure, reference numerals 1 to 5 are the same as those described in FIG. The potentiometer 4 manually adjusts the maximum voltage that can be applied according to the individual characteristics of the image display panel 101.

The selector 6 selects either the maximum allowable voltage from the potentiometer 4 or the voltage output from the analog subtractor 5 by a switching signal from the CPU 1 and outputs it as a control voltage.

Next, the operation of the CPU 1 will be described with reference to the flowchart shown in FIG.

Upon receiving the vertical synchronizing signal (VSYNC) output from the timing signal generating circuit 104, the interrupt processing starts.

In step S401, ABL setting is ON.
Check if it is in status. If it is OFF, in step S402, the selector 6 outputs an I / O output for selecting the maximum allowable voltage, and sets the control voltage to the maximum allowable voltage. On the other hand, if the setting of the ABL is ON, the process proceeds to step S403, and the average luminance level output from the APL detection circuit 106 is captured. Based on the value, step S
At 404, a target drive voltage is calculated.

FIG. 6 shows the relationship between the driving voltage of the image display panel 101 using the surface conduction electron-emitting device and the luminance of the image display panel in this embodiment.

The ABL controls the average luminance level of the entire surface so as not to exceed a target value, and the target value is set to, for example, 25% of the peak luminance.

In FIG. 6, V1 is a drive voltage at which a peak luminance is obtained, and V2 is a drive voltage at which a luminance of 25% of the target value is obtained. As the operation of the ABL, the image signal at the peak level is driven by the driving voltage of V2, and the driving is performed at the driving voltage of V1 when the average image signal is one-fourth or less of the peak. With respect to the image signal during that time, a desired luminance is obtained by calculating and driving an appropriate drive voltage using a polygonal line approximation, a function approximation, a conversion table, or the like according to the luminance characteristics.

On the other hand, in step S405, the maximum allowable voltage is fetched through the A / D converter 3. Then, in step S406, a voltage value to be set in the D / A converter 2 is obtained.

The target drive voltage calculated in step S404 is a voltage applied to the surface conduction electron-emitting device, and is supplied from the scanning circuit 102 to the terminals Dx1 to Dxm of the display panel 101.
And the modulation drive voltage Vd applied to the terminals Dy1 to Dxn of the image display panel 101 from the voltage drive circuit 109 are superimposed on each other, and are supplied to the voltage drive circuit 109. Modulation side drive voltage Vd
Is a voltage obtained by removing the amount of the selection voltage Vs from the target drive voltage calculated in step S404, and a control voltage to be applied to the power supply circuit 11 to give a drive condition is obtained.

Accordingly, the voltage value set in the D / A converter 2 is a voltage obtained by subtracting the control voltage from the maximum allowable voltage taken in step S405. The voltage is output to the D / A converter 2 in step S407.

Finally, in step S408, the selector 6
Outputs an I / O output that selects the analog subtractor 5, and uses the output of the analog subtractor 5 as the control voltage.

Steps S405 and S403, S
The order of 404 is not limited to this, and may be changed. Furthermore, since the ON / OFF setting of the ABL and the maximum allowable voltage setting do not dynamically change, they may be taken in as needed without being taken in every vertical cycle.

Here, the maximum value of the output voltage of the D / A converter 2 is set to be a difference between the maximum allowable voltage and V2 in FIG. 6 (ie, a value obtained by subtracting V2 from the maximum allowable voltage). Most desirable. If an optimum voltage value cannot be obtained, the voltage may be converted to an optimum voltage value using a resistor, an operational amplifier, or the like. Thereby, the resolution of the D / A converter 2 can be maximized, and highly accurate voltage control can be performed.

Therefore, as in the case of FIG. 1, the maximum allowable voltage from the potentiometer 4 is input to the CPU 1 through the A / D converter 3 and at the same time becomes the input to the analog subtractor 5 to act as a limiter.
Control voltage inputted to the power supply circuit 11 does not exceed the maximum allowable voltage even if the D / A converter 2 sets an abnormal voltage due to runaway.

In the image display panel 101 in which the voltage pulse signals are supplied to the terminals Dy1 to Dyn, only the surface conduction electron-emitting devices connected to the row selected by the scanning circuit 102 are used for a period corresponding to the supplied pulse width. The phosphor emits electrons and emits light. That is, during one horizontal scanning (1H) period,
All the elements on the selected row emit light in accordance with the image luminance signal. A two-dimensional image is formed by sequentially scanning the rows selected by the scanning circuit 102 from 1 to m.

In this embodiment, the S / H circuit 10
APL was detected at the output of 5, but was detected by an analog signal.
The data may be input to the CPU 1 through the A / D converter 2. Further, the D / A converter 2 and the A / D converter 3 may be those built in the CPU 1.

The above is the outline of the operation at the time of image formation.

Next, the configuration of the image display panel of the image display device of the present embodiment will be described with reference to a specific example. FIG. 7 is a perspective view of the image display panel used in the present embodiment, in which a part of the panel is cut away to show the internal structure.

In the figure, the rear plate 1015 and the side wall 10
16 and the face plate 1017 form an airtight container for maintaining the inside of the display panel at a vacuum. Further, since the inside of the hermetic container is maintained at a vacuum of about 10 −6 [Torr], the inside of the hermetic container is prevented from being destroyed due to an atmospheric pressure, an unexpected impact, or the like.
A spacer 1020 is provided as an atmospheric pressure resistant structure.

The rear plate 1015 has a substrate 1011
Are fixed, but N × M cold cathode elements 1012 are formed on the substrate 1011 (N and M are positive integers of 2 or more, and are appropriately set according to the target number of display pixels. For example, in a display device for displaying high-definition television, N = 3000 and M = 100
It is desirable to set the number to 0 or more. ).

The N × M cold cathode elements 1012 are arranged in a simple matrix by M row-directional wirings 1013 and N column-directional wirings 1014. That is, one terminal of the cold cathode element 1012 arranged in the same row is connected to the row wiring 1013, and the other terminal of the cold cathode element 1012 arranged in the same column is connected to the column wiring 1014.

Row direction wiring 1013 and column direction wiring 1014
An insulating layer (not shown) is formed between the electrodes at the intersections of the two to maintain electrical insulation.

As described above, the substrate 1011, the cold cathode element 1012, the row wiring 1013 and the column wiring 1014
Is called a multi-electron beam source.

The multi-electron beam source used in the image display apparatus of the present embodiment is a simple matrix wiring or ladder-shaped electron source in which the cold cathode elements 1012 are arranged. There are no restrictions. Therefore, for example, a surface conduction type emission element or FE
Or a cold cathode device such as an MIM type can be used.

In this embodiment, the substrate 1 of the multi-electron beam source is mounted on the rear plate 1015 of the airtight container.
However, when the substrate 1011 of the multi-electron beam source has a sufficient strength, the substrate 1011 of the multi-electron beam source itself may be used as the rear plate of the hermetic container.

On the lower surface of the face plate 1017, a fluorescent film 1018 is formed. Since this embodiment is a color display device, a CRT is
The phosphors of the three primary colors of red, green, and blue used in the field are separately applied. Note that when a monochrome display panel is formed, a single-color phosphor material may be used for the phosphor film 1018.

A metal back 1019 known in the field of CRT is provided on the surface of the fluorescent film 1018 on the rear plate side.
Is provided. The metal back 1019 is an anode electrode, and an anode voltage Va is supplied from an anode terminal Da.

Although not used in the present embodiment,
For the purpose of applying acceleration voltage and improving the conductivity of the fluorescent film,
Between the face plate 1017 and the fluorescent film 1018,
For example, a transparent electrode made of ITO may be provided.

The terminals Dx1 to Dxm and the terminal Dy1
Dyn and the anode terminal Da are electric connection terminals of an airtight structure provided for electrically connecting the image display panel 101 and the drive circuit.

The terminals Dx1 to Dxm are electrically connected to the row wiring 1013 of the multi-electron beam source, and
Dyn are electrically connected to the column wiring 1014 of the multi-electron beam source, and the anode terminal Da is electrically connected to the metal back 1019 of the face plate 1017.

In the image display apparatus using the image display panel described above, when a voltage is applied to each cold cathode element 1012 through the external terminals Dx1 to Dxm and Dy1 to Dyn, electrons are emitted from each cold cathode element 1012. . At the same time, the metal back 1019 has an anode terminal D outside the container.
a, a high voltage of several hundred [V] to several [kV] is applied to accelerate the emitted electrons, and the face plate 1
017. Thereby, the fluorescent film 101
Eight phosphors of each color are excited and emit light, and an image is displayed.

Normally, the voltage applied to the surface conduction electron-emitting device which is the cold cathode device 1012 is about 12 to 16 [V], and the distance between the metal back 1019 and the cold cathode device 1012 is 0.1.
The voltage is about 1 to 8 [mm], and the voltage between the metal back 1019 and the cold cathode element 1012 is about 0.1 to 10 [kV].

FIG. 8 is a block diagram showing an example in which ABL is performed by using the voltage control circuit shown in FIG. 1 for driving voltage control on the scanning circuit 102 side. In the figure, 101 to 109
And 10, 11 are equivalent to those described in FIG. The difference is that the power supply voltage supplied to the voltage driving circuit 109 is fixed at Vd, and the selection voltage Vs supplied to the scanning circuit 102 is controlled and supplied from the control circuit 10 and the power supply circuit 11.

Also in this configuration, the CPU 1 operates in the same manner as in FIG. 2 to obtain the same effect.

FIG. 9 is a block diagram showing another example in which the control circuit 10 shown in FIG. 1 is applied to ABL control in a driving circuit of an image display device. In FIG.
08 and 10 are equivalent to those described in FIG.

The difference is that a current driving circuit 110 is provided as a driving means instead of the voltage driving circuit 109. The current driving circuit 110 has a V / I converter, and the control voltage input from the control circuit 10 is used as a reference voltage. The set current value is V / I converted.

Then, according to the pulse width clock output from the timing signal generation circuit 104, the drive current obtained by the V / I conversion for the period of the pulse output from the pulse width modulation circuit 108 is converted to the terminals Dy1 to Dy1 of the display panel. It flows to the surface conduction electron-emitting device in the image display panel 101 through Dyn.

In the case of this configuration, the relationship between the drive current and the luminance of the image display panel 101 is known in advance. CPU1
Calculates the target drive current from the average image level, calculates the reference voltage of the current drive circuit 110, and sets the output voltage to the D / A converter 2.

(Second Embodiment) FIG. 10 is a block diagram for explaining a voltage control device according to a second embodiment. In the figure, 1 to 5 in the control circuit 20 are the same as those described in FIG. First
In the embodiment, the maximum allowable voltage is set by the A / D converter 3
In this embodiment, the voltage monitor value of the power supply circuit 11 is input to the CPU 1 through the A / D converter 3.
Is input to the CPU 1 through the.

The CPU 1 performs feedback control so that the A / D result of the voltage monitor value becomes equal to the target voltage.

The maximum allowable voltage is input to the analog subtractor 5 and functions as a limiter. Therefore, even if CP
Even if U1 runs away and abnormal voltage is set in D / A converter 2, the control voltage input to power supply circuit 11 does not exceed the maximum allowable voltage. Further, since the feedback control is performed using the voltage monitor value, more accurate voltage control is possible.

FIG. 11 is a block diagram showing an example in which the voltage control device according to the present embodiment is applied to ABL control in a drive circuit of an image display device. In the figure, 101 to 109 and 11 are the same as those described in FIG.

The difference is that the internal configuration of the control circuit 20 is the same as that described with reference to FIG. 10, and a voltage monitor value from the power supply circuit 11 is input. The input to the CPU 1 in FIG. 10 is a vertical synchronization signal (VSYNC) generated by the timing signal generation circuit 104, as in FIG.
And an average luminance level signal generated by the APL detection circuit 106.

Also in this configuration, the CPU 1 performs the same operation as in FIG. 2 to obtain the same effect.

FIG. 12 is a block diagram showing an example in which ABL is performed by using the voltage control circuit shown in FIG. 10 for controlling the anode voltage Va. In the figure, 101 to 109 and 20 are the same as those described in FIG.

The difference is that the power supply voltage supplied to the voltage drive circuit 109 is fixed at Vd, and the anode voltage Va supplied to the anode terminal Da is controlled by the control circuit 20 and the high voltage power supply circuit 21 serving as power supply voltage applying means. It is controlled and supplied from.

In the case of this configuration, the anode voltage Va is set in advance.
And the brightness of the image display panel 101. C
The PU 1 obtains a target anode voltage from the average image level as an application condition, calculates a control voltage to the high-voltage power supply circuit 21, and sets an output voltage to the D / A converter 2.

(Third Embodiment) FIG. 13 is a block diagram for explaining a voltage control device according to a third embodiment. In the figure, reference numerals 1 to 6 in the control circuit 30 are the same as those described in FIG. 1 and FIG. In the first embodiment, the D / A converter 2 outputs a command value D / A to output a control voltage corresponding to a target voltage set from the outside or a target voltage calculated based on information input from the outside. A converter 2
In the present embodiment, a target voltage or a set value to be given to the D / A converter 2 is obtained by referring to a look-up table (LUT) 7 based on information input from the outside.

The input to the CPU 1 may be address information of the LUT 7, or a clock and a reset signal of a counter (not shown) representing the address of the LUT 7.

When the target voltage is obtained, the CPU 1 compares the obtained target voltage with the power supply circuit 11 as in the first embodiment.
By giving a set value to output a voltage obtained by subtracting the control voltage from the maximum allowable voltage to the D / A converter 2,
The target voltage is obtained from the power supply circuit 11.

When a set value to be given to the D / A converter 2 is obtained from the LUT 7, the set value is given to the D / A converter 2 as it is, so that the voltage adjustment amount therefrom can be determined based on an arbitrary maximum allowable voltage. It is possible to control to a desired value.

Therefore, the maximum allowable voltage becomes an input to the analog subtractor 5 and operates as a limiter.
Even if U1 runs away and abnormal voltage is set in D / A converter 2, the control voltage input to power supply circuit 11 does not exceed the maximum allowable voltage.

FIG. 14 is a block diagram showing an example in which the voltage control device according to the present embodiment is applied to luminance correction in a drive circuit of an image display device. In the figure, 101 to 105, 1
Reference numerals 07 to 109 and 11 are equivalent to those described with reference to FIG.

The difference is that the internal configuration of the control circuit 30 is as described with reference to FIG. FIG.
The inputs to the CPU 1 at 1 are a vertical synchronization signal (VSYNC) and a horizontal synchronization signal (HSYNC) generated by the timing signal generation circuit 104.

The CPU 1 counts the input vertical synchronizing signal as a reset signal and the horizontal synchronizing signal as a clock signal, and generates an address of the LUT 7 as storage means. The LUT 7 holds a drive voltage adjustment amount corresponding to each scan line.

It is conceivable that the driving voltage for obtaining the desired luminance differs depending on the scanning line due to the influence of the structure of the image display panel and the manufacturing process. Further, there may be a case where it is desired to adjust the luminance depending on the display position. FIG. 15 (a),
(B) shows an example of the target drive voltage for each scanning line. In the figure, V1 is the maximum value of the target drive voltage, and V3 is the minimum value of the target drive voltage. To simplify the explanation,
The control voltage and the voltage supplied from the power supply circuit 11 have the same potential.

The potentiometer 4 in FIG. 13 is set so that the maximum allowable voltage is V1, and the maximum value of the output voltage of the D / A converter 2 is V1 and V3 in FIG.
It is desirable that the difference be Also, LUT7
Stores a set value of the D / A converter 2 corresponding to a voltage obtained by subtracting a target drive voltage for each scanning line from V1. As a result, the value read from the LUT 7 corresponding to each scanning line from the CPU 1 is directly used as the D / A converter 2
, The target drive voltage is supplied from the power supply circuit 11.

In the present embodiment, the LUT 7 holds the value corresponding to the voltage adjustment amount, but may hold the target drive voltage itself.
By performing the same processing as in steps 405 to S407, a target drive voltage can be obtained.

FIG. 16 is a block diagram showing an example in which luminance correction is performed using the voltage driving circuit shown in FIG. 13 for driving voltage control on the scanning circuit 102 side. In FIG.
Reference numerals 105, 107 to 109 and 11, 30 are the same as those described with reference to FIG.

The difference is that the power supply voltage supplied to the voltage driving circuit 109 is fixed at Vd, and the selection voltage Vs supplied to the scanning circuit 102 is controlled by the control circuit 30 and the power supply circuit 1.
This is a point controlled and supplied from 1.

Also in this configuration, CPU 1
By performing the same operation as in the case of, the same effect can be obtained.

[0110]

As described above, the present invention can control the voltage without exceeding the maximum allowable voltage even in an abnormal situation such as a runaway of the processing means.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a voltage control device according to a first embodiment.

FIG. 2 is a block diagram when the voltage control device according to the first embodiment is applied to an image display device.

FIG. 3 is a graph showing typical characteristics of a surface conduction electron-emitting device.

FIG. 4 is a block diagram illustrating a configuration example of a control circuit according to the first embodiment.

FIG. 5 is a flowchart illustrating an operation of a CPU according to the first embodiment.

FIG. 6 is a graph showing a driving voltage-emission luminance characteristic of the image display device.

FIG. 7 is a perspective view in which a part of an image display panel of the image display device used in the first embodiment is cut away.

FIG. 8 is another block diagram when the voltage control device according to the first embodiment is applied to an image display device.

FIG. 9 is another block diagram when the voltage control device according to the first embodiment is applied to an image display device.

FIG. 10 is a block diagram illustrating a voltage control device according to a second embodiment.

FIG. 11 is a block diagram when the voltage control device according to the second embodiment is applied to an image display device.

FIG. 12 is another block diagram when the voltage control device according to the second embodiment is applied to an image display device.

FIG. 13 is a block diagram showing a voltage control device according to a third embodiment.

FIG. 14 is a block diagram in a case where the voltage control device according to the third embodiment is applied to an image display device.

FIG. 15 is a graph showing a target drive voltage for each scanning line of the image display device.

FIG. 16 is another block diagram when the voltage control device according to the third embodiment is applied to an image display device.

FIG. 17 is a block diagram showing a conventional voltage control device.

FIG. 18 is a block diagram showing a conventional voltage control device.

FIG. 19 is a block diagram showing a conventional voltage control device.

[Explanation of symbols]

 Reference Signs List 1 CPU 2 D / A converter 3 A / D converter 4 Potentiometer 5 Analog subtractor 6 Selector 10, 20, 30 Control circuit 11 Power supply circuit 21 High voltage power supply circuit 101 Image display panel 102 Scanning circuit 103 Decoder 104 Timing signal generating circuit 105 S / H circuit 106 APL detection circuit 107 Serial / parallel conversion circuit 108 Pulse width modulation circuit 109 Voltage drive circuit 110 Current drive circuit 1011 Substrate 1012 Cold cathode device 1013 Row direction wiring 1014 Column direction wiring 1015 Rear plate 1016 Side wall 1017 Face plate 1018 Fluorescent film 1019 Metal back 1020 Spacer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G05F 1/10 G05F 1/10 L G09G 3/22 G09G 3/22 D

Claims (12)

[Claims] 1. A voltage control device for outputting a control voltage, comprising: processing means for setting an instruction voltage; voltage specifying means for setting a maximum allowable voltage; A voltage control device comprising: an analog operation unit configured to generate a control voltage by subtracting an instruction voltage set by the processing unit. 2. The voltage control apparatus according to claim 1, wherein said processing means sets the command voltage by subtracting a target voltage from the input maximum allowable voltage. 3. A power supply unit for supplying a power supply voltage according to the input control voltage as an output, and for outputting a voltage monitor value interlocked with the power supply voltage, wherein the processing unit is configured to output the power supply voltage from the power supply unit. 2. The voltage control device according to claim 1, wherein the command voltage is set such that the input voltage monitor value is equal to a target voltage. 4. The system according to claim 1, wherein the maximum value of the command voltage is substantially a value obtained by subtracting a minimum value of the control voltage corresponding to the target voltage from the maximum allowable voltage. 3. The voltage control device according to claim 1. 5. An image forming apparatus comprising: an electron-emitting device; a phosphor that emits light by electrons emitted from the electron-emitting device; and a driving unit that drives the electron-emitting device. Control means for outputting a control voltage for giving a driving condition to the control means, the control means comprising: a processing means for setting an instruction voltage; a voltage defining means for setting a maximum allowable voltage; An image forming apparatus comprising: an analog operation unit configured to generate a control voltage by subtracting an instruction voltage set by the processing unit from the maximum allowable voltage. 6. A plurality of said electron-emitting devices are provided in a simple matrix wiring, said driving means being a driving voltage corresponding to a control voltage outputted by said control means to a wiring to which said selected electron-emitting device is connected. 6. The image forming apparatus according to claim 5, wherein a voltage is applied to generate electrons from the selected electron-emitting devices. 7. A plurality of said electron-emitting devices are provided in a simple matrix wiring, and said driving means supplies a current corresponding to a control voltage outputted from said control means to said selected electron-emitting elements,
6. The image forming apparatus according to claim 5, wherein electrons are generated from the selected electron-emitting devices. 8. An electron-emitting device, a phosphor that emits light by electrons emitted from the electron-emitting device, and an anode electrode to which an anode voltage is applied to accelerate electrons emitted from the electron-emitting device to the phosphor. An image forming apparatus comprising: a power supply voltage applying unit that applies the anode voltage to the anode electrode; and a control that outputs a control voltage for applying the anode voltage application condition to the power supply voltage applying unit. Means, a control means for setting an instruction voltage, a voltage specifying means for setting a maximum allowable voltage, and an instruction set by the processing means from the maximum allowable voltage output from the voltage specifying means. An image forming apparatus comprising: an analog operation unit that generates a control voltage by subtracting a voltage. 9. A detecting means for detecting an average luminance level from an input image signal, wherein the control means changes the control voltage according to the average luminance level output from the detecting means. The image forming apparatus according to claim 5. 10. The maximum value of the instruction voltage is generally a value obtained by subtracting the control voltage such that an average luminance becomes a target value when the image signal is at a peak level from the maximum allowable voltage. The image forming apparatus according to claim 9, wherein: 11. A storage unit for storing a set value of each of the arranged electron-emitting devices, wherein the control unit reads the set value of the selected electron-emitting device from the storage unit and changes the control voltage. The image forming apparatus according to any one of claims 5 to 8, wherein: 12. The image forming apparatus according to claim 11, wherein the maximum value of the command voltage is substantially a value obtained by subtracting a minimum value of the control voltage from the maximum allowable voltage.