JP2002208945A - Destination information managing apparatus for packet - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a destination information managing apparatus for packet capable of keeping more prefixes than those of a CAM, and retrieving prefixes more rapidly than a RAM. SOLUTION: The apparatus for managing the destination information of the packets for selecting the paths of the packets is provided with a first memory, a second memory having a retrieval speed lower than the first memory and the degree of integration higher than the first memory, and a compiling section for compiling a path table storing the destination information so that the information is over the first and second memories.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a packet destination information management device, and more particularly to a device for managing an Internet Protocol (IP) address used in the Internet or an intranet.

[0002]

2. Description of the Related Art The Internet and intranets are
This is a communication method using CP / IP, which is a simple communication method between computers, from a local area network (LAN) to a wide area network (WAN).
Widely used until. In IP, all information is transferred in packets. The packet has a variable length size of about several tens of bytes to several tens of kilobytes. A header including a destination address (destination address), a source address (source address) and the like is attached to the packet.

[0003] The Internet is generally constructed by interconnecting communication devices called routers.
The router selects a route of the packet based on the destination information of the packet (routing: also referred to as forwarding). That is, when the router receives a packet, the router stores the next hop address (IP address of the router that should receive the packet next) corresponding to the destination IP address stored in the header of the received packet in the routing table (also referred to as “forwarding table”). ). Upon acquiring the next hop address, the router transfers the packet to the router having the next hop address. The routing table stores the IP address (called “prefix”) of the network (called “prefix”) of the destination network of the packet, and the next hop address corresponding to the prefix.

When dynamic routing is adopted, a router exchanges routing information (prefix and the like) with another router in accordance with a routing protocol and creates a routing table. The routing table is updated every few minutes to several hours by performing the above-described routing information exchange periodically and periodically. Routing protocols include, for example,
OSPF (Open Shortest Path First), RIP (Routing
Information Protocol), BGP (Border Gateway Proto
col) etc.

[0005] Routing is performed for each packet arriving at the router. For this reason, the routing performance is a major factor that determines the performance of the router. Routers used by Internet service providers (ISPs) require a routing table that can search for the next hop address corresponding to about 250,000 IP addresses. Techniques for searching for such a large amount of information at high speed and for efficiently storing the information have been conventionally studied.

The method of constructing the routing table is generally a method of using a dedicated memory such as a CAM (Contents Accessable Memory: referred to as “associative memory”).
(Called “CAM method”) and RAM (Rundam Access Mem
ory) (referred to as a “RAM tree method”).

The IP address is a network address
(Prefix) and host address. The effective prefix length (effective length) changes depending on the network configuration and the aggregation of address information (aggregation).
Specifically, in general, a network is a core
(Relay), edges, and the like, and the functions to be held by the routers and the fineness of the routing information (fineness of address aggregation) differ for each router. For example, in the case where the network is configured as shown in FIG.
All address length of P address (32 bits) is prefix
Used as (/ 32). On the other hand, in the access network, the upper 24 bits (/ 24) of the IP address are used as a prefix for routing. Further, in the core network, at the time of routing, the upper 16 bits (/ 16) of the IP address are used as a prefix.

[0008] As described above, the prefix used for routing becomes shorter toward the center of the network. In accordance with this, a router (edge router) connecting the LAN and the access network performs routing using all bytes or the upper 24 bytes of the IP address. Further, a router (core router) connecting the access network and the core network performs routing using the upper 24 bytes or the upper 16 bytes of the IP address.

However, actually, CIDR (Classless Int)
er-Domain Routing), calculation of route aggregation based on the routing information received by each router is performed. For this reason, the prefix length is not fixed, but a different prefix length is used for each IP address of the domain. The CIDR network address is represented by an IP address (corresponding to a prefix) and a mask value. The mask is a valid bit of the network address, and is expressed by a variable continuous bit string from the leftmost end (most significant bit) of the address.

[0010] Incidentally, the effective length is not specified in the packet input to the router. Therefore, the router
When searching for a prefix corresponding to the IP address of the packet destination, a longest match (longest matc
h) Perform a special search procedure called a search. The longest match search is a method of searching a routing table for an entry of a prefix whose bit string from the leftmost end (the highest order) matches the longest among the bit strings constituting the prefix in the destination IP address.

The CAM is a special memory that outputs the address of the entry corresponding to the key using the contents stored as the entry as a key. If the CAM method is used, the prefix corresponding to the destination IP address is
The search can be performed faster than in the AM tree method.

In the RAM tree method, prefix entries are arranged in a tree on the RAM, and each bit of the destination IP address is compared bit by bit from the most significant bit to the least significant bit to correspond to each other. The prefix entry is searched. FIG. 13 is an explanatory diagram of a search method based on the RAM tree method. In FIG.
A logical configuration of a Patricia tree is shown as one of the tree configuration methods.

In the Patricia tree, as entry data, a prefix value, a mask value (effective length), a 0 pointer
(Zero pointer), 1 pointer (one pointer), and routing information (next hop address) are set in the RAM (see FIG. 14). The Patricia tree is composed of a plurality of nodes N and links L provided according to the entry data. Each node N has the prefix value and the effective length described above, and further, a bit to be processed by the node N
It has a pointer P1 and a pointer P2 corresponding to (0 or 1). When there is a node N corresponding to the jump destination of the pointer P1 or the pointer P2, the nodes N are connected by a link L.

FIG. 13 shows “000xxxxx (0/3)”, “001xxx”
xx (32/3) "," 010xxxxx (64/3) "," 011000xx (96/6) ",
“01100011 (99/8)”, “011001xx (100/6)”, “01101xxx
(104/5) "," 0111xxxx (112/4) "," 100xxxxx (128/3) ",
“101xxxxx (160/3)”, “110xxxxx (192/3)”, and “111x
A Patricia tree corresponding to each entry data of xxxx (224/3) "is shown. Here, as an example, the maximum effective length of the prefix is set to 8 bits.

"X" in the entry data indicates an invalid bit in the prefix. The number on the left side in parentheses indicates the prefix value, and “x” in the entry data is “0”.
Is a value obtained by converting a binary value into a decimal number when. The number on the right side indicates the effective length. For example, entry data “001xxxxx” is prefix “3”.
2 ", and the effective length is 3 bits.

If the prefix of the destination IP address of the packet is “01100010 (98)” as shown in FIG. 13, the first node N (the leftmost node N in FIG. 13) It is determined whether the bit (most significant bit) is 0 or 1. At this time, since the bit is “0”, the next node according to the pointer P1 (the prefix value is “0”)
Then, the process proceeds to the node N having an effective length of 1 (node N of (0/1)), and it is determined whether the next bit is 0 or 1. Such processing is repeated until there is no longer any link destination specified by the pointer P1 or P2 (see the bold arrow in FIG. 13). Thereafter, when the link destination is lost at a certain node N, a prefix (destination network address) corresponding to the destination IP address is specified. Then, the next hop address corresponding to the specified prefix is extracted from the routing table as information on the output route.

On the actual RAM, the Patricia tree is stored in a tree table as shown in FIG.
For example, using the tree table shown in FIG.
When searching for the prefix “0”, the following processing is performed: In the first entry, the 0 pointer is checked based on the most significant bit “0”, and the jump to the entry indicated by the 0 pointer is performed. In the next entry, one pointer is checked based on the next bit "1", and the process jumps to the next entry indicated by the one pointer (S102). The 0 pointer is checked based on the bit “0.” At this time, an end flag indicating that there is no jump destination is stored in the 0 pointer instead of the jump destination address, and is stored in the entry. The output route information (next hop address) that has been set is read from the tree table (S103).

[0018]

In the RAM tree method, a processor (CPU, MPU, etc.) executes RA processing for each bit constituting a prefix by executing software.
The tree tables on M are read one after another. For this reason, the processor read count (memory access count)
Is proportional to the effective length. In the case of an IP address (up to 32 bits), the average value of the effective length is about 20 bits. For this reason, about 20 memory accesses are required. In view of this, for example, one RAM access takes 30 nanoseconds.
Even if a RAM that can be executed in about [ns] is used, an average of 600 [ns] is required until the search is completed, and about 1 microsecond [μs] if the search is slow. Therefore, in the RAM tree method, the packet transfer performance is set to 1 Mbps [mega packet per
[second] could only be raised.

The RAM is highly integrated, and the Patricia tree can store prefix entries relatively efficiently. For this reason, even when the RAM tree method is adopted in the ISP router, necessary entries can be stored in the routing table. Due to the development of semiconductor technology, a processor that implements a hardware procedure for searching routing information from a tree table
(Called "Layer 3 switches").

However, the tree system has a problem that the search speed is lower than that of the CAM system. Specifically, the CAM system can transfer packets at several tens of megapps, whereas the RAM tree system can transfer about 1 megappp.
s. However, the degree of integration of the CAM is lower than that of the RAM, and only about several kilo entries are currently realized.

As described above, the number of entries to be stored in the routing table is increasing with the expansion of the Internet. It is also desired to improve the packet transfer speed. For this reason, it is desired to realize a routing table having a large capacity of several hundred kilo entries and a high-speed search of several tens of megapps.

An object of the present invention is to retain more prefixes than a routing table created by the CAM system and to search for prefixes faster than a routing table created by the RAM tree system. Is to provide a destination information management device for packets that can perform the above.

[0023]

The present invention employs the following configuration to achieve the above object.

That is, the present invention is an apparatus for managing destination information of a packet for selecting a path of the packet,
A first memory, a second memory having a lower information retrieval speed and a higher degree of integration than the first memory, and the destination information is stored in a state of straddling the first memory and the second memory. A creation unit that creates a routing table.

According to the present invention, a part of the destination information is stored in the first memory, which has a higher search speed than the second memory, so that the stored destination information is searched using only the second memory. The destination information can be searched quickly.
Further, since the second memory has a higher degree of integration than the first memory, it can store more destination information than when only the first memory is used.

The first memory is, for example, a CAM (associative memory)
And the second memory is, for example, a RAM. The destination information is, for example, the IP network address of the destination of the packet.
(Prefix) or a combination of a VPN identifier and an IP network address.

[0027] The present invention may further comprise a threshold storage unit which stores a threshold value of the usage rate of the first memory, wherein the creating unit obtains the usage rate of the first memory, and the obtained usage rate is stored in the threshold storage unit. When the number is less than the threshold value stored in the section, it is preferable that destination information to be stored in the routing table is stored only in the first memory.

According to the present invention, there is provided a routing table in which destination information of a packet is stored in a state of straddling a first memory and a second memory having a lower information retrieval speed and a higher degree of integration than the first memory. And a search unit for searching the routing table for destination information corresponding to the input packet and acquiring information on an output route corresponding to the searched destination information.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to the configuration of the embodiment.

[First Embodiment] <Configuration of Router> FIG. 1 is a diagram showing a configuration example of a router 1 as a communication device to which a destination information management device and a route selection device according to the present invention are applied. The router 1 is roughly divided into a plurality of interface cards 2 that execute processes related to a physical layer (layer 1) and a data link layer (layer 2).
And a routing mechanism 3 for performing processing relating to packet routing (network layer: layer 3). The interface card 2 is provided for each packet output route (input route).

The routing mechanism 3 includes a routing protocol processing unit 4, a route calculation / route table creation unit 5 (hereinafter, referred to as a "route table creation unit 5"), a routing table (route table) 20, and a header extraction unit. 8, an address search unit 9, and a transfer processing unit 10. Note that the routing mechanism 3 corresponds to the management device and the route selection device of the present invention, the routing table creating unit 5 corresponds to the creating unit of the present invention, and the address searching unit 9 corresponds to the searching unit of the present invention.

The routing protocol processing unit 4
A routing information exchange process is executed in accordance with a predetermined routing protocol such as P, OSPF, BGP, etc., and routing information (prefix or the like) is obtained from another router, and the obtained prefix is given to the routing table creating unit 5.

The routing table creation unit 5 calculates an optimal output route corresponding to the prefix received from the routing protocol processing unit 4, and stores the prefix and information (next hop address) of the calculated output route. Create a routing table 20 (the threshold storage unit of the present invention,
(Corresponds to an allowable time storage unit and an access count storage unit).

The routing table 20 includes a CAM 6 as a first memory and a RAM 7 as a second memory. The CAM 6 and the RAM 7 include a routing table creation unit 5
Holds the entry for the prefix and the next hop address stored by. In the present embodiment, an example is described in which a prefix is obtained by dynamic routing. However, the present invention is also applicable to a router having a routing table created by static routing.

The header extraction unit 8 extracts the header of the packet input from each interface card 2 to the routing mechanism 3, and extracts the destination IP address from the extracted header.
(Destination IP address) and gives it to the address search unit 9.

The address search unit 9 reads out the next hop address corresponding to the prefix of the destination IP address received from the header extraction unit 8 from the routing table 20 and supplies it to the transfer processing unit 10.

The transfer processing unit 10 receives the packet input to the routing mechanism 3 from the interface card 2 corresponding to the next hop address received from the address search unit 9.
To enter.

The interface card 2 performs a process (for example, rewriting a destination MAC address) on layers 1 and 2 for the packet input from the routing mechanism 3. After that, the interface card 2
Forward the packet to another router corresponding to the next hop address.

The routing protocol processing unit 4,
Routing table creation unit 5, header extraction unit 8, address search unit 9
Is a function realized by a processor (not shown) such as a CPU executing a program. The transfer processing unit 9 is configured using, for example, a switch realized by software or hardware.

<Configuration of CAM> Next, the CAM 6 will be described. The CAM is a special memory that outputs an address of an entry that matches a given pattern. C in which only "0" or "1" can be set as a comparison pattern
The AM is called “bimary CAM”, and the CAM in which three patterns “0”, “1” and “dc (mask)” can be set as a comparison pattern is called “ternary CAM”.

FIG. 2 is a diagram showing a configuration example of the CAM 6. The CAM 6 includes a data array and a mask array 12 in which special memory elements each having a comparator for each bit are arranged on a plurality of arrays, and a priority encoder (p) for performing longest match search and priority control of addresses.
A riority encoder 13 and an input / output control device (I / O: not shown) for inputting / outputting write data and the like are provided.

As a premise of the longest match search, a combination of a prefix as write data and mask information is transmitted through the I / O to the data array / mask array 12.
Is written as an entry. When a destination IP address as a comparison target (output route search target) is input to the CAM 6 via I / O, the destination IP address and each entry of the data array / mask array 12 are compared, and the comparison target destination IP The address (CAM address) of the entry holding the prefix that matches the address is detected.

When a plurality of CAM addresses are detected, the priority encoder 13 specifies a CAM address that has the longest match with the destination IP address (has the longest effective length) or a CAM address to be given priority, and specifies The output CAM address is output.

An example of a prefix search using the CAM 6 as a ternary CAM will be described with reference to FIG. Now, CAM
As shown in FIG. 2, combinations of a plurality of prefixes and mask information are written as entries in the data array / mask array 12 of FIG. In this example, the prefixes held in the entries are sorted in the order of the effective length.

Here, for example, the destination IP of a certain packet
The address “192.168.0.177” is CAM11
Is entered. Then, the destination IP address “19”
2.168.0.177 "is compared with each entry (combination of prefix and mask information) held in the data array / mask array 12, and a signal indicating a CAM address that matches both is given a priority. Input to the encoder 13. In the example shown in FIG.
Addresses “1”, “1003”, “1007” and “6”
5535 "is input to the priority encoder 13.

The priority encoder 13 selects a signal indicating the CAM address “1” having the smallest address value among the input signals, and inputs the CAM address “1” to the auxiliary RAM 14. As a result, “192.168.0.177” held at the CAM address “1” is obtained.
/ 32 "is specified as a prefix corresponding to the destination IP address input to CAM6.

The auxiliary RAM 14 holds the next hop address corresponding to the CAM address, and when the CAM address "1" is input, outputs the next hop address corresponding to the input CAM address. The output next hop address is provided to the address search unit 9. Then, the next hop address is given to the transfer processing unit 10,
The transfer processing unit 10 gives the packet to the interface card 2 corresponding to the next hop address. The interface card 2 transfers the received packet to the next hop.

CAM6 has a destination IP address of CAM1.
The signal indicating the CAM address is input to the auxiliary R
The operation until the data is stored in the AM 14 (long guest match search for the destination IP address) can be performed at a time. At present, CAM is 50 to 100 million searches / sec (=
A high-speed search can be performed at a speed of 10 to 20 ns / search). However, the degree of integration of the CAM 6 is several Mbits because of the above-described comparison function, and is reduced to a fraction of that of the RAM.

<Arrangement of RAM> In the RAM 7, a Patricia tree (tree table) as shown in FIG. 13 is created. That is, the RAM 7 stores a prefix, a mask length,
The tree table stores the 0 pointer, the 1 pointer, and the next hop address as entries (see FIG. 14). The structures themselves of the RAM tree and the tree table are the same as those shown in FIGS. The routing table creation unit 5 adds a new prefix and an entry including the next hop address corresponding to the prefix to the Patricia tree (tree table). In this case, the routing table creation unit 5 adds an entry according to any of the four patterns shown in FIG. The four patterns are
It is as follows. (A) 1st pattern: When matching with existing node (B) 2nd pattern: When adding to existing node as child node (C) 3rd pattern: When adding in the middle of existing node (D) 4th pattern In the case of adding from an existing node together with a branch tree node, in the first pattern, an entry is added to a node (node N1 in FIG. 3A) already existing on the tree. In the second pattern, the entry is added as a child node (node N3 in FIG. 3B) of a node (node N2 in FIG. 3B) already existing on the tree. In the third pattern, the entry is composed of a certain parent node (node N4 in FIG. 3C) and a child node.
(The node N5 in FIG. 3C).
As a node N6).

In the fourth pattern, the entry is a tree node (FIG. 3 (D)) between a certain parent node (node N7 in FIG. 3 (D)) and a child node (node N8 in FIG. 3 (D)). ) Node N9)
And a child node of the branch tree node (node N in FIG. 3D).
10). When an entry is added,
The routing table creation unit 5 correctly replaces the pointers (0 pointer and / or 1 pointer) of the node related to the added entry (node). This modifies the RAM tree.

<Address Search Using Routing Table> Next, a process in which the address search unit 9 searches for a next hop address using the routing table 20 will be described. FIG.
FIG. 3 is a configuration diagram of a routing table 20 in the embodiment. In FIG. 4, CAM 6 is configured using ternary CAM. RAM7 is Patricia Tree
(RAM tree) 17 (a tree table thereof) is stored.

In this embodiment, the prefix corresponding to the destination IP address is stored in the routing table 20 in one of the following three patterns. (A) Stored as an entry in the CAM 6 (B) Stored as an entry in the RAM tree 17 (C) Stored (across) the CAM 6 and the RAM tree 17 In the pattern (C) described above, the prefix has a predetermined number of valid bits. In the prefix, from the leftmost bit (most significant bit) to a predetermined bit (first
Is set in the CAM 16, and an entry for searching (the second part) from the predetermined bit to the last bit (least significant bit) is RA
It is set in the M-tree 17.

For example, when the prefix “0000xxxx” (prefix value 0 / effective length 4) is set in the routing table 20 in the pattern (C), the CAM 6 and the RAM tree 17 have the following configurations. That is, CAM
No. 0 (0xxxx)
xxx) / 1 "is provided.
The tree 17 is provided with a node N11 holding an entry of “0/1”.

Address of entry E1 (CAM address)
Are linked to the RAM address of the node N11. Thereby, the address search unit 9 (see FIG. 1)
The node N11 can be accessed using the address of the entry E1 output from the AM 16.

That is, when the prefix is set in the pattern (C), the RAM address (address of the entry (node) of the RAM tree) corresponding to the CAM address
Are stored in the auxiliary RAM 14 (see FIG. 2) instead of the next hop address corresponding to the CAM address. The node N11 is a node N1 holding an entry of “0/2”.
2 is linked to the node N1 via the 0 pointer.
2 is linked via a 0 pointer to a node N13 holding an entry of “0/3”.

For example, the prefix “0110000x”
For (prefix value 96 / effective length 7), the CAM 6 and the RAM tree 17 have the following configuration. That is, CAM
The data array / mask array 12 of “6” contains “96 (011
00xxx) / 5 "entry is provided.
The RAM tree 17 is provided with a node N21 holding an entry of “96/5”.

The CAM address of the entry E2 is linked to the RAM address of the node N21 via the auxiliary RAM 14, and the address search unit 9 accesses the node N21 using the CAM address of the entry E2 output from the CAM 16. be able to. Node N21
It is linked via a 0 pointer to the node N22 holding the entry of "96/6".

When receiving the destination IP address from the header extracting unit 8, the address searching unit 9 executes the following routing processing. That is, the address search unit 9 inputs the destination IP address to the CAM 6. Here, if the input destination IP address is, for example, “01100000”,
The CAM 6 outputs the CAM address of the entry E2 of “96/5” in which each bit value from the most significant bit of the prefix matches the longest by the longest match search. The output CAM address is input to the auxiliary RAM 14. Then, the RAM address (address of the node N21) corresponding to the CAM address of the entry E2 is given from the auxiliary RAM 14 to the address search unit 9.

When receiving the RAM address from the auxiliary RAM 14, the address search unit 9 accesses the node N21 of the RAM tree 17 using the received RAM address. Next, the address search unit 9 accesses the node N22 specified by the 0 pointer of the node N21.

The address search unit 9 sets 0 at the node N22.
Refers to a pointer. The 0 pointer stores an end flag indicating that there is no link destination instead of the designated link destination. Therefore, the address search unit 9 determines that the destination I
The prefix corresponding to the P address is “011000xx (96
/ 6) ”, the prefix“ 96/6 ”
Is read from the RAM 7.
In this way, the prefix corresponding to the destination IP address is specified, and the output route (next hop) is determined.

According to the above-described routing processing, the CAM 16 searches all the prefixes corresponding to the destination IP address from the most significant bit to the fifth bit at a time. Thereafter, the processing for the sixth and seventh bits of the prefix is performed using the RAM tree 17, and the prefix of the destination IP address is specified.

In the above-described routing processing, if processing from the most significant bit to the fifth bit is performed using only the RAM tree 17, five RAM accesses are required. On the other hand, the above-mentioned routing process is performed in the CAM
, The search time is reduced.

When a prefix having an effective length of 7 bits is searched using only the RAM tree 17, seven RAM accesses are required. In contrast,
In the above routing process, the number of RAM accesses can be reduced to two. Therefore, the time required for the search is
This is shortened compared to a case where a prefix is searched using only the tree 17. On the other hand, if the prefix entry is
It is set in the RAM tree 17 according to the pattern (B) described above. Therefore, the number of entries set in the CAM 6 can be reduced.

Therefore, the above-described routing table 2
According to 0, more entries can be stored than when the routing table is configured using only the CAM. On the other hand, according to the routing table 20,
The time required for routing for one packet is
The routing table can be shorter than the case where the routing table is configured using only the RAM tree, and the routing performance can be improved.

<Addition of Entry> The topology of the network changes due to network restructuring, network maintenance / inspection, link or node failure, and the like. When the topology changes, the optimal route from the router 1 to a certain network changes. The router 1 updates the routing table 20 periodically or periodically to respond to a change in topology. That is, the routing protocol processing unit 4 of the router 1 periodically or periodically exchanges routing information according to the routing protocol, extracts a prefix from the routing information acquired from another router, and provides the routing table creation unit 5 with the prefix. . When a new prefix is received from the routing protocol processing unit 4, the routing table creation unit 5 calculates an optimal output route for transferring the packet to the received prefix, and based on the calculation result, the next hop. To determine.

Then, the routing table creating unit 5 stores the received prefix as an entry in the routing table 20, and associates the stored new entry with the determined next hop address. As a result, the address search unit 9 can obtain the corresponding next hop address for the packet having the destination IP address corresponding to the new entry.

FIGS. 5 and 6 are flowcharts showing the process of adding an entry by the routing table creation unit 5. FIG. In FIG. 5, the administrator of the router 1 stores the threshold ηc (max) of the usage rate of the CAM 6 and the threshold ηr (max) of the usage rate of the RAM 7 in a memory (not shown) of the routing table creation unit 5 ( Step S
1).

The utilization rate ηc of the CAM 6 is obtained by dividing the number of entries stored in (the data array / mask array 12 of) the CAM 6 by the total number of entries that can be stored in the CAM 6 (CA
M6 entry utilization rate). On the other hand, the usage rate ηr of the RAM 7 is a value obtained by dividing the number of entries stored in the RAM 7 as nodes constituting the RAM tree 17 by the total number of entries that can be stored in the RAM 7 (entry usage rate of the RAM 7).

Next, the administrator of the router 1 determines the permissible time Tmax for one routing, the access time τr to the RAM 7, and the maximum number of accesses δmax = Tmax / τr to the RAM 7 in one routing, Routing table creation unit 5
(Step S2). The processing in steps S1 and S2 may be automatically performed by the router 1.

Thereafter, the processing after step S3 is started when the routing table creator 5 receives the prefix from the routing protocol processor 4. When receiving one or more prefixes from the routing protocol processing unit 4 (step S3; Yes), the routing table creation unit 5 determines whether a new prefix to be added to the routing table 20 is included in the received prefix. (Step S4), and if not included, the process returns to step S3; otherwise, the process proceeds to step S5.

In step S5, the routing table creator 5 sets a new prefix to be added (a newly obtained prefix) to "N" and sets the effective length of the prefix "N" to "n". Set to. Subsequently, the routing table creating unit 5 searches the routing table 20 using the prefix “N”, and among the prefixes stored as entries in the routing table 20, the longest match with the prefix “N” is performed. The prefix “M” and the effective length “m” of the prefix “M” are obtained (step S6). next,
The effective length “m” is subtracted from the effective length “n” to obtain the effective length difference δ (step S7).

Next, as shown in FIG. 6, the routing table creation unit 5 measures the utilization ηc of the CAM 6 and
Then, the utilization factor ηr of Step 7 is measured (Step S8). Next, the routing table creation unit 5 determines whether there is a sufficient free area in the CAM 6 (Step S9). That is, the routing table creation unit 5
It is determined whether the utilization rate ηc of the CAM 6 satisfies the condition “ηc <ηc (max)”.

At this time, if the condition is satisfied (step S9; Yes), the routing table creation unit 5 adds (stores) an entry with the prefix “N” to the CAM 6 (step S10).

As described above, the value of the utilization factor ηc is equal to the threshold value ηc (ma
x), the CAM 6 utilization rate ηc is low,
Assuming that the CAM 6 has a sufficient free area, the entry of the prefix “N” is stored only in the CAM 6. As a result, the routing time can be reduced. On the other hand, if the condition is not satisfied, the process proceeds to step S11.

At step S11, the routing table creation unit 5
It is determined whether or not the RAM 7 has a sufficient free area. That is, the routing table creation unit 5 determines whether or not the utilization rate ηr of the RAM 7 satisfies the condition “ηr <ηr (max)”.

At this time, if the condition is not satisfied (step S11; No), the router 1 outputs an error as an entry having the prefix “N” cannot be registered in the routing table 20 (step S12).
On the other hand, when the condition is satisfied (step S11;
If Yes, the process proceeds to step S13.

At step S13, the routing table creation unit 5
When the RAM tree corresponding to the difference δ is created, whether or not the number of accesses to the created RAM tree (the number of stages of the additional tree) is less than the maximum access number δmax of the RAM 7
(Whether it is within the allowable range).

That is, the routing table creation unit 5 determines whether or not the difference δ satisfies the condition “δmax> δ”. At this time, when the difference δ satisfies the condition (step S13; Yes), the routing table creation unit 5 registers a node (entry) of each bit corresponding to the difference δ in the RAM 7 (step S15).

Here, the routing table 20 contains
The prefix “M” has already been stored. At this time, if the prefix “M” is stored only in the CAM 6, the node on the most root side (upstream side) and the node of each bit corresponding to the difference δ are stored in the CAM 6. The entry of the prefix “M” is connected by a link by the above method.

On the other hand, when the least significant bit of the valid bit of the prefix “M” is stored as a node in the RAM 7, the node of each bit corresponding to the difference δ is linked to the subsequent stage of the node. Being placed.

As a result, of the valid bits of the prefix "N", the bits from the most significant bit to the predetermined bit (first part) are stored in the CAM 6, and the bits from the predetermined bit to the least significant bit (second part) are stored. It is stored in the RAM tree 17. That is, the prefix “N” routes CAM6
It is stored in the tree as (root). This allows CA
The overflow of M6 is prevented.

If the prefix corresponding to the prefix "M" is not stored in the routing table 20, the prefix "N" is stored only in the RAM 7 in step S15. If the CAM 6 has an entry of “0/0”, all prefixes stored in the routing table 20 are CAM 6
6 and the RAM tree 17.

When the difference δ does not satisfy the condition (step S13; No), the routing table creator 5 rewrites the entry of the CAM 6 (step S14). That is, the routing table creation unit 5 deletes one of the CAM entries stored in the CAM 6. Subsequently, the routing table creation unit 5 stores the prefix “N” as an entry in the CAM 6.
Alternatively, the routing table creator 5 stores the prefix “N” from the most significant bit to a predetermined bit in the CAM 6 and stores the node (entry) corresponding to the predetermined bit to the least significant bit in the RAM 7 ( to add.

According to the above processing, the number of stages of the RAM tree 17 for the prefix “N” is reduced. Therefore, the number of accesses to the RAM 7 by the address search unit 9 decreases. Therefore, the address search unit 9 sets the prefix “N”
The time required to acquire the next hop address corresponding to the destination IP address as the next hop address corresponding to the destination IP address is prevented from exceeding the allowable time Tmax.

When deleting a CAM entry from the CAM 6, the routing table creation unit 5 selects a CAM entry to be deleted using at least one of the following methods. (1) Select a CAM entry at random. (2) Select a CAM entry in the order of the shortest effective length. (3) Select a CAM entry in the order of the longest effective length. (4) Select a CAM entry in the shortest order of the linked RAM tree. Selection When the method (3) is used, the routing table creation unit 5
Is the CAM of (/ 32) which is the entry of the host address
You can select an entry. When using the above method (4), the CAM entry is compared with the RAM tree length from the RAM entry connected by the link, and R
The CAM entry with the shorter AM tree length is deleted.

For example, in the example shown in FIG. 8, the routing table creator 5 creates the RAM tree starting from the node of the RAM entry with the prefix “96/3” and the prefix “96/3”.
Compared with the RAM tree starting from the node of the “/ 5/5” RAM entry, the node of the “96/5” RAM entry has a shorter RAM tree, so that the “96/5” corresponding to the RAM entry has the shorter length. Delete the CAM entry.

The routing table creator 5 executes the selection process using the method (4) described above, so that the RAM tree linked to the CAM entry is placed on the RAM entry or in a corresponding location in the working memory (not shown). Write the number of stages. And
When deleting a CAM entry by the method (4), the routing table creation unit 5 refers to the previously written stage number, selects and deletes the CAM entry connected to the shortest RAM tree by a link.

FIG. 7 is a diagram showing an example of processing for reducing the number of stages in the RAM tree 17 by adding an entry to the CAM 6. In FIG. 7, the entry A ′ of the CAM 6A (reference numeral 25)
The prefix "M" is registered by a RAM tree 17A including a node 26 (entry A), a node 27 (entry B), a node 28 (entry M), and a node 29 (entry X). Consider a case where a new prefix “N” is registered in such a routing table 20A.

In this case, for example, the following is assumed. That is, if the node 30 (entry Y) is added after the node 29 (entry X), the prefix “N”
Can be registered in the routing table 20A. However, when the node 30 is added, the number of stages (the number of accesses to the RAM) of the RAM tree 17A exceeds the maximum number of accesses δmax.

In this case, the routing table creation unit 5 sets the root of the RAM tree 17A for the prefix “N”.
, And a leaf to be added (l
eaf), an entry M ′ (reference numeral 31) corresponding to the node 32 (entry M) located in the middle of the node 30 (entry Y)
Is added to the CAM 6A (step S14). Thereafter, the node 30 (entry Y) is added (step S15).

In this way, even if the node 30 is added, the number of stages of the RAM tree 17A related to the prefix “N” becomes almost half that before the addition of the node 30. As a result, the number of accesses to the RAM becomes the maximum number of accesses δ
It can be kept below max. Further, since the number of accesses to the RAM is reduced, the search time for the prefix “N” is reduced.

Although the example in which the number of stages of the RAM tree is reduced to approximately half has been described with reference to FIG. 7, when there is no branch tree from the root node 26 to the leaf node 30 as in this example, If the entries corresponding to the entry X of the node 29 and the entry Y of the node 30 are stored in the CAM 6A, the number of accesses to the RAM can be further reduced.

As described above, when the number of stages of the RAM tree (the number of accesses) is reduced by adding an entry to the CAM, the number of accesses is reduced as much as possible without affecting the search for other prefixes. It is preferable to select an appropriate entry.

Returning to FIG. 6, after step S15, the routing table creator 5 associates the prefix “N” stored in the routing table 20 with the corresponding next hop address.

That is, if the corresponding next hop address is already R
When stored in the AM 7, the two are related so that the next hop address is given to the address search unit 9 as the next hop address corresponding to the prefix "N". At this time, if the corresponding next hop address is not set in the routing table 20,
The next hop address and the prefix “N” are stored in the routing table 20 in an associated state.

Thus, when a packet destined for the prefix "N" is input to the routing mechanism 3, the address search unit 9 acquires the next hop address corresponding to the prefix "N", and Forwarded to next hop address. When the above process is completed, the process returns to step S4, and the routing table creating unit 5 performs the above-described processes of steps S5 to S15 for another prefix received from the routing protocol processing unit 4.

<Deletion of CAM entry> Routing table creation unit 5
In the update process of the routing table 20, C
When the entry of AM6 (or CAM6A) runs short, one of the CAM entries is forcibly deleted. Hereinafter, the process of deleting the CAM entry will be described.

When the entry of the CAM 6 is forcibly deleted, it must be confirmed that there is no problem in the prefix search performed after the CAM entry is deleted. For this reason, the routing table creation unit 5
When the entry is forcibly deleted, the RA indicated by the CAM address of the CAM entry to be deleted is used.
If the RAM tree starting from the M address has another CAM entry (for example, a CAM holding a prefix shorter than the prefix held in the CAM entry to be deleted)
Entry), and confirm that the number of stages in the RAM tree counted from the node linked to the other CAM entry does not exceed the maximum access count δmax.

FIG. 8 is a diagram showing an example of forcible CAM entry deletion processing. As shown in FIG.
Stores the CAM entries of “96/3” and “96/5”, and the routing table creating unit 5 stores the CAM entries of “96/5”, for example.
CAM entry is deleted. In this case, the routing table creator 5 confirms that it can be deleted by the following procedure.

That is, the routing table creation unit 5 searches the CAM 6B for a CAM entry having a prefix shorter than the CAM entry “96/5” to be deleted. In this example, C
AM entry "96/3" is found. Next, the routing table creation unit 5 routes the CAM entry “96/3” to the root.
Check that all the RAM trees do not exceed the maximum access count δmax. In this case, the RAM from the node of the RAM entry with the prefix “96/3” to the node of the RAM entry with the prefix “99/8”
Count the number of levels in the tree and confirm that the number does not exceed the maximum access count δmax.

<Deletion of RAM Entry> Next, a process of deleting a RAM entry by the routing table creation unit 5 will be described. FIG. 9 is a diagram illustrating an example of a RAM entry deletion process. In FIG. 9, the routing table creation unit 5 is about to delete the RAM entry (node 32) having the prefix “99/8”. CA of RAM entry of “99/8”
The starting point on M6 is the entry of prefix “96/4”
(Reference numeral 38). Further, each of the nodes 33 and 34 in FIG.
The RAM entry 35 is a working entry having no substance, and the RAM entries of the nodes 32, 36, and 37 are RAM entries having a substance.

First, the routing table creation unit 5 confirms that the node 32 has no child nodes. Next, the routing table creation unit 5
Refers to the node 33 of “96/6” corresponding to the parent node of the node 32. The child node of node 33 is node 3
2, only the routing table creation unit 5
("96/6" RAM entry) is determined to be deleteable.

Next, the routing table creation unit 5 refers to the node 34 corresponding to the parent node of the node 33. Since the child node of the node 34 is only the node 33, the routing table creation unit 5
Determines that the node 34 (the entry of “96/5”) can also be deleted.

Next, the routing table creating section 5 refers to the node 35 corresponding to the parent node of the node 34. Since the child node of the node 35 is only the node 34, the routing table creation unit 5
Determines that the node 35 (the entry of “96/4”) can be deleted. Since the node 35 is linked to the CAM entry 38, the node 35 determines that the CAM entry 38 can be deleted.

Next, the routing table creation unit 5 refers to the node 36 corresponding to the parent node of the node 35. Node 36
Makes the node 37 (the entry of "112/4") a child node in addition to the node 34, so the routing table creation unit 5 judges that the node 36 (the entry of "96/3") cannot be deleted.

Then, the routing table creator 5 deletes the nodes 32 to 35 and the CAM entry 38 which have been judged to be deletable. In this way, unnecessary RAM entries and CA
The M entry is deleted.

In order for the routing table creation unit 5 to execute the above-described deletion processing, it is necessary that information as to whether a certain RAM entry (node) is linked to a CAM entry is held in advance. Therefore, a bit indicating the presence or absence of a link with the CAM entry is prepared in the RAM entry of each node, and if there is a link with the CAM entry, one of “0” and “1” is set, If there is no link, the other of “0” and “1” is set.

The routing table creator 5 refers to the bit set in the RAM entry to be determined whether or not to delete in the above-described deletion processing, and has a bit indicating that a link is set. When deleting a RAM entry, the CA linked to the RAM entry is deleted.
The M entry is also deleted.

According to the first embodiment, the routing table 20 has the CAM 6 and the RAM 7, and the prefix is stored across the CAM 6 and the RAM 7. For this reason, the time required for routing can be reduced as compared with the routing using only the RAM tree. Also, by using the CAM 6 and the RAM 7 together, the CAM 6
More prefixes (entries) can be stored in the routing table 20 than when drinking is used.

Further, the routing table creator 5 determines the utilization rate ηr of the CAM 6, the utilization rate ηc of the RAM, the difference δ, the maximum number of accesses δmax, the access time τr of one RAM tree, and the maximum allowable time Tmax of packet routing. A new prefix registration process (update process of the routing table 20) is performed using the new prefix. Thus, the prefix can be stored in the routing table 20 in an optimum state. Therefore, the number of accesses to the RAM (the number of stages in the RAM tree 17) is prevented while preventing the CAM 6 from overflowing.
Is reduced as much as possible, so that high-speed routing can be achieved.

Thus, a high-speed and large-capacity routing table can be configured.

<Second Embodiment> Next, a second embodiment of the present invention will be described. The second embodiment has common points with the first embodiment, and therefore only different points will be described. In the second embodiment, a packet destination information management device according to the present invention is provided with a virtual private network (VP).
N: Virtual Private Network).

The VPN is a technology for creating a virtual private network on the Internet. FIG.
It is a figure showing the example of. As shown in FIG. 10, the ISP (Int
In the network 51 of the Internet Service Provider (VPN), VPNs 52 and 53 that can be exclusively used by each user (here, the company A and the company B) are provided.

The packet transmitted from each site (terminal device) of company A is transmitted only to company A via company A's VPN 52 and is not leaked to other companies such as company B. In addition, V of company A
Packets from other companies such as company B do not flow into PN 52. The VPN 53 of the company B is the same as the VPN 52. A number of such virtual dedicated lines coexist in the ISP network 51 and inexpensive connections are provided by sharing the equipment.

Normally, the addresses used by the company A and the company B are determined independently, so that the same address may be used. Therefore, each of the edge routers 54 and 55
When transferring a packet to the PN 52 or the VPN 53, an identifier called a VPN-id indicating which corporate network the packet belongs to is added to the packet together with the IP address.

The structure of each of the edge routers 54 and 55 is shown in FIG.
The configuration is almost the same as that of the router 1 shown in FIG. FIG. 11 is a diagram showing an example of the routing table 20B provided in the routing mechanism 3 (see FIG. 1) of each of the edge routers 54 and 55.

As shown in FIG. 11, CAM6D has V
An entry of an extended prefix composed of a combination of a PN-id and a prefix is stored. The extension prefix is a continuous bit string in which a bit string forming a VPN-id and a bit string forming a prefix are connected in series.

In FIG. 11, “VPN-i
d: prefix ”is changed to“ 0: A ”,“ 1: B ”,“ 2:
C "is actually a variable-length bit string. In this example, VPN-id = 1 is the VP of the company A.
N-id, VPN-id = 2 is the VPN of company B
-Id. Further, VPN-id = 0 is a special VPN identifier as an identifier for the public Internet, and is assigned to a person who uses the ISP network 51 without using VPN.

Except for the points described above, the configuration of the CAM 6D and the RAM tree 17D, the processing by the path creation unit 5, and the routing processing by the address search unit 9 are the same as those in the first embodiment, and therefore description thereof is omitted.

According to the second embodiment, as the contents of the CAM 6D, in addition to the IP address, the VPN identifier (VP)
N-id) is used for the extended prefix,
The CAM entry and the RAM tree are configured without being aware of the VPN. As a result, without adding access to the CAM 6D and adding data to the RAM 7, the VPN
The routing search can be separated for each.

Further, a special VPN identifier (for example, VP
By using (N-id = 0) as an identifier for the public Internet, VPN and non-VPN traffic can be searched in the same routing table 20B.

[Supplementary Notes] The present invention can be specified as follows. (Supplementary Note 1) An apparatus for managing destination information of a packet for selecting a path of a packet, comprising: a first memory; and a second memory having a lower retrieval speed and a higher degree of integration than the first memory. A destination information management device for a packet, comprising: a creation unit that creates a routing table in which the destination information is stored so as to extend over the first memory and the second memory. (Supplementary Note 2) The apparatus further includes a threshold storage unit that stores a threshold of the usage rate of the first memory, wherein the creating unit obtains the usage rate of the first memory, and stores the obtained usage rate in the threshold storage unit. 2. The destination information management device for packets according to claim 1, wherein the destination information to be stored in the routing table is stored only in the first memory when the value is less than the threshold. (Supplementary Note 3) The apparatus further includes an allowable time storage unit that stores a maximum allowable time when obtaining information on an output route corresponding to the destination information stored in the routing table, wherein the creating unit is configured to perform the operation within the maximum allowable time. A state in which the destination information is straddled between the first memory and the second memory so that destination information of the packet is searched from a routing table and information of an output route corresponding to the searched destination information is obtained. Appendix 1
Or the destination information management device for packets described in 2. (Supplementary Note 4) The information processing apparatus further includes an access count storage unit that stores a maximum access count to the second memory that is possible within the maximum allowable time, wherein the creation unit is required to search for destination information stored in the routing table. If the number of accesses to the second memory is greater than or equal to the maximum number of accesses, the number of accesses is stored in or is scheduled to be stored in the second memory such that the number of accesses is less than the maximum number of accesses. 4. The packet destination information management device according to claim 3, wherein the destination information is stored in the first memory. (Supplementary Note 5) The destination information is composed of a bit string of a predetermined length, and the creation unit stores from the most significant bit of the bit string to a predetermined bit in the first memory, and stores the bit from the predetermined bit to the least significant bit. Storing in the second memory;
A destination information management device for a packet according to supplementary note 1. (Supplementary note 6) The packet destination information management device according to supplementary note 1, wherein the destination information is a destination IP network address of the packet. (Supplementary note 7) The packet destination information management device according to supplementary note 1, wherein the destination information is a combination of a virtual private network identifier and a packet destination IP network address. (Supplementary note 8) The packet destination information management device according to supplementary note 7, wherein the creating unit stores the identifier only in the first memory. (Supplementary Note 9) The destination information of the packet is the first memory and the first memory.
A routing table stored in a state that the information retrieval speed is lower than that of the second memory and the second memory with a higher degree of integration is stored, and destination information corresponding to the input packet is retrieved from the routing table, and the retrieved destination is retrieved. A packet route selection device comprising: a search unit that acquires information on an output route corresponding to the information. (Supplementary Note 10) A method of managing destination information of a packet for selecting a route of the packet by a management device,
The management device may store the destination information in a first memory and the first memory.
A destination information management method for a packet, comprising: creating a routing table stored over a second memory having a lower information search speed and a higher degree of integration than a memory. (Supplementary Note 11) The management device stores a threshold of the usage rate of the first memory, acquires the stored usage rate of the first memory, and stores the acquired usage rate in the threshold storage unit. 11. The packet destination information management method according to claim 10, wherein the destination information to be stored in the routing table is stored only in the first memory when the number is less than the number. (Supplementary Note 12) The management device stores a maximum allowable time for obtaining information on an output route corresponding to the destination information stored in the routing table, and stores the destination of the packet from the routing table within the maximum allowable time. Additional information 10 or 11 in which information is retrieved and the destination information is stored in a state of straddling the first memory and the second memory so that information on an output route corresponding to the retrieved destination information is obtained. The destination information management method of the described packet. (Supplementary Note 13) The management device stores a maximum number of accesses to the second memory that is possible within the maximum allowable time, and stores the maximum number of accesses to the second memory necessary for searching for the destination information stored in the routing table.
When the number of accesses to the memory is equal to or more than the maximum number of accesses, the destination information stored in or scheduled to be stored in the second memory is set so that the number of accesses is less than the maximum number of accesses. The destination information management method for packets described in Supplementary Note 12 stored in the first memory. (Supplementary Note 14) The destination information is composed of a bit string of a predetermined length, and the management device stores from the most significant bit of the bit string to a predetermined bit in the first memory, and stores the bit from the predetermined bit to the least significant bit. 11. The method according to claim 10, wherein the destination information is stored in the second memory. (Supplementary note 15) The packet destination information management method according to supplementary note 10, wherein the destination information is a destination IP network address of the packet. (Supplementary note 16) The packet destination information management method according to supplementary note 10, wherein the destination information is a combination of a virtual private network identifier and a packet destination IP network address. (Supplementary note 17) The packet destination information management method according to supplementary note 16, wherein the management device stores the identifier only in the first memory. (Supplementary Note 18) A method of selecting a packet route by a packet route selection device, wherein the route selection device comprises:
Creates a routing table in which destination information of a packet is stored over a first memory and a second memory having a lower information retrieval speed and a higher degree of integration than the first memory, and corresponds to an input packet. Searching for the destination information to be performed from the routing table,
A method of selecting a packet route, including obtaining information on an output route corresponding to the searched destination information.

[0123]

According to the present invention, it is possible to hold more prefixes than a routing table created by the CAM system, and to search for prefixes faster than a routing table created by the RAM tree system. can do.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a router.

FIG. 2 is a configuration diagram of a CAM.

FIG. 3 is an explanatory diagram of processing for adding a node (entry).

FIG. 4 is an explanatory diagram of a routing table.

FIG. 5 is a flowchart showing a process of adding a prefix.

FIG. 6 is a flowchart showing a process of adding a prefix.

FIG. 7 is an explanatory diagram of a process for reducing the number of stages in a RAM tree.

FIG. 8 is a diagram showing an example of CAM entry deletion.

FIG. 9 is a diagram showing an example of RAM entry deletion.

FIG. 10 is an explanatory diagram of a VPN.

FIG. 11 is an explanatory diagram of a routing table.

FIG. 12 is an explanatory diagram of a conventional technique.

FIG. 13 is an explanatory diagram of a conventional technique.

FIG. 14 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 Reference Signs List 1 router 2 interface card 3 routing mechanism 4 routing protocol processing unit 5 route calculation / routing table preparation unit 6 CAM 7 RAM 8 header extraction unit 9 address search unit 10 transfer processing unit 12 data array / mask array 13 priority encoder 14 auxiliary RAM 17 RAM tree 20 Routing table

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K030 GA01 GA06 HA08 HB29 HD03 HD09 KA01 KA05 KA13 LB05 LE03 MA13

Claims (5)

[Claims] An apparatus for managing destination information of a packet for selecting a path of a packet, comprising: a first memory; and a second memory having a lower information retrieval speed and a higher degree of integration than the first memory. A destination information management device for a packet, comprising: a creation unit that creates a routing table in which the destination information is stored so as to extend over the first memory and the second memory. 2. The apparatus according to claim 1, further comprising a threshold storage unit that stores a threshold value of the usage rate of the first memory, wherein the creating unit obtains the usage rate of the first memory, and the obtained usage rate is stored in the threshold storage unit. 2. The packet destination information management device according to claim 1, wherein when the number is less than the stored threshold, the destination information to be stored in the routing table is stored only in the first memory. 3. An apparatus according to claim 1, further comprising an allowable time storage unit for storing a maximum allowable time for obtaining information on an output route corresponding to the destination information stored in said routing table, wherein said creating unit stores said maximum allowable time within said maximum allowable time. The destination information is straddled between the first memory and the second memory so that destination information of the packet is retrieved from the routing table and information of an output route corresponding to the retrieved destination information is obtained. 3. The packet destination information management device according to claim 1, wherein the packet is stored in a state. 4. The apparatus according to claim 1, further comprising: an access count storage unit storing a maximum access count to the second memory within the maximum allowable time, wherein the creation unit searches for the destination information stored in the routing table. If the required number of accesses to the second memory is greater than or equal to the maximum number of accesses, the number of accesses is stored or scheduled to be stored in the second memory such that the number of accesses is less than the maximum number of accesses. 4. The apparatus according to claim 3, wherein the destination information is stored in the first memory. 5. A routing table in which destination information of a packet is stored across a first memory and a second memory having a lower information retrieval speed and a higher degree of integration than the first memory. A packet routing apparatus comprising: a search unit that searches destination information corresponding to a packet from the routing table and obtains information on an output route corresponding to the searched destination information.