JP2002207633A - Electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the operational speed of an electronic device equipped with a destructive read type memory such as a DRAM and its controller by drastically shortening the cycle time of reading. SOLUTION: The destructive read type memory 4 has no rewriting control part, a controller 5 holds data read out of the destructive read type memory 4, and a coherency control part 6 holds the memory coherency of the destructive read type memory 4. For example, when the controller 5 begins to operate, data necessary for the controller 5 are transferred to the destructive read type memory 4 altogether at a time, and when the controller 5 finishes operating, data read out of the destructive read type memory 4 together at a time are transferred from the controller 5 to the destructive read type memory 4 together.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a destructive read memory such as a DRAM (Dynamic Random Access Memory) and an electronic device having a control device therefor.

[0002]

2. Description of the Related Art FIG. 32 is a conceptual diagram of an essential part of an example of a conventional electronic device having a destructive read memory and its control device. In FIG. 32, 1 is a destructive read memory, 2 is a rewrite control unit provided in the destructive read memory 1, and 3 is a device that reads data from the destructive read memory 1 and writes data to the destructive read memory 1. It is a control device.

FIG. 33 is a time chart showing an operation example of the conventional electronic device shown in FIG. 32. FIG. 33A shows a command applied from the control device 3 to the destructive read memory 1, and FIG. The read data and the data written to the destructive read memory 1, and FIG. 33C shows the internal operation of the destructive read memory 1.

[0004] For example, the control unit 3 sends the data "DAT" from the address "Adr1" to the destructive read type memory 1.
When a command "READ1" to read "A1" is given, the destructive read memory 1 responds to this by performing an output operation (destructive read) of data "DATA1" from the address "Adr1", and The write control unit 2 rewrites the data “DATA1” to the address “Adr1”.

[0005] Next, from the address "Adr2" to the data "DATA" from the control device 3 to the destructive read memory 1
When a command "READ2" to read "2" is given, the destructive read memory 1 responds to this by performing an output operation (destructive read) of data "DATA2" from the address "Adr2", and The write control unit 2 rewrites the data “DATA2” to the address “Adr2”.

As described above, in the conventional electronic device shown in FIG. 32, the destructive read memory 1 executes rewriting of the data which is destructively read, while the control device 3
When data is read from the destructive read memory 1, it is assumed that the read data is rewritten and held in the destructive read memory 1, that is, a rewrite instruction is issued to the destructive read memory 1. Works without doing. As a result, the cycle time at the time of reading is the sum of the time from the start of access by inputting an address to the data output (hereinafter referred to as data output time) and the time from the completion of rewriting of the read data.

[0007]

In recent years, DRAMs, which are destructive read-out memories, and information devices, such as personal computers and mobile phones, which are electronic devices having a control device for the DRAMs, have been required to have higher functions. ing. In order to realize this, it is necessary to improve the processing performance of the processor.

Factors that determine the processing performance of the processor include "effective operation parallelism of the instruction operation unit" and "access latency from the instruction operation unit to the DRAM".
The "effective parallelism of the instruction operation unit" has been improved by changing the operation processing architecture such as superscalar or VLIW (very long instruction word).

However, the "access latency from the instruction operation unit to the DRAM" has a problem that the cycle speed of the DRAM used as the main memory is lower than that of the processor. Therefore, as a method for improving the effective cycle speed of the DRAM,
"Multi-bank DRAM" and "higher operating frequency of DRAM" have been proposed.

In the "multi-bank DRAM", the interleave operation can be performed between banks by optimizing the order of DRAM addresses accessed by the controller. Therefore, the probability of a page miss in each bank is reduced. The effective cycle time of the DRAM can be approximated to the column cycle time instead of the row cycle time, and the cycle time for reading can be reduced.

However, when the number of banks is about two to four, the address order is not so optimized, and it is difficult to frequently perform interleave operations between banks. Interleave operations between banks are frequently performed. Therefore, it is necessary to increase the number of banks. However, when the number of banks is increased, the chip area and the power consumption increase in proportion to the number of banks, so that the number of banks is limited. For this reason, DR
By making the AM a multi-bank, there is a limit in reducing the cycle time at the time of reading.

[0012] As a method for achieving "higher operating frequency of DRAM", there is a method of increasing the operating frequency of a transmission line on a motherboard. However, in order to increase the operating frequency of the transmission line, a board having good transmission line characteristics is required, and a design considering the transmission line characteristics is required. For this reason, design cost and design time increase.

As described above, in the "multi-bank DRAM", since the chip area and the power consumption increase in proportion to the number of banks, the number of banks is limited.
"Higher operating frequency of RAM" increases design cost and design time. Therefore, in such a method,
There is a problem that the cycle time at the time of reading cannot be reduced.

In view of the foregoing, the present invention is an electronic device including a destructive read-out memory such as a DRAM and a control device therefor. The read-out cycle time can be greatly reduced and the speed can be increased. It is an object of the present invention to provide an electronic device which can be used.

[0015]

According to a first aspect of the present invention, there is provided an electronic apparatus including a destructive read memory and a control device for controlling the destructive read memory, wherein the destructive read memory performs a rewrite operation. Instead, the control device operates to hold the data read from the destructive read memory and to maintain the memory coherency (coherency as a memory) of the destructive read memory.

According to the first aspect, the control device operates to hold the data read from the destructive read memory and to maintain the memory coherency of the destructive read memory. This eliminates the need to rewrite data that has been destructively read.

According to a second aspect of the present invention, there is provided an electronic device including a destructive read-type memory and a control device for controlling the destructive read-type memory, wherein the destructive read-type memory has a rewrite control unit, Indicates whether or not to perform a rewrite operation on the destructive read-type memory when making a data read request to the destructive read-type memory, and indicates that the rewrite operation should not be performed on the destructive read-type memory. Is to hold data read from the destructive read memory and operate to maintain the memory coherency of the destructive read memory.

According to the second invention, when the control device instructs that the rewrite should not be performed on the destructive read memory, the control device holds the data read from the destructive read memory, and Therefore, the destructive read memory does not need to perform a rewrite operation for data for which rewrite has not been instructed by the control device.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
A first embodiment and a second embodiment of the present invention will be described.

First Embodiment FIGS. 1 to 17 FIG. 1 is a conceptual view of a main part of a first embodiment (an embodiment of the first invention) of the present invention. In FIG. 1, reference numeral 4 denotes a destructive read type memory having no rewrite control unit, and reference numeral 5 denotes a control device for reading data from the destructive read type memory 4, writing data to the destructive read type memory 4, and the like. When data is read from the readout type memory 4, it is assumed that the destructive readout type memory 4 does not rewrite the read out data and the destructive readout type memory 4 does not hold the read data. It works. Reference numeral 6 denotes a memory coherency control unit that controls the memory coherency of the destructive read memory 4.

FIG. 2 is a flowchart conceptually showing a memory coherency operation in the first embodiment of the present invention. In the first embodiment of the present invention, when the control device 5 needs data of a certain address “Adr1” of the destructive read memory 4, the address is determined based on a read request from the control device 5 to the destructive read memory 4. The data of "Adr1" is transferred from the destructive read memory 4 to the control device 5, and the data of the address "Adr1" is used in the control device 5. Thereafter, the data of the address "Adr1" is transferred to the control device 5.
Is transferred to the destructive read memory 4 and the memory coherency of the destructive read memory 4 is maintained.

FIG. 3 is a time chart showing an operation example of the first embodiment of the present invention. FIG. 3A shows a command applied from the control device 5 to the destructive read memory 4, and FIG. FIG. 3C shows the internal operation of the destructive read memory 4 and the output data and the data to be written to the destructive read memory 4.

For example, when the control device 5 needs the data “DATA1” of the address “Adr1” of the destructive read memory 4, the control device 5 sends the data “DATA1” of the address “Adr1” to the destructive read memory 4. In response to this, the destructive read memory 4 performs an output operation (destructive read) of the data "DATA1" from the address "Adr1".

Next, the control device 5 controls the destructive read type memory 4
When the controller 5 needs the data “DATA2” of the address “Adr2”, the controller 5 gives the destructive read memory 4 a command “READ2” for reading the data “DATA2” of the address “Adr2”, In response to this, the memory 4 performs an output operation (destructive reading) of the data “DATA2” from the address “Adr2”.

Next, the control unit 5 operates the destructive read type memory 4
When the use of the data “DATA1” of the address “Adr1” is completed, the control device 5 gives the destructive read memory 4 a command “WRITE1” for writing the data “DATA1” to the address “Adr1” and performs the destructive read. In response to this, the type memory 4 performs an operation of writing data “DATA1” to the address “Adr1”.

Although not shown, the control device 5 transmits the data “DATA” at the address “Adr2” of the destructive read memory 4.
When the use of “2” is completed, the control device 5 stores the data “DAT” in the address “Adr2” in the destructive read memory 4.
A command "WRITE2" to write "A2" is given, and the destructive read memory 4 responds to this and performs a write operation of data "DATA2" to the address "Adr2".

As described above, in the first embodiment of the present invention, the destructive read memory 4 does not perform the data rewriting operation after the data output operation of the address requested by the control device 5, When data is read from the destructive read memory 4, the destructive read memory 4 does not rewrite the read data, and the destructive read memory 4 holds the read data. It operates on the premise that there is no data, and transfers the data read from the destructive read memory 4 from the control device 5 to the destructive read memory 4 after use is completed, so that the memory coherency of the destructive read memory 4 is maintained.

The control device 5 can be constituted only by hardware, or can be constituted by hardware and software. Further, the memory coherency control unit 6 can be configured only with hardware, can be configured with hardware and software, or can be configured only with software. In addition,
The hardware includes a group of circuits that can be operated logically manufactured on a semiconductor, and the software includes an input program and an OS written in a specific programming language.
(Operating system), middleware and firmware.

FIG. 4 is a diagram showing a first configuration example of the control device 5 and the memory coherency control unit 6. In the first configuration example, the control device 5 is configured by hardware, and therefore, the memory coherency control unit 6 is also configured by hardware. In the case of the first configuration example, as hardware operations for maintaining memory coherency, data used by the control device 5 is transferred from the destructive read-type memory 4 to the control device 5, and data used by the control device 5 is completed. Is transferred from the control device 5 to the destructive read memory 4.

FIG. 5 is a flowchart of the memory coherency operation in the first configuration example. In the first configuration example, when the control device 5 starts operating and data used by the control device 5 is generated, the data used by the control device 5 is transferred to the control device 5.
Is determined (step S5-1), and if the data to be used by the control device 5 is not in the control device 5, the data is transferred from the destructive read memory 4 to the control device 5 (step S5-1). Step S5-2).

After the data is transferred from the destructive read memory 4 to the control device 5, or when it is determined in step S5-1 that the data to be used by the control device 5 is in the control device 5, the control is performed. It is determined whether or not the used data exists in the device 5 (step S5-3). If there is the used data in the control device 5, the use of the data from the control device 5 to the destructive read memory 4 is completed. The transferred data is transferred (step S5-4).

After the data is transferred from the control device 5 to the destructive read memory 4, or when it is determined in step S5-3 that there is no data in the control device 5 which has been completely used, the control device 5 It is determined whether or not there is a next operation (step S5-5). If the control device 5 has an operation other than data transfer as the next operation, the operation is executed (step S5-6), and It returns to S5-1. On the other hand, if it is determined in step S5-5 that there is no next operation in the control device 5, the operation is terminated.

There are several possible operation timings for steps S5-2 and S5-4. As one example, when the operation of the control device 5 is started, data necessary for the control device 5 is collectively transferred from the destructive read memory 4 to the control device 5, and when the operation of the control device 5 is completed, the destructive read memory is An operation timing is conceivable in which data collectively read from memory 4 is collectively transferred from control device 5 to destructive read memory 4. As another example, data necessary for the control device 5 is sequentially transferred from the destructive read type memory 4 to the control device 5, and when the operation of the control device 5 ends, the destructive read type memory 4
An operation timing may be considered in which data sequentially read out from the memory is collectively transferred from the control device 5 to the destructive read memory 4.

FIG. 6 is a conceptual diagram of an example of hardware in the first configuration example. The control device 5 includes an external bus interface unit 7, an operation unit 8, and a memory interface unit 9. The external bus interface unit 7, the operation unit 8, and the memory interface unit 9 are connected by an internal bus 10.

The external bus interface 7 arbitrates with the external bus. The operation unit 8 includes an operation control unit 11 and an operation unit 12, and the operation control unit 11 controls the operation unit 12. The memory interface unit 9 includes a memory control unit 13 and a memory coherency control unit 14. The memory control unit 13 issues a read request or a write request and an address to the destructive read memory 4 based on the information held by the memory coherency control unit 14. And the like.

The memory coherency control unit 14 has a read data table 15 and reads an address value of data that does not have memory coherency (data that has not been rewritten to the destructive read memory 4).
To perform an operation such as storing in a file. The set condition (address value storage condition) for the read data table 15 is when a read request is issued to the destructive read memory 4, and the reset condition (address value erase condition) is when data is transmitted to the destructive read memory 4.

FIG. 7 is a diagram showing a second configuration example of the control device 5 and the memory coherency control unit 6. In the second configuration example, the control device 5 is configured by hardware and software, and the memory coherency control unit 6 is configured by hardware. In the case of the second configuration example, the software does not perform control relating to memory coherency such as a memory transfer instruction (memory read instruction, memory write instruction), and executes an operation instruction unrelated to memory coherency. As hardware operations for maintaining memory coherency, destruction of data used by the control device 5 is transferred from the readout memory 4 to the control device 5 and destruction of data used by the control device 5 is completed by the control device 5. Transfer to the read-type memory 4 is performed.

FIG. 8 is a flowchart of the memory coherency operation in the second configuration example.
The flow of the memory coherency operation is the same as in the configuration example. That is, in the second configuration example, when the control device 5 starts operating and data to be used by the control device 5 is generated, it is determined whether or not data to be used by the control device 5 is in the control device 5 ( In step S8-1), if the data to be used by the control device 5 is not in the control device 5, the data is transferred from the destructive read memory 4 to the control device 5 (step S8-2).

After the data is transferred from the destructive read memory 4 to the control device 5, or when it is determined in step S8-1 that the data to be used by the control device 5 is in the control device 5, the control is performed. It is determined whether there is data that has been used in the device 5 (step S8-3). If there is data that has been used in the control device 5, the use of the data from the control device 5 to the destructive read memory 4 is completed. The transferred data is transferred (step S8-4).

After the data has been transferred from the control device 5 to the destructive read memory 4, or when it is determined in step S8-3 that there is no data whose use has been completed in the control device 5, the control device 5 It is determined whether or not there is a next operation (step S8-5). If the control device 5 has an operation other than the data transfer as the next operation, the operation is executed (step S8-6), and It returns to S8-1. On the other hand, if it is determined in step S8-5 that there is no next operation in the control device 5, the operation is terminated.

There are several possible operation timings for steps S8-2 and S8-4. As one example, when the operation of the control device 5 is started, data necessary for the control device 5 is collectively transferred from the destructive read memory 4 to the control device 5, and when the operation of the control device 5 is completed, the destructive read memory is An operation timing is conceivable in which data collectively read from memory 4 is collectively transferred from control device 5 to destructive read memory 4. As another example, data necessary for the control device 5 is sequentially transferred from the destructive read type memory 4 to the control device 5, and when the operation of the control device 5 ends, the destructive read type memory 4
An operation timing may be considered in which data sequentially read out from the memory is collectively transferred from the control device 5 to the destructive read memory 4.

FIG. 9 is a diagram showing a third configuration example of the control device 5 and the memory coherency control unit 6. In the third configuration example, the control device 5 is configured by hardware and software, and the memory coherency control unit 6 is also configured by hardware and software. In the case of the third configuration example, as a hardware operation for maintaining the memory coherency, when the stored data is to be replaced in the data storage unit, the data corresponding to the data storage position of the replacement target is stored in the destructive read type memory 4. Is written back.

The software controls memory coherency, such as a memory transfer instruction (memory read instruction, memory write instruction), and also executes an operation instruction unrelated to memory coherency. In addition,
The operation of data transfer from the control device 5 to the destructive read memory 4 is described as a read instruction in input target software (including a code generated by a compiler).

FIG. 10 is a flowchart of a hardware portion of the memory coherency operation in the third configuration example. In the hardware part of the third configuration example, the instruction is executed based on the description of the software (step S10-).
1) It is determined whether the instruction to be executed is an instruction to read data from the destructive read memory 4 (step S10).
-2) If the instruction to be executed is an instruction for reading data from the destructive read memory 4, the destructive read memory 4
Is transferred to the control device 5 from the server (step S10).
-3).

Then, it is determined whether or not there is data to be replaced in the data storage unit in the control device 5 (step S1).
0-4) If there is data to be replaced in the data storage unit in the control device 5, the data to be replaced is transferred from the control device 5 to the destructive read memory 4 (step S10).
-5).

After the data to be replaced is transferred from the control device 5 to the destructive readout memory 4, or when it is determined in step S10-4 that there is no data to be replaced in the control device 5, or , Step S1
When it is determined in 0-2 that the execution instruction is not an instruction for reading data from the destructive read memory 4, it is determined whether or not the control device 5 has the next operation (step S1).
0-6), if the control device 5 has an operation other than the data transfer as the next operation, the operation is executed (step S10-7), and the process returns to step S10-1. On the other hand, if it is determined in step S10-6 that there is no next operation in control device 5, the operation is terminated.

As for the operation timings of steps S10-3 and S10-5, other operation timings can be considered. As one example, when the operation of the control device 5 is started, data necessary for the control device 5 is collectively transferred from the destructive read memory 4 to the control device 5, and when the operation of the control device 5 is completed, the destructive read memory is An operation timing may be considered in which data read collectively from memory 4 is collectively transferred from control device 5 to destructive read memory 4.

FIG. 11 is a flowchart of the software portion of the memory coherency operation in the third configuration example. In the software portion of the third configuration example, when the program operation is started, data is read from the destructive read memory 4 to the control device 5 (step S11-1), and the data read from the destructive read memory 4 is used. The calculation is performed (step S11-2), and it is determined whether or not the next description is provided for the control device 5 (step S11-3). If the next description is provided for the control device 5, the process proceeds to step S1.
Return to 1-1. On the other hand, if it is determined in step S11-3 that there is no next description of the control device 5, the program operation ends.

FIG. 12 is a diagram showing a description example of an input program for the memory coherency operation in the third configuration example.
This description example includes a LOAD_NP instruction (LOAD_NO
_PRECHARGE: destructive read type LOAD instruction)
Describes that data is transferred from the destructive read memory 4 to the control device 5 and then an ADD instruction (addition instruction) and a MUL instruction (multiplication instruction) are executed.

FIG. 13 is a diagram showing a fourth configuration example of the control device 5 and the memory coherency control unit 6. In the fourth configuration example, the control device 5 is configured by hardware and software, and the memory coherency control unit 6 is configured by software. In the case of the fourth configuration example, the software performs control relating to memory coherency such as a memory transfer instruction (memory read instruction and memory write instruction), executes an operation instruction unrelated to memory coherency, and the like. When data to be used in the control device 5 is generated, the data is transferred from the destructive read memory 4 to the control device 5.

However, the data transfer operation from the destructive read memory 4 to the control device 5 is described as a read instruction in the software to be input (including the code generated by the compiler), and the destructive read from the control device 5 is performed. The data transfer to the type memory 4 is described as a write instruction in software to be input (including a code generated by a compiler).

FIG. 14 is a flowchart of the software portion of the memory coherency operation in the fourth configuration example. In the software portion of the fourth configuration example, when the program operation is started, data is read from the destructive read memory 4 to the control device 5 (step S14-1), and the data read from the destructive read memory 4 is used. An operation is performed (step S14-2), and the data to be replaced is transferred from the control device 5 to the destructive read memory 4 (step S1).
4-3) It is determined whether or not the next description is provided for the control device 5 (step S14-4). If the next description is provided for the control device 5, the process returns to step S14-1. On the other hand, if it is determined in step S14-4 that there is no next description of the control device 5, the program operation ends.

As for the operation timings of steps S14-1 and S14-3, other operation timings can be considered. As one example, at the start of a program, data necessary for the control device 5 is transferred collectively from the destructive read memory 4 to the control device 5, and when the operation of the control device 5 ends, the data is collectively transferred from the destructive read memory 4. An operation timing may be considered in which the read data is collectively transferred from the control device 5 to the destructive read memory 4.

FIG. 15 is a diagram showing an example of a description of an input program for a memory coherency operation in the fourth configuration example.
In this description example, data is transferred from the destructive read type memory 4 to the control device 5 by the LOAD_NP instruction,
It describes that an instruction and a MUL instruction are executed, and then data is transferred from the control device 5 to the destructive read memory 4 by a STORE instruction.

FIG. 16 is a diagram showing a fifth configuration example of the control device 5 and the memory coherency control unit 6. In the fifth configuration example, similarly to the fourth configuration example, the control device 5 is configured by hardware and software, and the memory coherency control unit 6 is configured by software. In the case of the fifth configuration example, the software performs control relating to memory coherency such as a memory transfer instruction (memory read instruction and memory write instruction), executes an operation instruction unrelated to memory coherency, and the like. When data to be used in the control device 5 is generated, the data is transferred from the destructive read memory 4 to the control device 5.

The operation of data transfer from the destructive read memory 4 to the control device 5 is described as a read instruction in software to be input (including a code generated by a compiler). The data transfer operation to the destructive read memory 4 is not described in the software to be input, but is guaranteed by software such as an OS or middleware.

FIG. 17 is a diagram showing a description example of an input program for a memory coherency operation in the fifth configuration example of the control device 5 and the memory coherency control unit 6. In this description example, the destructive read type memory 4 is read by the LOAD_NP instruction.
Is transferred to the control device 5 by the ADD instruction and M
Executing a UL instruction is described.

As described above, according to the first embodiment of the present invention, the destructive read memory 4 does not rewrite the data after the operation of outputting the data at the address requested by the control device 5, but performs the destructive read. The control device 5 is responsible for the memory coherency of the pattern memory 4. Therefore, when designing the destructive read memory 4, it is only necessary to stop the rewriting operation for the conventional destructive read memory, and the design cost of the destructive read memory 4 can be reduced. Further, since the read time in the destructive read memory 4 is only the data output time, the cycle time at the time of reading can be greatly reduced, and the speed can be increased.

Second Embodiment FIG. 18 to FIG. 31 FIG. 18 is a conceptual diagram of a main part of a second embodiment (one embodiment of the second invention) of the present invention. In FIG. 18, 16 is a destructive read memory, 17 is a rewrite control unit provided in the destructive read memory 16, and 18 reads data from the destructive read memory 16, writes data to the destructive read memory 16, and the like. A control device that, when making a data read request to the destructive read-type memory 16, supplies a dewrite select signal for instructing whether to perform a rewrite operation to the destructive read-type memory 16 to the destructive read-type memory 16, When it is instructed that rewriting should not be performed on the destructive read memory 16, the rewritten data is not rewritten on the destructive read memory 16, and the data is read on the destructive read memory 16. It operates on the assumption that no data is held. A memory coherency controller 19 controls the memory coherency of the destructive read memory 16.

The control device 18 can be constituted only by hardware, or can be constituted by hardware and software. Memory coherency control unit 19
Can be composed only of hardware, can be composed of hardware and software,
It can also be configured with software only.

FIG. 19 is a diagram showing a first configuration example of the control device 18 and the memory coherency control section 19. In the first configuration example, the control device 18 is configured by hardware, and therefore, the memory coherency control unit 19 is also configured by hardware. In the case of the first configuration example, as the hardware operation for maintaining the memory coherency, the transfer of the data used by the control device 18 from the destructive read memory 16 to the control device 18 and the use by the control device 18 are completed. Dirty
Data (data not rewritten when data is transferred from the destructive read memory 16 to the control device 18) is transferred from the control device 18 to the destructive read memory 16.

FIG. 20 is a flowchart of the memory coherency operation in the first configuration example. In the first configuration example, when the control device 18 starts operating and data to be used by the control device 18 is generated, it is determined whether or not the data to be used by the control device 18 is in the control device 18 (step S1). S20-1) If the data to be used in the control device 18 is not in the control device 18, a read request is issued from the control device 18 to the destructive read memory 16 and the destructive read memory 16 performs a rewrite operation. Is issued (step S20-).
2), data is transferred from the destructive read memory 16 to the control device 18 (step S20-3).

From the destructive read memory 16 to the controller 18
After the data has been transferred to step S20-
1, the data used by the control device 18 is the control device 1
If it is determined that the dirty data exists in the control device 18, it is determined whether or not there is dirty data used in the control device 18 (step S20-4). If there is, dirty data is transferred from the control device 18 to the destructive read memory 16 (step S20-5).

The destructive read memory 16 from the controller 18
After the dirty data is transferred, or when it is determined in step S20-4 that there is no used dirty data in the control device 18, it is determined whether the control device 18 has the next operation. Is determined (step S2).
0-6) If the control device 18 has an operation other than the data transfer as the next operation, the operation is executed (step S20-7), and the process returns to step S20-1. On the other hand, if it is determined in step S20-6 that there is no next operation in control device 18, the operation is terminated.

The operation timing of steps S20-3 and S20-5 can be considered in several ways. As one example, when the operation of the control device 18 is started, data necessary for the control device 18 is collectively stored in the destructive read memory 16 from the control device 18.
And when the operation of the control device 18 is completed, the dirty data is collectively transferred from the control device 18 to the destructive read memory 1
6 may be considered. As another example, data necessary for the control device 18 is sequentially transferred from the destructive read memory 16 to the control device 18, and when the operation of the control device 18 is completed, the dirty data is collectively read from the control device 18. An operation timing of transferring the data to the pattern memory 16 is conceivable.

FIG. 21 is a diagram showing a second configuration example of the control device 18 and the memory coherency control section 19. In the second configuration example, the control device 18 is configured by hardware and software, and the memory coherency control unit 19 is configured by hardware. In the case of the second configuration example, the software does not perform control relating to memory coherency such as a memory transfer instruction (memory read instruction, memory write instruction), and executes an operation instruction unrelated to memory coherency. The hardware operation for maintaining the memory coherency includes the data destructive read type memory 16 used by the control device 18 and the control device 1
8 and the destructive read-out memory 1 of the dirty data used by the controller 18 from the controller 18.
6 is performed.

FIG. 22 is a flow chart of the memory coherency operation in the second configuration example, and has the same memory coherency operation flow as in the first configuration example. That is, in the second configuration example, when the control device 18 starts operating and data to be used by the control device 18 is generated, it is determined whether data to be used by the control device 18 is in the control device 18 ( In step S22-1), if the data to be used in the control device 18 is not in the control device 18, a read request is issued from the control device 18 to the destructive read memory 16 and the destructive read memory 16 is rewritten. A rewrite selection signal indicating whether or not to perform an operation is issued (step S22-2), and the control device 1 is transmitted from the destructive read memory 16 to the controller 1.
The data is transferred to No. 8 (step S22-3).

From the destructive read memory 16 to the controller 18
After the data has been transferred to step S22-
1, the data used by the control device 18 is the control device 1
If it is determined that the dirty data exists in the control device 18, it is determined whether or not there is dirty data used in the control device 18 (step S22-4). If there is, dirty data is transferred from the control device 18 to the destructive read memory 16 (step S22-5).

The destructive read memory 16 from the controller 18
After the dirty data is transferred, or when it is determined in step S22-4 that there is no used dirty data in the control device 18, it is determined whether the control device 18 has the next operation. Is determined (step S2).
2-6) If the control device 18 has an operation other than the data transfer as the next operation, the operation is executed (step S22-7), and the process returns to step S22-1. On the other hand, if it is determined in step S22-6 that there is no next operation in control device 18, the operation is terminated.

The operation timing of steps S22-3 and S22-5 can be considered in several ways. As one example, when the operation of the control device 18 is started, data necessary for the control device 18 is collectively stored in the destructive read memory 16 from the control device 18.
And when the operation of the control device 18 is completed, the dirty data is collectively transferred from the control device 18 to the destructive read memory 1
6 may be considered. As another example, data necessary for the control device 18 is sequentially transferred from the destructive read memory 16 to the control device 18, and when the operation of the control device 18 is completed, the dirty data is collectively read from the control device 18. An operation timing of transferring the data to the pattern memory 16 is conceivable.

FIG. 23 is a diagram showing a third configuration example of the control unit 18 and the memory coherency control unit 19. In the third configuration example, the control device 18 is configured by hardware and software, and the memory coherency control unit 19 is also configured by hardware and software. In the case of the third configuration example, as a hardware operation for maintaining memory coherency, when stored data is to be replaced in the data storage unit, data corresponding to the data storage position of the replacement target is stored in the destructive read memory 16. Is written back.

The software controls memory coherency such as a memory transfer command (memory read command and memory write command), and also executes an operation command unrelated to the memory coherency. In addition,
The operation of data transfer to the destructive read memory 16 is described as a read instruction in input target software (including code generated by a compiler).

FIG. 24 is a flowchart of a hardware portion of the memory coherency operation in the third configuration example. In the hardware portion of the third configuration example, the instruction is executed based on the description of the software (step S24-).
1) It is determined whether the instruction to be executed is an instruction to read data from the destructive read memory 16 (step S).
24-2) If the instruction to be executed is an instruction to read data from the destructive read memory 16, the control unit 18
Issues a read request to the destructive read memory 16 and issues a rewrite select signal (step S2).
4-3), data is transferred from the destructive read memory 16 to the control device 18 (step S24-4).

Then, it is determined whether or not there is dirty data to be replaced in the data storage unit in the control device 18 (step S24-5), and the dirty data to be replaced is stored in the data storage unit in the control device 18. If there is, the dirty data to be replaced is transferred from the control device 18 to the destructive read memory 16 (step S24-6).

After the data to be replaced is transferred from the control device 18 to the destructive read memory 16, or when it is determined in step S24-5 that there is no dirty data to be replaced in the control device 18, If it is determined in step S24-2 that the execution instruction is not an instruction to read data from the destructive read memory 16, it is determined whether the control device 18 has the next operation (step S24-7). If the control device 5 has an operation other than dirty data transfer as the next operation, the operation is executed (step S24-8), and step S2 is performed.
Return to 4-1. On the other hand, if it is determined in step S24-7 that there is no next operation in the control device 18, the operation is terminated.

As for the operation timings of steps S24-4 and S24-6, other operation timings can be considered. As one example, when the operation of the control device 18 starts,
The data necessary for the control unit 18 is collectively transferred from the destructive read memory 16 to the control unit 18, and when the operation of the control unit 18 is completed, the dirty data is collectively transferred to the control unit 18.
An operation timing at which the data is transferred to the destructive readout type memory 16 is considered.

FIG. 25 is a flowchart of the software portion of the memory coherency operation in the third configuration example. In the software part of the third configuration example, when the program operation is started, the destructive read memory 16
The data is read out from the memory 16 (step S25-1), an operation is performed using the data read out from the destructive read-out memory 16 (step S25-2). Judge (Step S25-
3) If there is the following description about the control device 18,
It returns to step S25-1. In contrast, step S
If it is determined in 25-3 that there is no next description of the control device 18, the program operation is terminated.

FIG. 26 is a diagram showing an example of a description of an input program for a memory coherency operation in the third configuration example.
This description example includes a LOAD_P instruction (LOAD_PRE
CHAR: a LOAD instruction for performing a rewrite operation in the destructive read memory) to transfer data from the destructive read memory 16 to the control device 18 and a LOAD_NP instruction to transfer data from the destructive read memory 16 to the control device 18. , ADD instruction is described.

FIG. 27 is a diagram showing a fourth configuration example of the control unit 18 and the memory coherency control unit 19. In the fourth configuration example, the control device 18 is configured by hardware and software, and the memory coherency control unit 19 is configured by software. The software is
It performs control related to memory coherency such as memory transfer instructions (memory read instructions and memory write instructions), executes operation instructions unrelated to memory coherency, etc. Is transferred from the destructive read memory 16 to the control device 18.

However, the data transfer operation from the destructive read memory 16 to the control device 18 is described as a read command in software to be input (including a code generated by a compiler), and the destructive read from the control device 18 is performed. The data transfer to the type memory 16 is described as a write instruction in software to be input (including a code generated by a compiler).

FIG. 28 is a flowchart of the software portion of the memory coherency operation in the fourth configuration example. In the software portion of the fourth configuration example, when the program operation is started, the destructive read memory 16
(Step S28-1), an operation is performed using the data read from the destructive read memory 16 (step S28-2), and then the dirty data to be replaced is destructively read from the control device 18. Type memory 16
(Step S28-3), and it is determined whether or not there is the following description about the control device 18 (step S28-).
4) If there is the following description about the control device 18,
It returns to step S28-1. In contrast, step S
If it is determined in 28-4 that there is no next description of the control device 18, the program operation ends.

Regarding the operation timing of steps S28-1 and S28-3, another example of operation is conceivable. As one example, at the start of a program, data necessary for the control device 18 is transferred from the destructive read memory 16 to the control device 18 at a time. An operation timing may be considered in which the read data is collectively transferred from the control device 18 to the destructive read memory 16.

FIG. 29 is a diagram showing a description example of an input program for a memory coherency operation in the fourth configuration example.
In this description example, data is transferred from the destructive read memory 16 to the control device 18 by a LOAD_NP instruction,
_P instruction to transfer data from the destructive read memory 16 to the control device 18, and then execute the ADD instruction to
It is described that data is transferred from the control device 18 to the destructive read memory 16 by the RE instruction.

FIG. 30 is a diagram showing a fifth configuration example of the control device 18 and the memory coherency control section 19. In the fifth configuration example, similarly to the fourth configuration example, the control device 18 is configured by hardware and software, and the memory coherency control unit 19 is configured by software. In the case of the fifth configuration example, the software performs control relating to memory coherency such as a memory transfer instruction (memory read instruction and memory write instruction), executes an operation instruction unrelated to memory coherency, and the like. When data to be used is generated in the control device 18, the data is transferred from the destructive read memory 16 to the control device 18.
Transfer to

However, the operation of data transfer from the destructive read memory 16 to the control device 18 is described as a read command in software to be input (including a code generated by a compiler). The data transfer operation to the destructive read memory 16 is guaranteed by software such as an OS or middleware, instead of being described in input target software.

FIG. 31 is a diagram showing an example of a description of an input program for a memory coherency operation in the fifth configuration example.
In this description example, data is transferred from the destructive read memory 16 to the control device 18 by a LOAD_P instruction,
It is described that data is transferred from the destructive read memory 16 to the control device 18 by the NP instruction, and then the ADD instruction is executed.

As described above, according to the second embodiment of the present invention, when the read type memory 16 instructs that the rewrite should not be performed by the read type memory 16, the control unit 18 performs the destructive read operation. The destructive read memory 16 operates to hold the data read from the type memory 16 and maintain the memory coherency of the destructive read memory 16. There is no need to perform a rewrite operation. Therefore, the read time of data for which rewriting is not instructed is only the data output time, so that the cycle time at the time of reading can be significantly reduced, and the speed can be increased.

[0088]

As described above, according to the first aspect of the present invention, the destructive read type memory does not need to perform the rewrite operation of the destructively read data. When designing a memory, it is only necessary to stop the rewriting operation for the conventional destructive read memory, and the design cost of the destructive read memory can be suppressed. Further, the read time in the destructive read memory is only the data output time, so that the cycle time at the time of read can be significantly reduced, and the speed can be increased.

According to the second aspect of the present invention, the destructive read memory does not need to perform a rewrite operation on data for which a rewrite operation has not been instructed by the control device. The read time of the data that has not been read is only the data output time, so that the cycle time at the time of read can be significantly reduced, and the speed can be increased.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of a main part of a first embodiment (an embodiment of the first invention) of the present invention.

FIG. 2 is a flowchart conceptually showing a memory coherency operation in the first embodiment of the present invention.

FIG. 3 is a time chart illustrating an operation example of the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a first configuration example of a control device and a memory coherency control unit provided in the first embodiment of the present invention.

FIG. 5 is a flowchart of a memory coherency operation in the first configuration example of the control device and the memory coherency control unit provided in the first embodiment of the present invention.

FIG. 6 is a conceptual diagram illustrating an example of hardware in a first configuration example of a control device and a memory coherency control unit included in the first embodiment of the present invention.

FIG. 7 is a diagram illustrating a second configuration example of a control device and a memory coherency control unit included in the first embodiment of the present invention.

FIG. 8 is a flowchart of a memory coherency operation in a second configuration example of the control device and the memory coherency control unit provided in the first embodiment of the present invention.

FIG. 9 is a diagram illustrating a third configuration example of the control device and the memory coherency control unit included in the first embodiment of the present invention.

FIG. 10 is a flowchart of a hardware part of a memory coherency operation in a third configuration example of the control device and the memory coherency control unit provided in the first embodiment of the present invention.

FIG. 11 is a flowchart of a software part of a memory coherency operation in a third configuration example of the control device and the memory coherency control unit provided in the first embodiment of the present invention.

FIG. 12 is a diagram illustrating a description example of an input program of a memory coherency operation in a third configuration example of the control device and the memory coherency control unit provided in the first embodiment of the present invention.

FIG. 13 is a diagram illustrating a fourth configuration example of the control device and the memory coherency control unit provided in the first embodiment of the present invention.

FIG. 14 is a flowchart of a software part of a memory coherency operation in a fourth configuration example of the control device and the memory coherency control unit provided in the first embodiment of the present invention.

FIG. 15 is a diagram illustrating a description example of an input program of a memory coherency operation in a fourth configuration example of the control device and the memory coherency control unit provided in the first embodiment of the present invention.

FIG. 16 is a diagram illustrating a fifth configuration example of the control device and the memory coherency control unit provided in the first embodiment of the present invention.

FIG. 17 is a diagram illustrating a description example of an input program of a memory coherency operation in a fifth configuration example of the control device and the memory coherency control unit provided in the first embodiment of the present invention.

FIG. 18 is a conceptual diagram of a main part of a second embodiment (one embodiment of the second invention) of the present invention.

FIG. 19 is a diagram illustrating a first configuration example of a control device and a memory coherency control unit provided in a second embodiment of the present invention.

FIG. 20 is a flowchart of a memory coherency operation in the first configuration example of the control device and the memory coherency control unit provided in the second embodiment of the present invention.

FIG. 21 is a diagram illustrating a second configuration example of a control device and a memory coherency control unit provided in the second embodiment of the present invention.

FIG. 22 is a flowchart of a memory coherency operation in a second configuration example of the control device and the memory coherency control unit provided in the second embodiment of the present invention.

FIG. 23 is a diagram illustrating a third configuration example of the control device and the memory coherency control unit provided in the second embodiment of the present invention.

FIG. 24 is a flowchart of a hardware part of a memory coherency operation in a third configuration example of the control device and the memory coherency control unit provided in the second embodiment of the present invention.

FIG. 25 is a flowchart of a software part of a memory coherency operation in a third configuration example of the control device and the memory coherency control unit provided in the second embodiment of the present invention.

FIG. 26 is a diagram illustrating a description example of an input program of a memory coherency operation in a third configuration example of the control device and the memory coherency control unit provided in the second embodiment of the present invention.

FIG. 27 is a diagram illustrating a fourth configuration example of the control device and the memory coherency control unit provided in the second embodiment of the present invention.

FIG. 28 is a flowchart of a software part of a memory coherency operation in a fourth configuration example of the control device and the memory coherency control unit provided in the second embodiment of the present invention.

FIG. 29 is a diagram illustrating a description example of an input program of a memory coherency operation in a fourth configuration example of the control device and the memory coherency control unit provided in the second embodiment of the present invention.

FIG. 30 is a diagram illustrating a fifth configuration example of the control device and the memory coherency control unit provided in the second embodiment of the present invention.

FIG. 31 is a diagram illustrating a description example of an input program of a memory coherency operation in a fifth configuration example of the control device and the memory coherency control unit provided in the second embodiment of the present invention.

FIG. 32 is a conceptual diagram of a main part of an example of a conventional electronic device.

FIG. 33 is a time chart showing an operation example of the conventional electronic device shown in FIG. 32;

[Explanation of symbols]

 (FIG. 1) 4 Destructive readout memory 5 Controller 6 Memory coherency control unit (FIG. 6) 7 External bus interface unit 8 Operation unit 9 Memory interface unit 10 Internal bus 11 Operation control unit 12 Operation unit 13 Memory control unit 14 Memory coherency Control unit 15 Read data table (FIG. 18) 16 Destructive read type memory 17 Rewrite control unit 18 Control device 19 Memory coherency control unit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B005 MM01 NN01 PP01 5B024 AA15 BA25 BA29 CA15 CA27 5B060 CB08

Claims (3)

[Claims] 1. An electronic device comprising a destructive read memory and a control device for controlling the destructive read memory, wherein the destructive read memory does not perform a rewrite operation, and the control device includes the destructive read memory. An electronic device which operates to hold data read from a memory and to maintain memory coherency of the destructive read memory. 2. An electronic device comprising: a destructive read memory; and a control device for controlling the destructive read memory, wherein the destructive read memory has a rewrite control unit; When performing a data read request to the type memory, instructing whether to perform a rewrite operation on the destructive read type memory, and instructing that rewrite should not be performed on the destructive read type memory,
An electronic device, wherein the electronic device operates to hold data read from the destructive read memory and maintain memory coherency of the destructive read memory. 3. The data transfer operation from the controller to the destructive read memory for maintaining the memory coherency of the destructive read memory is guaranteed by software other than the input target software. The electronic device according to claim 1 or 2, wherein