JP2002207456A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a simplified circuit constitution and a display driving circuit in which an internal power supply system and an output power supply system do not coexist. SOLUTION: A two input NAND section 20i which is operated by a power supply voltage VCC2 for external circuit driving and an inverter section 30i form a holding circuit. Clock signals CLK are inverted by a level shift section 50, level shifted to a power supply voltage VCC2 and supplied to the NAND section 20i as clock signals /CK. When the signals CLK are 'H' and display data DTi are 'H', NMOS 11 and 12 of a data setting section 10i are turned on and output signals SB of the section 30i become 'L'. When the clock signals CLK are 'H' and the data DTi are 'L', the NMOS 11 is turned off and the signals SB become 'H'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit used as a driving circuit for a liquid crystal panel (hereinafter, referred to as “LCD”).

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional LCD drive circuit. The LCD drive circuit captures and holds the display data DTi based on the timing of the clock signal CLK, and a logic level of the data held in the data capture unit 60 (for example, 0V /
5V) to the level for driving the LCD (for example, 0 V / 20
V), and an output transistor unit 80 for driving the display electrodes of the LCD.

The data fetch unit 60 has a data latch 61. The display terminal DTi of the data latch 61 receives the display data DTi, the clock terminal C receives the clock signal CLK, and
Each is given. Data latch 6
The first output terminal Q is connected to the input side of an inverter 62 composed of a P-channel MOS transistor (hereinafter, referred to as “PMOS”) 62p and an N-channel MOS transistor (hereinafter, referred to as “NMOS”) 62n. The output side of the inverter 62 includes a PMOS 63p and an NMOS 63
n is connected to the input side of an inverter 63 composed of n. The data latch 61 and the inverters 62 and 63 include:
A power supply voltage VCC1 of 5 V of the internal power supply system is supplied, and the display data DTi held in the data latch 61 and its inverted signal are output from the inverters 63 and 62 as logic level signals S1 and S2, respectively. It has become.

The level shift section 70 includes NMOSs 71 and 7
2, and the gates of these NMOSs 71 and 72 are supplied with the signals S1 and S2 of the data acquisition unit 60. The sources of the NMOSs 71 and 72 are connected to the ground voltage GN.
D and the drains are PMOS 73 and 74, respectively.
Connected to the drain of The gates of the PMOSs 73 and 74 are connected to the drains of the NMOSs 72 and 71, respectively.
Is given. NMOS 72 and PMO
The node N1, which is the connection point of the drain of S74, is connected to the PMO
Inverter 75 composed of S75p and NMOS 75n
Is connected to the input side. A power supply voltage VCC2 of an output power supply system is supplied to the inverter 75, and a signal S3 converted into a voltage for driving the LCD is output from the inverter 75 and supplied to the output transistor unit 80.

In such a drive circuit, the display data DTi of the internal logic level is held in the data latch 61 at the rising timing of the clock signal CLK of the same internal logic level. The display data DTi held in the data latch 61 is output from the inverters 62 and 63 as complementary signals S1 and S2 of an internal logic level.

The signals S1 and S2 are supplied to NMOSs 71 and 72 of the level shift unit 70,
One of the switches 1 and 72 is turned on, and the other is turned off. When the NMOS 71 is turned on, this NMOS
The drain of the transistor 71 becomes almost the ground voltage GND, and the PMOS
74 is turned on, and the node N1 is almost at the power supply voltage VC.
C2. When the NMOS 72 is turned on,
Node N1 is almost at ground voltage GND.

The voltage at the node N1 is inverted by an inverter 75, and the output side of the inverter 75 outputs a signal S3 of an output power supply system.
Given to.

[0008]

However, the conventional driving circuit has the following problems. Display data D
For each Ti, a data capture unit 60, a level shift unit 70 and an output transistor unit 80 as shown in FIG.
Since the scale of the drive circuit increases with an increase in the number of display pixels of the CD, simplification of the circuit configuration has been a problem.

Further, a 5V internal power supply system is provided in the drive circuit,
Since the output power supply system of 20V is mixed, if the wells of the internal power supply system and the output power supply system are provided close to each other in the semiconductor substrate, the power supply potential may fluctuate via the substrate due to surges such as electrostatic noise. , Latch-up may occur. Therefore, it is necessary to isolate the internal power supply system and the output power supply system, and it has been difficult to reduce the pattern area.

The present invention solves the problems of the prior art and provides a semiconductor integrated circuit having a display drive circuit in which a circuit configuration is simplified and an internal power supply system and an output power supply system are not mixed. Things.

[0011]

In order to solve the above-mentioned problems, the present invention provides a two-input NAND gate (hereinafter referred to as a "NAND") operating in an output power supply system for driving an external circuit in a semiconductor integrated circuit. ) Which operates on the output power supply system, inverts a signal on the output side of the NAND unit to generate an output signal for driving the external circuit, and outputs the output signal to a first terminal of the NAND unit. An inverter section applied to an input side, a level shift section applied to a second input side of the NAND section, inverting a clock signal of an internal power supply system for logic operation, converting the clock signal to a level of the output power supply system, A data setting section for connecting an output side of the NAND section to a common potential and setting the output side potential to a common potential when both the output data of the power supply system and the clock signal become high level. I have.

According to the present invention, since the semiconductor integrated circuit is configured as described above, the following operation is performed.

When both the output data for the logical operation and the clock signal attain the "H" level, the data setting unit sets the NA.
The output side of the ND section is connected to a common potential. This allows
An output signal for driving an external circuit set to “H” of the output power supply system is output from the inverter unit. If the output data is at "L" level when the clock signal goes to "H", the clock signal inverted by the level shift unit and converted to "L" of the output power supply system is output from the NAND unit. 2
To the input side. As a result, the output side of the NAND unit becomes “H”, and the inverter unit outputs an output signal for driving an external circuit set to “L” of the output power supply system.

[0014]

FIG. 1 is a configuration diagram of an LCD drive circuit showing an embodiment of the present invention. This LCD drive circuit is configured as a semiconductor integrated circuit, and outputs a plurality of output data (for example, 5 V) of an internal power supply system (for example, 5 V) for logic operation.
(Display data) Data setting unit 10i, NAND unit 20i, inverter unit 30 provided for each DTi (i = 1 to n)
i, the output transistor section 40i, and each display data DT
i includes a level shift unit 50 provided in common.

The data setting section 10i has NMOSs 11 and 12 connected in series between a node NA and a common potential (for example, ground voltage) GND. Has become. The gate of the NMOS 12 is supplied with a clock signal CK from a level shift unit 50 described later.

The NAND unit 20i is connected to a PM connected in parallel.
OSs 21 and 22 and NMOSs 23 and 24 connected in series
, A first input side of which is provided with a clock signal / C from the level shift unit 50.
K (where “/” indicates inversion) is given, and the second input side is connected to the node NB which is the output side of the inverter unit 30i. The output side of the NAND unit 20i is connected to the node NA and the inverter unit 30i.
i is connected to the input side.

The inverter unit 30i includes a PMOS 31 and an N
This is a typical inverter composed of a MOS 32, which inverts a signal SA at a node NA applied to the gates of the PMOS 31 and the NMOS 32 and outputs a signal SB to an output node NB. A power supply voltage VC of an output power supply system (for example, 20 V) for driving an external circuit such as an LCD is provided in the NAND unit 20i and the inverter unit 30i.
C2 is supplied.

The node NB is connected to the second
And the input side of an output transistor unit 40i for driving the display electrodes of the LCD.

On the other hand, the level shift section 50 is provided with a clock signal CL indicating the timing of fetching the display data DTi.
K is converted into a level corresponding to the power supply voltage VCC2 of the output power supply system.

The level shift unit 50 includes an NMOS 5 controlled by complementary clock signals / CLK and CLK.
1,52. The sources of the NMOSs 51 and 52 are connected to the ground voltage GND, and the drains are PMOs, respectively.
It is connected to the power supply voltage VCC2 via S53 and S54. The gates of the PMOSs 53 and 54 are respectively N
The drains of the MOSs 52 and 51 are connected.

The drain of the NMOS 52 is connected to a PMOS 55
p and NMOS 55n are connected to the input side of an inverter 55, and the output side of the inverter 55 is connected to the PMO
Inverter 5 composed of S56p and NMOS 56n
6 is connected to the input side. The power supply voltage VCC2 of the output power supply system is supplied to the inverters 55 and 56, and complementary clock signals CK and / CK converted to the level of the output power supply system are output from the inverters 55 and 56, respectively.
Each is output.

FIG. 3 is a signal waveform diagram showing an example of the operation of FIG. Hereinafter, the operation of FIG. 1 will be described with reference to FIG.

At time t1 in FIG. 3, the display data DTi
Is the level "L", the NMO of the data setting unit 10i
S11 is off. Here, when the clock signal CLK rises to the level “H”, the clock signal / CK output from the level shift unit 50 becomes “L”.
The PMOS 21 of the AND unit 20i is turned on, and the NMOS 2
3 turns off. Thereby, the signal S of the node NA is
A becomes "H" regardless of the state before time t1.
Further, the signal SA is inverted by the inverter unit 30i, and the signal SB at the node NB becomes “L”.

When the clock signal CLK falls to "L" at time t2, the clock signal / CK becomes "H", the PMOS 21 is turned off, and the NMOS 23 is turned on. However, since the signal SB output from the inverter unit 30i is "L", the PMOS 23 remains on, the NMOS 21 remains off, and the node NA
Is held at "H".

When the display data DTi changes to "H" at time t3, the NMOS 11 is turned on, but the NMOS 12 is turned off.
A and SB do not change.

When the clock signal CLK rises at time t4, the NMOS 12 is turned on. NMOS
11 is turned on by the display data DTi of "H", the node NA is almost at the ground voltage GND, and the signals SA and SB change to "L" and "H", respectively.

Thereafter, the clock signal C at time t5
The signals SA and SB held by the NAND unit 20i and the inverter unit 30i do not change with respect to the fall of LK and the change of the display data DTi at times t6 and t7.

At time t8, when the display data DTi is "H" and the clock signal CLK rises, at time t4
The same situation occurs when. However, at time t8, the signals SA and SB are "L" and "H", respectively, so that the signals SA and SB do not change.

At time t9, when the display data DTi is "L" and the clock signal CLK rises, at time t1
The same situation occurs when. Thereby, the signals SA,
SB changes to “H” and “L”, respectively.

That is, in this LCD drive circuit, the data signal DTi of the logical level of the internal power supply system is applied to the clock signal C
It is taken in according to the rise timing of LK, converted to the level of the power supply voltage VCC2 of the output power supply system, and given to the output transistor unit 40i as a signal SB.

As described above, the LCD drive circuit according to the present embodiment has the following advantages. (1) The level of the clock signal CLK of the internal power supply system is
A level shift unit 50 is provided for converting the voltage to the output power supply voltage, and the converted clock signals CK and / CK are supplied in common to a plurality of display data DTi. As a result, circuit elements can be reduced and the circuit configuration can be simplified as compared with a conventional circuit that performs a level shift for each display data DTi.

(2) The NAND unit 20i, the inverter unit 30i, and the level shift unit 50 are configured to use only the power supply voltage VCC2 of the output power supply system. Thus, the internal power supply system and the output power supply system do not coexist in the drive circuit, and the possibility of latch-up can be eliminated.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications.

(A) Although described as an LCD drive circuit, a drive circuit of a display device such as a plasma display,
The present invention can be similarly applied to a drive circuit of an external circuit having a different power supply voltage.

(B) NMOS 1 of data setting unit 10i
2 may be a clock signal CLK of an internal power supply system.

(C) The circuit configuration of the level shift section 50 is merely an example, and any circuit configuration can be used as long as the clock signal CLK of the internal power supply system can be inverted to generate the clock signal / CK of the output power supply system.

[0037]

As described above in detail, according to the present invention, there is provided a holding circuit comprising a two-input NAND unit and an inverter unit operating on an output power supply system for driving an external circuit. A data setting unit is provided for connecting one input side of the NAND unit to a common potential based on the level of a clock signal and output data. As a result, the holding circuit can be unified in the output power supply system, and the occurrence of latch-up or the like due to the mixture of different voltages can be eliminated. In addition, a level shift unit is provided which inverts the clock signal of the internal power supply system, converts the inverted signal to the level of the output power supply system, and supplies the same to the second input side of the NAND unit. Thus, since only one level shift unit needs to be provided for a plurality of NAND units, the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an LCD drive circuit showing an embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating an example of a conventional LCD drive circuit.

FIG. 3 is a signal waveform diagram showing an example of the operation of FIG.

[Explanation of symbols]

 10i Data setting unit 20i NAND unit 30i Inverter unit 40i Output transistor unit 50 Level shift unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 H03K 19/00 101F H03K 19/0185 19/0175 F-term (Reference) 5C006 BB11 BF26 BF27 BF31 BF42 BF46 EB05 FA31 FA41 5C080 AA10 BB05 DD12 DD22 JJ03 JJ04 5F038 AV06 CD02 CD06 DF01 EZ20 5F048 AA00 AA01 AB03 AB04 AB10 AC03 5J056 AA05 AA11 BB35 BB40 BB51 CC21 DD13 DD28 DD29 EE07 GG06 KK01

Claims (1)

[Claims] 1. A two-input NAND gate that operates on an output power supply system for driving an external circuit, and operates on the output power supply system and inverts a signal on the output side of the NAND gate. An inverter for providing the output signal to the first input side of the NAND gate, and an inverter for inverting a clock signal of an internal power supply system for logic operation. A level shift unit for converting the output data to the level of the output power supply system and applying it to the second input side of the NAND gate unit; and when the output data of the internal power supply system and the clock signal both become high level. A data setting section for connecting an output side of the NAND gate section to a common potential and setting the potential on the output side to a common potential.