JP2002203826A - Method for manufacturing semiconductor device and polishing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device where a CMP polishing step for a wiring metal film can be appropriately performed and throughput of an apparatus can be enhanced and, to provide a polishing apparatus. SOLUTION: A relaying part 6, arranged between a polishing unit 2 having a plurality of polishing parts 2A-2C and a transfer robot 5 and temporarily supporting a wafer, is provided with a inspecting means for evaluating a machined surface of a wafer to have been processed. Thus, while performing a polishing step, the machining evaluation of an earlier processed wafer can be performed and productivity of the apparatus can be improved. In addition, by making the object to be inspected by the inspecting means separation widths in a surface and dishing quantity of the wiring layer formed by a damascene method, a proper machining evaluation depending on roughness and fineness of wiring patterns can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device suitable for manufacturing a device having a wiring layer formed by a damascene method, and a polishing apparatus used in the method.

[0002]

2. Description of the Related Art In recent years, the development of ultra-high density and high integration of VLSI has been supported by lithography technology capable of coping with a fine region of submicron or less. However, since the surface of the silicon wafer becomes uneven as the processing progresses in the device fabrication process, it is difficult to achieve both resolution and depth of focus in the projection exposure method, and it is necessary to focus simultaneously on the concave and convex portions of the wafer surface. Is getting harder. Because of this, at the right stage of the process,
It is indispensable to perform a planarization (planarization) process for removing irregularities on the device surface of the wafer so that the irregularities are less than the depth of focus.

One of the techniques for flattening the wafer surface is a CMP method. As is well known, the CMP method is a technique of polishing a wafer processing surface with a polishing cloth via slurry, and flattening the wafer processing surface by an oxidizing action of the slurry by the slurry and a mechanical polishing action of the polishing cloth. It is.

Although CMP was originally used in the step of planarizing an interlayer insulating film in preparation for processing a wiring pattern of the second and subsequent layers, recently, a metal film for wiring formed on an insulating film has also been used. Have been applied. This is the so-called damascene method.
This is because a groove (contact hole) for connecting an upper layer wiring and a lower layer wiring and a groove for forming a wiring are formed in an insulating film, a metal film serving as a wiring material is formed thereon, and then a groove other than the groove is formed. Is a technique for removing the metal film of the portion by CMP, and is also called an embedded wiring method. In the damascene method, the planarization is completed at the stage when the wiring pattern is formed, so that the step of planarizing the insulating film can be omitted.

As a wiring metal film applied to the damascene method, W (tungsten), Al (aluminum), Cu
(Copper). Among them, Cu is advantageous in that the resistance of the wiring can be reduced and the electromigration resistance can be improved.

[0006]

In the CMP process in the damascene method, an insulating film having a lower processing speed than a wiring layer serves as a polishing stopper. However, the progress of processing differs depending on the density and size of the wiring pattern. Therefore, even if the insulating film functions as a processing stopper to some extent, the progress of processing cannot be stopped in the high-density wiring pattern portion. As a result, over-processing of the wiring portion occurs,
Thinning occurs in which the thickness of the wiring layer is reduced. On the other hand, in a relatively low-density wiring pattern or a wide wiring portion, dishing in which the central portion of the wiring layer is depressed occurs, which causes a decrease in reliability and an uneven surface of an insulating film formed thereover.
Dishing occurs due to the difference between the polishing rate of the interlayer insulating film and the polishing rate of the metal layer at the stage of over-processing the wiring portion. Also, if the amount of processing of the Cu layer is suppressed to avoid over-processing, Cu remains between adjacent wirings (metal remaining), causing wiring failure.

Therefore, in the CMP, it is necessary to control the polishing amount with high precision, and it is important to appropriately determine the polishing end point to prevent excessive processing of the wiring portion.

Therefore, conventionally, optical measurement methods have been widely used because of their high spatial resolution.
In Japanese Patent Application Laid-Open No. 7604, the presence of a metal residue on an insulating film is confirmed based on reflected laser light.
Also, JP-A-9-298174 and JP-A-9-29
No. 8175, Japanese Patent Application Laid-Open No. 9-298176,
The thickness distribution of the insulating film is measured by a spectral reflectance measuring method while rotating the wafer.

However, the former merely detects the presence or absence of a metal film on an insulating film, and does not detect overwork such as dishing of a wiring layer. The latter is
Since the surface shapes in the same radius region in the wafer surface are averaged and detected, it is difficult to perform highly accurate processing evaluation. In particular, in a region where the wiring pattern is sparse, the amount of dishing becomes a problem, while in a region where the wiring pattern is dense, the separation width between adjacent wiring layers becomes a problem. Point detection is extremely difficult with the above method.

Next, before processing the product wafer by the CMP apparatus, the pilot wafer (monitor wafer) is usually polished and evaluated to determine whether the apparatus is in an apparatus state capable of processing the product wafer or under any conditions. I'm judging you. However, in the current CMP technology, the fluctuation of the processing characteristics is larger than that of other semiconductor manufacturing apparatuses. Therefore, in order to perform highly accurate polishing, it is necessary to flow a monitor wafer at a high frequency. On the other hand, there is an inspection (evaluation) unit provided near the loader / unloader unit of the CMP apparatus to evaluate the processed product wafer. However, the product evaluation is performed immediately before unloading. However, there is a problem that it is difficult to give feedback to the apparatus, such as a change in polishing conditions.

Therefore, the above-mentioned Japanese Patent Application Laid-Open No. 9-298174 has been disclosed.
JP-A-9-298175, JP-A-9-29817
No. 6, each of JP-A-11-307604 is provided with an inspection step for performing processing evaluation during wafer polishing, and when the wafer surface is within a predetermined condition range, polishing is stopped,
Otherwise, a technique is described in which polishing is continued. As a result, it is possible to reduce the time and consumable materials involved in the polishing evaluation of the monitor wafer, and it is possible to perform the optimum processing without being affected by fluctuations in the polishing rate and variations in the film thickness of each product wafer. Product wafer loss can be minimized.

However, in the above configuration, since the polishing operation of the product wafer cannot be performed during the inspection process, there is a problem that the time loss due to the inspection is large and the throughput of the entire apparatus cannot be improved. .

The present invention has been made in view of the above-mentioned problems, and provides a method of manufacturing a semiconductor device and a polishing apparatus capable of appropriately performing a polishing step of a wiring metal film and improving the throughput of the apparatus. The task is to

[0014]

In order to solve the above-mentioned problems, according to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: The method is characterized by comprising a step of measuring an in-plane separation width and a step of measuring a dishing amount of a wiring layer.

By performing both of the above steps, it is possible to detect the amount of processing for the region where the wiring pattern is sparse and the amount of processing for the region where the wiring pattern is dense. The polishing conditions can be set, and the polishing end point can be controlled with high accuracy.

In order to solve the above problems, a polishing apparatus according to a second aspect of the present invention includes a polishing unit having a plurality of polishing units for polishing a layer to be processed formed on a wafer surface; Transfer means for transferring the wafer to and from the unit; a relay unit disposed between the polishing unit and the transfer means, for temporarily supporting the transferred wafer; and each of the polishing units and the relay unit A polishing apparatus provided with a carrier for circulating and supplying wafers to a wafer, wherein the relay unit is provided with inspection means for evaluating a work surface of the polished wafer.

The operation of the present invention will be described. The wafer supplied from the loader unit to the relay unit by the transfer unit is transported by the carrier to each polishing unit in the polishing unit, and a predetermined polishing process is performed. On the other hand, the wafer that has been subjected to the predetermined polishing processing by the polishing unit is supplied to the relay section, and is transported from here to the unloader section by the transfer means. At this time, the processed surface of the processed wafer supplied to the relay unit is evaluated by the inspection unit to determine whether the polishing process is appropriate, and if the polishing is insufficient, the wafer is transferred to the polishing unit again. If the polishing is excessively performed, the setting of the polishing conditions such as the polishing time in the polishing section is changed. In the present invention, by performing a predetermined polishing operation in the plurality of polishing units even during the above-described wafer inspection process, the throughput of the apparatus is improved, and the inspection result by the inspection unit is transmitted to the polishing unit. Feedback,
It becomes possible to change polishing conditions and the like of a wafer during production on the spot.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing an outline of a polishing apparatus according to an embodiment of the present invention. Polishing apparatus 1 of the present embodiment
Is a polishing unit 3 having a plurality of first to third polishing units 2A, 2B, 2C, and a transfer robot 5 for transferring a wafer between the polishing unit 3 and the loader / unloader unit 4.
And a relay unit 6 for temporarily supporting the wafer when transferring the wafer from the transfer robot 5 to the polishing unit 3 and from the polishing unit 3 to the transfer robot 5.

Each of the polishing units 2A to 2C and the relay unit 6 are arranged on the same circumference, and a carrier (head) capable of supporting the wafer W corresponding to each of the polishing units 2A to 2C and the relay unit 6. 7 are provided. The carrier 7 rotates intermittently around the center O in the direction of the arrow, and
The wafer W is circulated and supplied synchronously between the 2C and the relay unit 6.

The control unit 8 controls polishing conditions such as polishing time, polishing pressure, and slurry supply amount in each of the polishing units 2A to 2C;
In addition to controlling the operation of the transfer robot 5 and the carrier 7, the setting of the polishing conditions in each of the polishing units 2A to 2C can be changed based on the inspection result of the inspection unit provided in the relay unit 6 as described later. Be composed.

Each of the polishing sections 2A to 2C has the same configuration, and is configured as, for example, a CMP polishing apparatus as shown in FIG. Each of the polishing units 2A to 2C has a polishing plate (platen) 11 supported by a rotating shaft 9 rotatable in the direction of arrow C and having an upper surface on which a polishing cloth 10 is laid. The carrier 7 has a rotating shaft 12 rotatable in the direction of arrow D. The lower surface of the carrier 7 is configured to hold the wafer W by suction with the surface to be processed Wp facing downward. Then, the wafer W is pressed against the polishing cloth 10 with a predetermined polishing pressure, and the rotating shafts 9 and 12 are rotated to polish the processing surface Wp via the slurry (abrasive) 13. .

In this embodiment, each of the polishing units 2A to 2A
An endpoint monitor (not shown) is provided on 2C,
The polishing unit 2A is controlled by the control unit 8 based on the output of each monitor.
2C is performed. The end point monitor is a conventionally known end point monitor that averages and detects a change in the state of the processed surface based on light reflected from the processed surface Wp of the wafer being polished.

The relay section 6 is provided with the inspection means according to the present invention. As shown in FIG. 3, the relay unit 6 includes an inspection stage 14 that supports a peripheral edge of a surface of the wafer W on the processing surface Wp side. Inspection stage 14 is hollow 14a
And a measuring head 15 for optically detecting the surface state of the surface to be processed Wp is disposed below the cylindrical head. The measuring head 15 is supported on a movable table 16 that can move in a direction parallel to the processing surface Wp.

In this embodiment, the measuring head 15 emits the short-wavelength irradiation light L in the ultraviolet region emitted toward the processing surface Wp.
, And supplies the output to the control unit 8. The control unit 8 measures the in-plane separation width of the wiring layer formed on the surface to be processed Wp by a damascene process described later and the dishing amount of the wiring layer based on the output of the measuring head 15. When these values are not within the predetermined range, the wafer is supplied to the polishing units 2A to 2C again for polishing as described later, or an abnormality of the apparatus is notified.

Next, the polishing apparatus 1 configured as described above
A method for manufacturing a semiconductor device using the method will be described. In the present embodiment, the polishing apparatus 1 having the above configuration is used in the step of burying and forming a copper wiring layer on an insulating film by the damascene method shown in FIG. First, a process of forming a copper wiring layer by a damascene method will be described.

After a trench 22 for embedding wiring is formed in the insulating film 21 such as SiO ₂ (silicon dioxide) by a plasma etching method (FIG. 4A), a barrier metal layer 23 is formed (FIG. 4B). A metal layer 24 is formed thereon by a CVD method, a plating method or the like to form a Cu layer (FIG. 4C).
The barrier metal layer 23 prevents diffusion of Cu into the insulating film 1,
It is formed from the viewpoint of improving the adhesion, for example, TiN
(Titanium nitride), Ta (tantalum), TaN (tantalum nitride), WN (tungsten nitride) and the like are used. Next, the Cu layer 24 other than the groove 22 is formed by the CMP method.
And the barrier metal layer 23 is removed, and C
The u wiring layer 24A is formed (FIG. 4D).

A wafer W in a state shown in FIG. 4C (hereinafter, also referred to as an unprocessed wafer) is carried into the loader / unloader section 4 of the polishing apparatus 1, and is brought into a state shown in FIG. Processed into Hereinafter, the operation of the polishing apparatus 1 will be described.

FIG. 8 is a flowchart showing the operation of the present embodiment. First, the unprocessed wafer W accommodated in the loader / unloader unit 4 is transferred by the transfer robot 5 onto the inspection stage 14 of the relay unit 6 with the work surface Wp facing downward (step S1). Then, as shown below, each polishing unit 2A
Wafers W are sequentially circulated and supplied to ２2C, and a predetermined polishing process is performed (steps S2 and S3).

The carrier 7 located in the relay section 6 holds the back surface side of the wafer W by suction, moves to the first polishing section 2A, and performs a predetermined polishing action on the work surface Wp. Here, C
Rough polishing is performed to remove irregularities on the surface of the u film 24. The polishing end point is determined based on the thickness distribution of the Cu film 24 detected by the endpoint monitor.

Next, the carrier 7 moves from the first polishing section 2A to the second polishing section 2B. Here, polishing for removing the Cu film 24 other than the groove 22 on the insulating film 21 is performed. The polishing end point is determined based on the in-plane average value of the change in reflected light intensity due to the change of the wafer surface from the Cu film 24 to the barrier metal layer 23.

Subsequently, the carrier 7 moves from the second polishing section 2B to the third polishing section 2C. Here, polishing for the purpose of removing the barrier metal layer 23 other than the groove 22 on the insulating film 21 is performed. The polishing end point is determined based on the in-plane average value of the reflected light intensity change due to the change of the wafer surface from the barrier metal layer 23 to the insulating film 21.

After the polished surface Wp of the wafer W is polished from the state shown in FIG. 4C to the state shown in FIG.
4) The carrier 7 is moved from the third polishing section 2C to the relay section 6 again, and the wafer W is mounted on the inspection stage 14 in the form shown in FIG. 3 (step S5). Thereafter, the moving unit 5 grips the processed wafer W placed on the inspection stage 14 and transports it to the loader / unloader unit 4 (step S7). Inspection of the surface state of Wp is performed (Step S)
6).

When the wafer W is positioned and placed on the inspection stage 14 with the surface to be processed Wp facing downward, the measuring head 15 located below the inspection stage 14 is moved to a predetermined chip area on the wafer set in advance. C1, C
2 and C3 (see FIG. 7), and inspect the surface condition in the area.

In this embodiment, the in-plane separation width X of the Cu wiring layer 24A in the dense portion of the wiring pattern is determined from the intensity distribution of reflected light of the irradiation light L, the amount of phase shift, and the like (see FIG. 5)
And the Cu wiring layer 24 in the portion where the wiring pattern is sparse
The dishing amount ΔY of A is measured (see FIG. 6).
In particular, since the opening 22a of the groove 22 has a tapered shape,
The separation width X according to the processing amount can be detected, whereby the thinning amount can be measured, and the thickness of the insulating film 21 can be measured indirectly.

As described above, by making the measurement target different depending on the density of the wiring pattern, it is possible to detect whether or not appropriate polishing has been performed on a device area having the density of the wiring pattern. C using CMP
The polishing conditions for the u-soft metal wiring can be appropriately controlled, and high quality assurance can be achieved. That is, a wiring layer having low resistance and high electromigration resistance can be obtained.

In this inspection step, as shown in FIG. 7, several chips located at different radial regions on the wafer W, for example, a chip C1 located at the center of the wafer, a chip C2 located at the peripheral edge of the wafer, and a space between these chips The above measurement is performed for the chip C3 located. This makes it possible to inspect whether the entire wafer W has been properly polished.

In the present embodiment, for example, the in-plane separation width of the wiring layer 24A is about 0.2 μm, and the dishing amount ΔY is 50
Each of the polishing sections 2A to 2C is set to be equal to or less than nm, but when the separation width X is less than the above-mentioned predetermined value, it is determined that the polishing is insufficient because there is a possibility of a wiring short circuit failure or a remaining metal. When the predetermined width is again performed by the polishing units 2A to 2C, and the separation width X and the dishing amount ΔY exceed the above-mentioned predetermined values, it is determined that overpolishing is performed, and the respective polishing units 2A to 2C are overpolished.
An apparatus abnormality is issued to change the polishing conditions of A to 2C or to perform maintenance of the apparatus (step S6).
Further, the output transmission timing of the endpoint monitor of each of the polishing units 2A to 2C may be changed.

The above operations are performed by the respective carriers 7 in synchronization with each other, so that the polishing of the wafer W is performed separately in each of the polishing sections 2A to 2C, while the relay section 6 performs the polishing of the wafer W immediately after polishing. Since the above-described inspection is performed, the wafer processing surface Wp can be polished without stopping the production of the product wafer. In particular, the change of the polishing condition based on the inspection result in the inspection process is reflected in the polishing process in the polishing units 2A to 2C performed in parallel,
Thereby, appropriate polishing can be maintained.

Although the embodiment of the present invention has been described above, the present invention is, of course, not limited to this, and various modifications can be made based on the technical idea of the present invention.

For example, in the above embodiment, Cu is used as the metal wiring layer 24, but the present invention is not limited to this, and the present invention is applicable to a process of forming a wiring layer made of a metal material such as Al or W. It is.

In the above-described embodiment, the wafer W is polished step by step in each of the first to third polishing units 2A to 2C. However, the entire polishing process is performed independently for each polishing unit. You may make it do. In addition, although the respective polishing units are arranged on the same circumference, they may be linearly juxtaposed.

Further, the configuration of the CMP polishing apparatus is not limited to the above-described embodiment, but may be applied to a CMP polishing apparatus that performs polishing by applying a plurality of pressure heads to one wafer.
The present invention is applicable.

Further, the intensity distribution of the reflected light is used for measuring the in-plane separation width X of the wiring layer 24, but secondary electrons generated from the irradiated surface when the electron beam is irradiated may be used. It is possible.

[0045]

As described above, according to the method of manufacturing a semiconductor device of the present invention, it is possible to perform a proper processing evaluation according to the density of a wiring pattern formed by a damascene method.
High quality assurance is possible.

According to the second aspect of the present invention, since the processing evaluation can be performed not by the average value but by the actual measurement value, the processing evaluation can be performed with high accuracy, and the variation in the processing in the wafer surface can be detected. be able to.

According to the third aspect of the present invention, the wafer processing surface can be evaluated without stopping the production of the product, so that the throughput can be improved.

According to the fourth aspect of the present invention, a damascene process using a soft metal material can be properly performed, and the device can have low electric resistance, improved electromigration resistance, and the like.

Further, according to the polishing apparatus of the present invention, it is possible to evaluate the processing of the processed surface of the processed wafer while polishing the wafer in each polishing section, thereby improving the throughput of the apparatus. be able to. In addition, when abnormal polishing is detected, feedback to each polishing unit becomes possible, and an appropriate polishing end point can be secured.

According to the invention of claim 6, processing evaluation with high spatial resolution can be performed, and according to the invention of claim 7, individual processing evaluation can be performed for each chip in a wafer surface. With these configurations, it is possible to perform processing evaluation of the wafer processing surface with high accuracy.

According to the eighth aspect of the present invention, the evaluation result of the surface to be processed previously processed can be fed back to the polishing processing of another wafer to be performed in parallel, so that appropriate processing conditions can be maintained. Can be.

[Brief description of the drawings]

FIG. 1 is a plan view showing a schematic configuration of a polishing apparatus according to an embodiment of the present invention.

FIG. 2 is a side sectional view showing an example of a configuration of each polishing unit in FIG.

FIG. 3 is a side view illustrating a configuration of a relay unit in FIG. 1;

FIG. 4 is a schematic cross-sectional view illustrating each step of a damascene process applied to an embodiment of the present invention, wherein A is a wiring groove forming step, B is a barrier metal layer forming step, and C is a wiring metal film forming step. Step D indicates a CMP polishing step.

FIG. 5 is a fragmentary cross-sectional view for explaining an in-plane separation width between wiring layers formed by a damascene process in the embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view for explaining a dishing amount of a wiring layer formed by a damascene process in the embodiment of the present invention.

FIG. 7 is a wafer plan view schematically explaining a polishing evaluation target in the embodiment of the present invention.

FIG. 8 is a flowchart illustrating an operation of the exemplary embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Polishing apparatus, 2A ... 1st grinding | polishing part, 2B ... 2nd grinding | polishing part,
2C: third polishing section, 3: polishing unit, 4: loader / unloader section, 5: transfer robot (transfer means), 6: relay section, 7: carrier, 8: control section, 14: inspection stage,
15 measuring head (inspection means), 16 moving table, 21
Insulating film, 22 groove, 23 barrier metal layer, 24 metal film (copper), 24A wiring section.

Claims (8)

[Claims] A polishing step of polishing and removing the metal film other than the grooves to form a wiring layer on a wafer having a wiring metal film formed on an insulating film having the wiring grooves formed therein;
A semiconductor device manufacturing method for performing an inspection step of inspecting a surface state of a surface to be polished of the wafer, wherein the inspection step comprises: measuring an in-plane separation width of the wiring layer; and measuring a dishing amount of the wiring layer. Measuring the semiconductor device. 2. The method according to claim 1, wherein the inspection step is performed on a predetermined chip area in the wafer surface. 3. The method according to claim 1, wherein the inspection step is performed while another wafer is being processed in the polishing step. 4. The method according to claim 1, wherein the metal film is made of copper. 5. A polishing unit having a plurality of polishing units for polishing a layer to be processed formed on a wafer surface, transfer means for transferring the wafer to and from the polishing unit, and the polishing unit and the transfer A polishing device, comprising: a relay unit disposed between the relay unit and a temporary support for the transferred wafer; and a carrier for circulating and supplying the wafer to each of the polishing units and the relay unit. A polishing unit provided with an inspection means for evaluating a surface to be processed of the polished wafer. 6. The inspection means includes: an inspection stage that supports the wafer; and a measurement head that is arranged to face the processing surface and optically detects a surface state of the processing surface. The polishing apparatus according to claim 5, wherein the polishing is performed. 7. The polishing apparatus according to claim 6, wherein the measuring head is movable in a direction parallel to the surface to be processed. 8. The polishing apparatus according to claim 5, further comprising control means capable of changing setting of polishing conditions in said polishing section based on an inspection result by said inspection means.