JP2002198528A - P-channel field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a heterojunction p-channel field-effect transistor that inhibits formation of a parasitic channel, at the same time, can be speedily operated, and has a high drive current. SOLUTION: In a channel layer 103 made of SiGe containing C, a Ge composition is linearly changed from 0 to 50% from the end section of a silicon buffer layer side 102 toward that of the side of a silicon cap layer 104, and C is selectively contained by 0.5% in a region with 40 to 50% Ge composition, namely, a region where the Ge composition exceeds 30%. On the SiGe channel layer 103, the Si cap layer 104 is provided. In the Si cap layer 104, a layer containing carbon is provided, where the layer containing carbon prevents impurities from being diffused from the SiGe channel layer for entering a gate insulating film 105, thus reducing a threshold while the critical film thickness in the SiGe channel layer 103 is being largely secured for increasing a driving current, and at the same time inhibiting drop in a threshold voltage due to the entry of the impurities to the gate insulating film 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a p-channel field effect transistor having a channel formed in a SiGeC layer.

[0002]

2. Description of the Related Art Conventionally, for the purpose of increasing the speed of a field effect transistor, Si _1-x G which is a mixed crystal of Si and Ge has been used.
e _x layer (0 <x <1) (hereinafter referred to as SiGe layer) Si
Utilizing a hetero barrier formed between the SiGe layer and the SiGe layer,
There has been reported a MOS (Metal-Oxide-Semiconductor) type field effect transistor in which a hole is confined in a layer to form a p-channel.

FIG. 22 is a sectional view showing an example of such a conventional p-channel field effect transistor (p-MOSFET). As shown in FIG.
1, a Si buffer layer 302, a SiGe channel layer 303, and a Si cap layer 304 are sequentially epitaxially grown by a UHV-CVD method or the like. The thicknesses of the Si buffer layer 302, the SiGe channel layer 303, and the Si cap layer 304 are 10 nm, 10 nm, and 5 nm, respectively, and the layers 302, 303, and 304 are not doped with impurities. A gate insulating film 305 made of a silicon oxide film and a gate electrode 30 made of a polysilicon film are formed on the Si cap layer 304.
6 are provided. Further, the Si buffer layer 302,
A source region 307 and a drain region 308 containing a high-concentration p-type impurity (for example, boron) are formed in regions located on both sides of the gate electrode 306 in a wide region extending over the SiGe channel layer 303 and the Si cap layer 304. Have been. Then, a source electrode 309 is provided over the source region 307, and a drain electrode 310 is provided over the drain region 308. The channel length and channel width of the MOS field effect transistor are
For example, they are 0.5 μm and 10 μm.

Here, FIGS. 23A and 23B show SiG
FIG. 4 is a diagram illustrating a difference in lattice constant between an e single crystal and a Si single crystal, and a cross-sectional view illustrating a state when a SiGe layer is epitaxially grown on a Si layer. As shown in FIG. 23A, the lattice constant of the SiGe single crystal is larger than the lattice constant of the Si single crystal, and therefore, as shown in FIG.
The Ge channel layer 303 is epitaxially grown on the Si buffer layer 302 under a compressive strain. In the distorted SiGe channel layer 303, the degeneracy of the energy band is released, and a band of a light hole and a heavy hole is generated.
It has a higher mobility than the degenerated holes in the i single crystal. Therefore, in a conventional p-channel field effect transistor using a Si / SiGe heterojunction, high-speed operation is realized by using a SiGe layer which has undergone compressive strain as a channel.

In the field effect transistor using the strained SiGe as a channel as described above, when the gate voltage is high, the gate insulating film 3 of the Si cap layer 304 is formed.
There is a problem of a channel (hereinafter, referred to as a “parasitic channel”) parasitically generated in a region adjacent to the region 05. Hereinafter, the parasitic channel will be described.

FIGS. 24A and 24B (solid lines) show a gate electrode 306, a gate insulating film 305, a Si cap layer 304, a SiGe channel layer 303, a Si buffer layer 302, and a Si substrate of a p-channel field effect transistor. 301
FIG. 3 is a band diagram showing an energy band when a small voltage and a large voltage are applied in a cross-section taken along a line. In this example, the SiG
The e-channel layer 303 has a Ge content (hereinafter simply referred to as Ge
At the boundary with the Si buffer layer 302).
%, The Ge composition is almost continuously inclined so as to be 30% at the boundary with the Si cap layer 304. FIG.
As shown in (a), when the negative voltage Vg applied to the gate electrode 306 is small (when the absolute value is small), a remarkable parasitic channel does not appear, but the negative voltage applied to the gate electrode 306 is small. It can be seen that when the voltage is increased (when the absolute value is increased), the energy level at the upper end of the Si cap layer 304 is increased, so that a noticeable parasitic channel appears.

FIGS. 24A and 24B show the band structure in the case where the Ge composition is a constant value of 15% by a dotted line. The band structure of the solid line is the G of the SiGe channel layer.
This is a structure in which the e content is increased almost linearly from 0% to 30%. Compared with the dotted line structure, the upper end of the valence band has a steep slope, that is, SiGe.
The band discontinuity (ΔEv) at the interface between the channel layer 303 and the silicon cap layer 304 is large.

FIGS. 25 (a) and 25 (b) show, respectively,
It is a figure which shows the profile of Ge composition, and the profile of the amount of distortion. Since the overall strain amount is the same between the gradient composition shown by the solid line and the constant composition shown by the dotted line, it can be said that the thermal stability is equivalent.

As shown in FIGS. 24 (a) and 24 (b), in a weakly overdriven state, the energy level at the upper end of the valence band becomes maximum in the SiGe layer 303, so that almost all holes are formed of SiGe. Channels present in layer 303 and contributing to conduction are formed in SiGe layer 303. Since this channel is formed in a portion that is deeper than the outermost surface of the entire semiconductor layer by the thickness of the silicon cap layer 304, it is called a buried channel. But,
When the overdrive becomes strong, the silicon cap layer 3
04 band edge profile steepened,
In addition to the Ge layer 303, holes also exist at the interface with the gate insulating film 305 in the silicon cap layer 304. The channel formed in the silicon cap layer 304 is called a parasitic channel.

As described above, holes in the buried channel formed in the SiGe layer 303 have a higher mobility than Si due to the effect of distortion. On the other hand, holes in the parasitic channel are scattered due to roughness at the interface between the gate insulating film 305 and the silicon cap layer 304, and thus travel with a lower mobility than the mobility in the buried channel. Therefore, when the buried channel is dominant, the hole mobility is large as a whole, and the hole can operate at a higher speed than the p-MOSFET made of Si, and the current driving force can be increased. However, when the parasitic channel becomes dominant, the mobility of holes as a whole decreases, hindering high-speed operation and reducing the current driving force.

FIG. 26 is a diagram showing the gate bias dependence of the sheet carrier concentration (hole sheet concentration) of holes in the buried channel and the parasitic channel. The curve shown by the dotted line in FIG. 26 shows the case where the Ge composition is constant at 15%, and the curve shown by the solid line shows the case where the Ge composition changes linearly from 0% to 30%. As can be inferred from FIGS. 24A and 24B, by changing the Ge composition linearly from 0% to 30%, the band discontinuity at the interface between the SiGe channel layer 303 and the silicon cap layer 304 ( Δ
In the case where Ev) is increased, the hole sheet concentration in the buried channel is increased and the hole sheet concentration in the parasitic channel is increased while having the same thermal stability as compared with the case where the Ge composition is constant. It can be kept small.
As a result, high-speed operation and high current driving force can be maintained over a wider range of gate voltage. As described above, the conventional example of the field effect transistor in which the parasitic channel is suppressed by inclining the Ge composition is, for example,
Literature (SVVandebroek et al., IEEE Transactions on E
lectron Devices, vol. 41, p. 90 (1994)) and U.S. Pat. No. 5,821,577.

Further, conventionally, a modulation doping structure has been used as another means for increasing the current driving force of a field effect transistor.

FIG. 27 is a diagram showing an example of a profile of a Ge composition and a p-type impurity concentration (here, boron) when a modulation doping structure is adopted. A so-called δ-doped layer is provided near the channel 303 in the silicon buffer layer 302 by doping impurities for supplying carriers at a high concentration. This δ-doped layer may be provided in the silicon cap layer 304. 27, the Ge composition of the channel layer 303, the size of the transistor, etc.
Other conditions are the same as those in FIG. As described above, by providing the δ-doped layer separately from the channel layer and spatially separating the δ-doped layer, the scattering of impurities in the channel is suppressed while realizing a high current driving force, and the carrier traveling through the channel is reduced. The mobility can be kept high. A field effect transistor having such a structure and using SiGe as a hole channel is, for example, SPVoinig.
escu et al., IEDM Tech. Dig., p.369 (1994).

FIG. 28 shows a drain voltage-drain current characteristic (V.sub.V) of a transistor whose Ge and boron profiles are as shown in FIGS.
(d-Id characteristic). As can be seen by comparing the solid curve and the broken curve, a higher current driving force can be obtained by employing the modulation doping structure shown in FIG.

[0015]

However, the above-mentioned conventional field-effect transistor using a SiGe layer as a channel has the following problems. These are the problem of thermal stability due to strain and the problem of impurity diffusion in modulation doping, which will be described below.

In order to suppress the parasitic channel, as described above, the band offset value ΔEv at the interface between the SiGe channel layer and the silicon cap layer may be increased. For this purpose, the Ge composition may be increased. Then, the SiGe channel layer 303 receives a larger compressive strain. If the distortion is too large, the crystal cannot maintain the distorted state, and causes a crystal defect to return to the original lattice constant. This is called lattice relaxation. When the lattice relaxation of the crystal occurs, a localized level is generated due to a crystal defect, which causes a decrease in the leakage current and the mobility of holes, and deteriorates the device characteristics.

The likelihood of lattice relaxation also depends on the thickness of the thin film crystal. That is, there is an upper limit to the film thickness at which crystal growth can be performed in a state containing strain (without causing lattice relaxation), and this upper limit film thickness is called a critical film thickness. FIG.
FIG. 3 is a diagram showing a relationship between a Ge composition of strained SiGe on a Si substrate and a critical film thickness. As shown in FIG. 29, the critical film thickness sharply decreases with an increase in the Ge composition, that is, with an increase in the amount of strain. However, a film thickness of about ten and several nm or more is practically required for the SiGe channel layer. Considering this, it is necessary to suppress the distortion amount to about 0.5 to 0.8% if possible. This means that the Ge composition must be suppressed to about 15% or less in order to obtain a transistor having practically necessary thermal stability, and the Ge composition (15%) shown in the conventional example is less than this. Almost corresponds to the upper limit. On the other hand, even in the conventional example having a gradient composition in which the Ge composition changes from 0% to 30%, the average Ge composition is 15%.
Therefore, this value is equal to the upper limit value when the Ge composition is fixed.

From the above, it can be seen that the Ge composition should be increased in order to suppress the parasitic channel.
However, at this time, since the amount of distortion also increases, lattice relaxation is likely to occur. In such a structure, lattice relaxation is likely to occur even by heat treatment in a transistor manufacturing process. That is, the thermal stability is poor. Higher temperature heat treatment is required to form a good-quality gate insulating film and to sufficiently activate impurities in the source region and the drain region. However, as described above, the thermal stability of the SiGe layer is poor. In this state, sufficient heat treatment cannot be performed, and sufficient performance of the transistor cannot be obtained.

In the modulation doping structure shown in FIG. 27, it is advantageous to bring the δ-doped layer as close as possible to the channel layer in order to obtain a large current driving force. As shown in FIG. 27, the impurity in the δ-doped layer is changed to the δ-doped layer (peak position).
From the channel layer 303. In that case, impurity scattering with respect to carriers occurs in the channel layer 303, so that the carrier mobility is reduced and the driving current is reduced.

An object of the present invention is to achieve both suppression of a parasitic channel and excellent thermal stability and suppression of diffusion of impurities into a channel layer in a field effect transistor having a SiGe channel layer. .

[0021]

A first p-channel field-effect transistor according to the present invention is a field-effect transistor formed on a semiconductor substrate, the first p-channel field-effect transistor comprising a first semiconductor layer made of silicon; Provided on the semiconductor layer of
a second semiconductor layer having a composition represented by i _1-x Ge _x (0 <x <1); a third semiconductor layer made of silicon provided on the second semiconductor layer; 3, a gate insulating film provided on the semiconductor layer, and a gate electrode provided on the gate insulating film, wherein the second semiconductor layer is provided when a negative voltage is applied to the gate electrode. The hole becomes a p-channel region where the hole travels, and the Ge
C is contained in a region including the maximum value of the content ratio of C.

Thus, since C is contained in the second semiconductor layer, diffusion of impurities in the second semiconductor layer to be a SiGe channel region is suppressed. Therefore,
Impurity scattering of carriers can be suppressed, so that a transistor having high carrier mobility and large driving current can be obtained. The distortion can be reduced by adjusting the content of C. In this case, too, the band at the upper end of the valence band formed between the first semiconductor layer and the second semiconductor layer. The value of the offset hardly changes. Therefore, while maintaining the same threshold value as that having the same Ge composition without containing C, distortion can be reduced and thermal stability can be improved. That is, since the carrier mobility does not deteriorate due to lattice relaxation, a high current driving force can be realized. In the region where the second semiconductor layer includes the maximum value of the Ge content,
, It is possible to reliably prevent diffusion of impurities into a portion where carriers are actually confined.

The second semiconductor layer may have a lattice strain of 0.5% or less in at least one of a region in contact with the first semiconductor layer and a region in contact with the third semiconductor layer. By being configured in
The thickness of the channel layer can be sufficiently ensured within a range in which lattice relaxation does not occur.

It is more preferable that the second semiconductor layer is configured to lattice-match with the first semiconductor layer and the third semiconductor layer in all regions.

[0025] The semiconductor device further includes a δ-doped layer provided in a portion of the first semiconductor layer adjacent to the second semiconductor layer and containing a high-concentration p-type impurity. While suppressing impurity scattering in the channel region.

In this case, it is preferable that at least a part of the second semiconductor layer containing C is adjacent to the first semiconductor layer.

Further, the second semiconductor layer of the third semiconductor layer
And a δ-doped layer provided at a portion adjacent to the semiconductor layer and containing a high concentration of p-type impurities.

In that case, C in the second semiconductor layer
Is included in the at least a part of the third region.
Is preferably adjacent to the semiconductor layer.

A second p-channel field-effect transistor of the present invention is a field-effect transistor formed on a semiconductor substrate, comprising: a first semiconductor layer made of silicon;
Provided on the first semiconductor layer, Si _1-x Ge _x (0
A second semiconductor layer having a composition represented by <x <1);
A third semiconductor layer made of silicon provided on the second semiconductor layer, a gate insulating film provided on the third semiconductor layer, and a gate electrode provided on the gate insulating film. The second semiconductor layer is a p-channel region where holes travel when a negative voltage is applied to the gate electrode, and at least a part of the third semiconductor layer has C Contains.

Thus, since C is contained in the second semiconductor layer, the diffusion of impurities in the second semiconductor layer to be the SiGe channel region is suppressed. Therefore,
Impurity scattering to carriers can be suppressed, and a transistor having high carrier mobility and high driving current can be obtained. The distortion can be reduced by adjusting the content of C. In this case, too, the band at the upper end of the valence band formed between the first semiconductor layer and the second semiconductor layer. The value of the offset hardly changes. Therefore, while maintaining the same threshold value as that having the same Ge composition without containing C, distortion can be reduced and thermal stability can be improved. That is, since the carrier mobility does not deteriorate due to lattice relaxation, a high current driving force can be realized. Further, since at least a part of the region in the third semiconductor layer contains C, diffusion of impurities into the gate insulating film can be suppressed, which may be caused by intrusion of impurities into the gate insulating film. It is possible to avoid occurrence of problems such as variation in threshold voltage.

Since at least a part of the region containing C in the third semiconductor layer is adjacent to the second semiconductor layer, the region in the third semiconductor layer can be more effectively used. Diffusion of impurities can be suppressed.

In the second semiconductor layer, at least a part of the region where C is contained is one part from the gate insulating film.
The distance is preferably at least 2 nm, more preferably at least 2 nm from the gate insulating film. This is to prevent C from entering the gate insulating film to prevent the quality of the gate insulating film from deteriorating and reducing the reliability of the MOS transistor.

A third p-channel field effect transistor of the present invention is a field effect transistor formed on a semiconductor substrate, comprising: a first semiconductor layer made of silicon;
Provided on the first semiconductor layer, Si _1-x Ge _x (0
A second semiconductor layer having a composition represented by <x <1);
A third semiconductor layer made of silicon provided on the second semiconductor layer, a gate insulating film provided on the third semiconductor layer, and a gate electrode provided on the gate insulating film. The second semiconductor layer becomes a p-channel region where holes travel when a negative voltage is applied to the gate electrode, and the Ge content in the second semiconductor layer exceeds 30%. ing.

Thus, since C is contained in the second semiconductor layer, the diffusion of impurities in the second semiconductor layer to be the SiGe channel region is suppressed. Therefore,
Impurity scattering to carriers can be suppressed, and a transistor having high carrier mobility and high driving current can be obtained. The distortion can be reduced by adjusting the content of C. In this case, too, the band at the upper end of the valence band formed between the first semiconductor layer and the second semiconductor layer. The value of the offset hardly changes. Therefore, while maintaining the same threshold value as that having the same Ge composition without containing C, distortion can be reduced and thermal stability can be improved. That is, since the carrier mobility does not deteriorate due to lattice relaxation, a high current driving force can be realized. Since the Ge content in the second semiconductor layer exceeds 30%, a steep impurity concentration profile can be realized while increasing the band offset as much as possible.

The semiconductor substrate in each of the first to third p-channel field-effect transistors is an SOI substrate having a semiconductor layer provided on an insulating layer, and the first semiconductor layer is provided on the SOI substrate. A depletion layer configured to reach the lower end of the first semiconductor layer when a negative voltage is applied to the gate electrode; Can be suppressed.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) First, a first embodiment of the present invention will be described. FIG. 1 is a sectional view of a p-type field effect transistor in which a channel layer is formed of a strained SiGe layer containing C. A silicon buffer layer 10 is formed on an n-type silicon substrate 101 by UHV-CVD.
2. Channel layer 103 and silicon cap layer 104
Are sequentially grown epitaxially. Channel layer 10
3 is composed of a SiGe layer containing C and having a strain. The thicknesses of the silicon buffer layer 102, the channel layer 103, and the silicon cap layer 104 are 10 nm, 10 nm, and 5 nm, respectively, and a process for doping impurities in each layer is not performed. Also, S
On the i-cap layer 104, a gate insulating film 105 made of a silicon oxide film and a gate electrode 106 made of a polysilicon film are provided. In addition, the Si buffer layer 1
02, SiGe channel layer 103 and Si cap layer 1
In the wide region extending over the region 04, regions located on both sides of the gate electrode 106 include a source region 107 and a drain region 108 containing a high-concentration p-type impurity (for example, boron).
Are formed. A source electrode 109 is provided on the source region 107, and a drain electrode 110 is provided on the drain region 108. Note that MO
The channel length and channel width of the S-type field effect transistor are, for example, 0.5 μm and 10 μm.

FIGS. 2 (a), (b), (c) and (d)
In order, the composition profiles of Ge and C in the depth direction along the cross section taken along the line AA ′ of FIG. 1, the energy level Ev (based on the upper end of Si) and the strain amount profile at the upper end of the valence band. FIG. FIG.
As shown in (a) and (b), the Ge composition is changed from the end on the silicon buffer layer 102 side to the silicon cap layer 104.
Linearly from 0% to 50% towards the side edge,
C is selectively 0.1% in the region where the Ge composition is 40% to 50%.
Contains 5%. 2 (c) and 2 (d), a solid line indicates a transistor according to the present embodiment, and a dotted line indicates a conventional field effect transistor having a channel of SiGe having a gradient composition not including C. In the case where only the solid line is shown, the present embodiment and the conventional example are completely the same, or even if there is a slight difference, little difference appears on this scale.

FIG. 3 shows a strained Si _1-xy Ge _x C _y (0 ≦ x ≦ 1, 0 <) formed on a silicon substrate.
FIG. 9 is a diagram showing the relationship between the Ge composition and the C composition, the amount of strain, and Ev for Y ≦ 1). The compositions of Ge and C at which the strain amount and Ev are equal are indicated by a dotted line and an alternate long and short dash line, respectively. In FIG. 3, changes in the Ge and C compositions in the channel layer are indicated by arrows. The starting point of the arrow represents the composition at the end of the channel layer on the silicon buffer layer side, and the ending point of the arrow represents the composition at the end of the channel layer on the silicon cap layer side. Along the line. The arrows indicate those according to the present embodiment, and the arrows indicate conventional field effect transistors having a channel of SiGe having a gradient composition not containing C.

As can be seen from FIGS. 2 and 3, by containing 0.5% of C in a region where the Ge composition is 40% to 50% (that is, a region exceeding 30%), the amounts of strain are 12% and 12%, respectively. It can be seen that although it can be reduced by about 10%, Ev hardly changes. (Figure 2
At the scale of (c), the difference in Ev is invisible. That is, it is possible to increase the drive current while securing a large critical film thickness of the SiGe channel layer. In particular, in a conventional SiGe-pMOSFET, the Ge level of the SiGe layer is at a practical level aside from a research level.
When the content exceeds 30%, the film thickness necessary for obtaining a sufficient drive current is secured within the range of the critical film thickness.
Since it is difficult to obtain thermal stability such that lattice relaxation does not occur during the process, it has not yet existed. On the other hand, in the present embodiment, C
Is contained only in a small amount, only the lattice strain can be reduced while Ev is secured. Therefore, even if the Ge content in the SiGe layer (strictly speaking, the SiGeC layer) is 30% or more, a sufficient driving current and Great thermal stability can be ensured.

Next, regarding the effect of suppressing the parasitic channel,
A description will be given in comparison with a conventional case not including C. FIG.
(A) and (b) show the band edges of the conduction band and the valence band in the cross section taken along line AA ′ in FIG. 1 when a negative gate voltage Vg is applied to the gate electrode 106 of the p-MOSFET. It is a figure showing a profile. FIG. 4A shows a state in which the gate voltage is weakly overdriven from the threshold voltage, and FIG. 4B shows a state in which the gate voltage is strongly overdriven from the threshold voltage. In the figure, the area indicated by the reference numeral 101 and the like corresponds to the area indicated by the reference numeral in FIG. Since the profile of the upper end of the valence band in the channel layer is hardly different between the present embodiment and the conventional one not including C, the entire profile in FIGS. 4A and 4B is also the same. Therefore, the parasitic channel can be suppressed as well as the conventional SiGe gradient composition.

FIG. 5 is a diagram showing the gate voltage dependence of the sheet carrier concentration (hole sheet concentration) of the buried channel 103 and the parasitic channel 104. As described above, the present embodiment and the conventional SiGe gradient composition are equivalent with respect to the suppression of the parasitic channel.

FIG. 6 is a diagram showing Vd-Id characteristics of the field effect transistor of the present invention containing C in the SiGe channel layer and the conventional field effect transistor not containing C. As shown in FIG. 6, in the field-effect transistor of the present invention, by including C in a region having a large Ge composition, a larger drain current is obtained as compared with a conventional field-effect transistor.

That is, according to the present invention, the channel layer 1
By including C in 03, the strain of the channel layer 103 is reduced and the thermal stability is greatly improved, but the value of the band offset with respect to the cap layer is the same as the Ge composition without including C. Since this is not different from the above, it is possible to suppress lattice relaxation while maintaining a low threshold value. As described above, since the carrier mobility is not deteriorated due to the lattice relaxation of the crystal of the SiGe channel layer, a higher current driving force can be realized as compared with the conventional Ge-graded composition not containing C. It has practical advantages.

(Second Embodiment) Next, a second embodiment of the field effect transistor according to the present invention will be described. In order to explain the superiority of the field effect transistor (SiGeC-pMOSFET) in which the channel layer is made of SiGeC according to the present invention, a conventional field effect transistor in which the channel layer is made of SiGe having a graded composition (not including C) ( (SiGe-pMOSFET).

Also in this embodiment, SiGeC-pM
The structure of the OSFET is such that the channel layer entirely contains C
The structure is basically the same as the structure shown in FIG. 1 described in the first embodiment except that the structure is made of iGeC.
Description is omitted. The thicknesses of the silicon buffer layer 102, the channel layer 103, and the silicon cap layer 104 are 10 nm, 10 nm, and 5 nm, respectively, and no impurity doping is performed. The channel length and channel width of the transistor are 0.5 μm and 10 μm, respectively.

FIG. 7 shows the SiGeC-pMO of this embodiment.
SFET and first and second conventional SiGe-p
FIG. 3 is a diagram illustrating a method of adjusting a Ge composition and a C composition in a channel layer of a MOSFET. Arrow in FIG. 7,
, Are the SiGeC-pMOSFET of the present embodiment,
The Ge composition and the C composition in the channel layer of the first and second conventional SiGe-pMOSFETs are shown.

That is, the SiGeC-pM according to the present invention
In the OSFET (arrow), the channel layer 103 is silicon that does not contain Ge and C at the end on the silicon buffer layer 102 side, and the composition of Ge and C at the end on the silicon cap layer 104 side is 45% and 3.8%. The Ge composition and the C composition change linearly from the start point to the end point of the arrow. The band offset at the end of the arrow is about 250 meV, and the amount of distortion is about 0.5% (compression distortion).

First Conventional SiGe-pMOSFET
In (arrow), the channel layer 103 is silicon that does not contain Ge and C at the end on the silicon buffer layer 102 side, and the Ge composition at the end on the silicon cap layer 104 side is 40%. The Ge composition changes linearly from the start point to the end point of the arrow. Ev at the end point of the arrow is the SiGeC-pMOSFE of the present embodiment.
As in the case of T, the strain is about 250 meV, and the amount of strain is about 1.6% (compression strain), which is three times or more that of the SiGeC-pMOSFET of the present embodiment.

Second Conventional SiGe-pMOSFET
In (arrow), the channel layer 103 is silicon that does not contain Ge and C at the end on the silicon buffer layer 102 side, and the Ge composition at the end on the silicon cap layer 104 side is 12%. The Ge composition changes linearly from the start point to the end point of the arrow. Ev at the end of the arrow is SiGeC-pM
It is about 80 meV, which is one third that of the OSFET, and the amount of strain is about 0.5% (compressive strain) as in the case of the SiGeC-pMOSFET.

FIGS. 8 (a), (b), (c) and (d)
In this order, the SiGeC-pMOSFE of this embodiment is
T and Ge composition of conventional SiGe-pMOSFET, C
It is a figure which shows the profile of composition, Ev, and the amount of distortion. The regions indicated by the reference numerals in the drawing correspond to the regions indicated by the reference numerals in FIG. 1, and the circled numbers in the drawing correspond to the numbers indicated by the arrows in FIG.

First, the SiGeC-pMOS of the present embodiment
FET (arrow) and first conventional SiGe-pMOSF
Compare ET (arrow).

Since the profile of Ev in the channel layer 103 is the same as that of the present invention and the first conventional one, the entire profile from the gate electrode to the Si substrate in the cross section taken along line AA ′ in FIG. Become. Therefore,
As described in the first embodiment, the suppression of the parasitic channel is the same in the SiGeC-pMOSFET of the present embodiment and the first conventional SiGe-pMOSFET.

FIG. 9 shows the SiGeC-pMO of this embodiment.
FIG. 4 is a diagram illustrating a Vd-Id characteristic of an SFET. FIG. 8 (d)
As shown in the figure, the SiGeC-pMOS according to the present embodiment
FET (arrow) shows the first conventional SiGe-pMOS
Compared with the FET (arrow), the amount of distortion is one third or less, and the thermal stability is greatly improved. Therefore, the lattice relaxation of the crystal hardly occurs even by the heat treatment at a high temperature, so that the deterioration of the carrier mobility can be suppressed, and the high speed operation and the high current driving force can be realized. Since the heat treatment can be performed at a relatively high temperature, it is possible to form a high-quality gate insulating film 105 and to reduce a leak current in the gate insulating film 105.
07 and the drain region 108 can be sufficiently activated, so that the transistor can have high performance, such as low resistance.

As described above, the SiGeC according to the present embodiment is
-PMOSFET is the first conventional SiGe-pMOSF
Compared to ET, thermal stability can be greatly improved while maintaining the same effect on suppression of parasitic channels, and higher performance of the transistor can be realized. are doing.

Next, the SiGeC-pM according to the present embodiment
OSFET (arrow) and second conventional SiGe-pMO
Compare SFETs (arrows).

FIG. 10 is a diagram showing the gate voltage dependence of the sheet carrier concentration (hole sheet concentration) of the buried channel 103 and the parasitic channel 104. FIG.
As can be seen from (c), Ev in the present embodiment in the channel layer 103 is three times or more as large as that in the second conventional one. Therefore, the SiGeC-
In the case of a pMOSFET, the holes in the buried channel
Therefore, it is possible to increase the gate concentration and to reduce the hole sheet concentration in the parasitic channel. As a result, a high-speed operation and a high current driving force can be maintained over a wider range of gate voltage, which has practical advantages.

Further, as shown in FIG. 8D, the strain amount is the same between the SiGeC-pMOSFET (arrow) of the present embodiment and the second conventional SiGe-pMOSFET (arrow). Thermal stability can be considered almost equal.

As described above, the SiGeC-p of the present embodiment
The MOSFET is a second conventional SiGe-pMOSFE
Compared with T, the parasitic channel can be greatly suppressed while maintaining the same effect on thermal stability, and the performance of the transistor can be improved, which has a practical advantage. .

The following advantages are also obtained by forming the channel layer 103 of SiGeC. As the gate length of the field effect transistor becomes shorter, short channel effects such as a decrease in threshold voltage become more pronounced.
In order to suppress this short channel effect, finely controlling the implantation profile near the source and drain regions in two dimensions, such as LDD implantation and pocket implantation, is performed. However, if a high-temperature heat treatment for activating the impurities is performed after performing the fine profile control, the impurities are diffused and the two-dimensional profile is blurred, and the short channel effect is not sufficiently suppressed. Would. On the other hand, in the field-effect transistor of this embodiment, since C is contained in the channel layer, diffusion of impurities is suppressed, and a fine two-dimensional profile can be maintained even after the heat treatment at a high temperature. The channel effect can be sufficiently suppressed.

(Third Embodiment) A third embodiment of the field effect transistor according to the present invention will be described. In order to explain the superiority of the field effect transistor (SiGeC-pMOSFET) whose channel layer is made of SiGeC in this embodiment, the channel layer is made of (does not contain C).
A description will be given in comparison with a conventional field effect transistor (SiGe-pMOSFET) made of a gradient composition SiGe.

The SiGeC-pMOSFET of the present embodiment
Has a structure in which the channel layer entirely contains C and the SiG
The structure is basically the same as that of the first embodiment shown in FIG. 1 except that the structure is made of eC, and the description is omitted. Silicon buffer layer 102, channel layer 10
3. The thickness of each layer of the silicon cap layer 104 is 10 nm, 10 nm, and 5 nm, respectively, and no treatment for doping impurities into each layer is performed. The channel length and channel width of the transistor are each 0.5 μm,
10 μm.

FIG. 11 shows the SiGeC-pM of this embodiment.
FIG. 4 is a diagram showing profiles of Ge and C compositions in a channel layer of an OSFET and a conventional SiGe-pMOSFET. The arrows in FIG. 11 indicate the profiles of the Ge and C compositions in the channel layers of the present embodiment and the conventional pMOSFET.

That is, the SiGeC-pM of the present embodiment
In the OSFET (arrow), the channel layer 103 is silicon that does not contain Ge and C at the end on the silicon buffer layer 102 side, and the composition of Ge and C at the end on the silicon cap layer 104 side is 25% and 3%. The Ge composition and the C composition change linearly from the start point to the end point of the arrow.
Ev at the end of the arrow is about 140 meV. The channel layer 103 has a strain amount of 0% from the portion in contact with the silicon buffer layer 102 to the portion in contact with the silicon cap layer 104, and is lattice-matched to the silicon substrate 101. Even when the channel layer 103 has no strain, the hole in the SiGeC layer has a higher mobility than the hole in the Si layer due to the material properties of SiGeC, High-speed operation can be realized.

Further, a conventional SiGe-pMOSFET
In (arrow), the channel layer 103 is silicon that does not contain Ge and C at the end on the silicon buffer layer 102 side, and the Ge composition at the end on the silicon cap layer 104 side is 22%. The Ge composition changes linearly from the start point to the end point of the arrow. Ev at the end point of the arrow is about 140 meV, and the distortion amount is about 0.8% (compression distortion).

FIGS. 12 (a), (b), (c) and (d)
Are, in order, the SiGeC-pM of the third embodiment.
OSFET and conventional SiGe-pMOSFET Ge
It is a figure which shows the profile of composition, C composition, Ev, and the amount of distortion. The numbers in the figure correspond to the numbers of the arrows in FIG.

Since the profile of Ev in the channel layer 103 is the same as that of the present embodiment and that of the conventional example,
In FIG. 1, the entire profile from the gate electrode of the cross section indicated by AA 'to the Si substrate becomes the same. Therefore, as described in the first embodiment, with respect to the suppression of the parasitic channel, the SiGeC-pMOSFE of the present embodiment is used.
T (arrow) is equivalent to the conventional SiGe-pMOSFET (arrow).

FIG. 13 shows this embodiment and a conventional MOSFE.
FIG. 4 is a diagram showing Vd-Id characteristics of T. As shown in FIG. 12D, in the SiGeC-pMOSFET of this embodiment, the channel layer 103 is lattice-matched to the silicon substrate 101, and the distortion amount is 0% everywhere. Therefore, the thermal stability is dramatically improved to the same level as Si. Accordingly, since the lattice relaxation of the crystal does not occur even by the heat treatment at a high temperature, the carrier mobility does not deteriorate, which indicates that a high-speed operation and a high current driving force can be realized. Further, since the heat treatment at a high temperature becomes possible, it is possible to form a high-quality gate insulating film 105 and to reduce a leak current in the gate insulating film. By sufficiently activating the region 108, a high-performance transistor can be realized, for example, a low resistance can be realized.

As described above, the SiGeC according to the present embodiment is
Compared with the conventional SiGe-pMOSFET, the −pMOSFET can dramatically improve the thermal stability while maintaining the same effect on suppressing the parasitic channel,
Higher performance of the transistor can be realized, which has practical advantages.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described. Also in this embodiment, the structure of the field effect transistor is basically the same as the structure shown in FIG. 1 in the first embodiment. However, the present embodiment is characterized in that the channel layer has a modulation doping structure and the silicon buffer layer 102 contains a high concentration p-type impurity doped layer 8δ doped layer). . The thicknesses of the silicon buffer layer 102, the channel layer 103, and the silicon cap layer 104 are 10 nm, 10 nm, and 5 nm, respectively, and doping of impurities into the channel layer and the silicon cap layer is not performed. The channel length and channel width of the transistor are 0.5 μm and 10 μm, respectively.

FIG. 14 is a diagram showing profiles of the Ge composition and the C composition in the channel layer of the field-effect transistor of this embodiment. Arrows in FIG. 14 indicate changes in the Ge composition and C composition in the channel layer of the field-effect transistor of the present embodiment.

That is, the channel layer 103 of the field-effect transistor of this embodiment is
The Ge composition and the C composition at the end on the 02 side are 8
%, 0.9%. Further, as indicated by the arrow, the Ge composition in the channel layer linearly increases toward the silicon cap layer 104 side, and at a certain depth in the channel layer, the Ge composition becomes 20% and the C composition becomes 0%. 0.9%.
Further, in the channel layer, the silicon cap layer 1
The Ge composition and the C composition linearly increase again as approaching the 04 side, and at the end on the silicon cap layer 104 side, the Ge composition becomes 30% and the C composition becomes 3.4%.

FIGS. 15 (a), (b), (c), (d)
Are in sequence Ge along the section AA 'of FIG.
FIG. 3 is a diagram showing a composition, a C composition, a concentration of a p-type impurity (boron), and profiles of Ev and a strain amount. These profiles show the state after the transistor is manufactured. In the heat treatment in the manufacturing process, the diffusion of boron occurs. However, the diffusion of boron in the channel layer is prevented by C in the channel layer 103. You can see that.

As a result, in the field-effect transistor of this embodiment, high-speed operation can be realized while preventing deterioration of mobility due to scattering of impurities in the channel layer. This means that the high concentration p-type impurity doped layer can be brought as close as possible to the channel layer 103, so that a higher current driving force can be obtained in this embodiment.

Next, as shown in FIG. 15C, Ev in the channel layer 103 is the same as that of the silicon buffer layer 1.
02 monotonically increases from the end on the side of the silicon buffer layer 102 to the end on the side of the silicon buffer layer 102, and increases to about 45 meV at the end on the side of the silicon buffer layer 102.
It becomes about 165 meV at the end on the 04 side. Therefore, a sufficient band offset can be obtained at the end of the channel layer 103 on the silicon cap layer 104 side.
The formation of a parasitic channel can be reliably suppressed while keeping the threshold voltage small.

Next, as shown in FIG. 15D, the amount of strain in the channel layer 103 is set at 0.2% at the center of the channel layer 103 where the Ge composition is 20% and the C composition is 0.9%. 5%
And 0% (no distortion) at both the end on the silicon buffer layer 102 side and the end on the silicon cap layer 104 side. In the field-effect transistor of the present embodiment, the channel layer 103 is lattice-matched with the silicon layer at both the end on the silicon buffer layer 102 side and the end on the silicon cap layer 104 side, so that excellent heat dissipation is obtained. It has stable stability. Therefore, even when the heat treatment is performed at a high temperature, the crystal is not easily relaxed and the carrier mobility is not deteriorated, so that a field effect transistor having a high-speed operation and a high current driving force can be realized. Further, since heat treatment at a high temperature becomes possible, it is possible to form a high-quality gate insulating film 105 and to reduce a leak current in the gate insulating film.
07 and the drain region 108 can be sufficiently activated, so that the transistor can have high performance, such as low resistance.

FIG. 16 is a diagram showing Vd-Id characteristics in a SiGeC-pMOSFET with and without a p-type impurity doped layer (δ-doped layer) in a silicon buffer layer. As shown in the figure, the current driving force can be further increased by providing a δ-doping layer to form a modulation doping structure.

FIGS. 30A and 30B show SiGeC-p
FIG. 4 is a diagram showing a band structure when a gate bias is applied when a p-type impurity doped layer (δ-doped layer) is provided in a silicon buffer layer and a silicon cap layer, respectively, in a MOSFET. As shown in the figure, in particular, by providing the δ-doped layer in the silicon cap layer, a sharp depression is formed in the band offset portion, so that the function of confining carriers can be further enhanced.

As described above, the field effect transistor according to the present embodiment can not only improve the thermal stability while reliably suppressing the formation of the parasitic channel, but also can improve the thermal stability.
Further, the transistor can be improved in performance, for example, the current driving force can be increased by the modulation doping structure, and it has a practical advantage.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described. Also in this embodiment, the structure of the field effect transistor is basically the same as the structure described in the first embodiment with reference to FIG. However,
The present embodiment is characterized in that the transistor has a modulation doping structure, and that the silicon cap layer 104 includes a high concentration p-type impurity doping layer (δ-doped layer). The thickness of each of the silicon buffer layer 102, the channel layer 103, and the silicon cap layer 104 is 10 n.
m, 10 nm, and 5 nm, and doping of impurities into the channel layer and the silicon buffer layer is not performed.
The channel length and channel width of the transistor are 0.5 μm and 10 μm, respectively.

Also in this embodiment, the profiles of the Ge composition and the C composition in the channel layer of the field-effect transistor are the same as those in the fourth embodiment indicated by the arrow in FIG.

FIGS. 17A, 17B, 17C, and 17D.
Are in sequence Ge along the section AA 'of FIG.
FIG. 3 is a diagram showing a composition, a C composition, a concentration of a p-type impurity (boron), and profiles of Ev and a strain amount. These profiles are shown after the transistor is manufactured, and FIG.
As shown in FIG. 7B, the diffusion of boron occurs due to the heat treatment in the manufacturing process.
It can be seen that C in the figure prevents the diffusion of boron in the channel layer.

As a result, in the field-effect transistor of the present embodiment, high-speed operation can be realized while preventing mobility degradation due to impurity scattering in the channel layer. This means that a high concentration p-type impurity doped layer (δ-doped layer) can be made as close as possible to the channel layer 103, and a higher current driving force can be obtained.

Next, as shown in FIGS. 17C and 17D, in the present embodiment, similarly to the fourth embodiment, the end of the channel layer 103 on the silicon cap layer 104 side is sufficiently large. Because of having Ev, a large band offset can be secured, and a parasitic channel can be sufficiently suppressed. In addition, channel layer 1
The strain amount is 0% at both the end of the silicon buffer layer 102 and the end of the silicon cap layer 104 on the side of the silicon buffer layer 102.
Therefore, similarly to the fourth embodiment, the MOSFET of the present embodiment also has excellent thermal stability.

FIG. 18 is a diagram showing Vd-Id characteristics in a SiGeC-pMOSFET with and without a p-type impurity doped layer (δ-doped layer) in a silicon cap layer. As shown in the figure, the current driving force can be further increased by providing a p-type impurity doped layer (δ-doped layer) to form a modulation doped structure.

Here, as shown by the broken line in FIG. 17B, at least a p-type impurity-doped layer (δ-doped layer) doped with a high-concentration p-type impurity (for example, boron) in the silicon cap layer 104. By forming a region including a part thereof with a carbon-containing layer containing carbon (for example, 0.3%), diffusion of a p-type impurity (for example, boron) into a channel region and a gate oxide film can be suppressed. . Thus, it is possible to suppress the occurrence of variations in the threshold voltage of the transistor due to the intrusion of boron or the like into the gate oxide film. The range of this carbon-containing layer is:
It is preferably at least 1 nm from the gate oxide film, more preferably at least 2 nm. This is to prevent C from entering the gate oxide film to prevent the quality of the gate insulating film from being deteriorated and the reliability of the MOS transistor from being lowered.

As described above, according to the field effect transistor of this embodiment, not only the thermal stability can be improved while the formation of the parasitic channel is reliably suppressed, but also the current The transistor can have higher performance, such as higher driving force, and has practical advantages.

(Sixth Embodiment) Next, in this embodiment, a SiG layer formed on an SOI substrate and having a strained channel layer is used.
p-type field-effect transistor (SiGeC)
-PMOSFET) will be described.

FIG. 19 shows SiGeC in this embodiment.
It is sectional drawing of -pMOSFET. Silicon substrate 21
1. Surface silicon layer 2 of SOI substrate 201 composed of buried oxide film 212 and surface silicon layer 213
A silicon buffer layer 202, a channel layer 203, and a silicon cap layer 204 are sequentially epitaxially grown on the substrate 13 by UHV-CVD. The channel layer 203 is made of SiGeC. The thickness of the surface silicon layer 213 on the buried oxide film 212 is 3
When a voltage is applied, the entire active region becomes a depletion layer, and operates as a so-called fully depleted field-effect transistor.

Silicon buffer layer 202, channel layer 2
03, the thickness of the silicon cap layer 204 is 1
The thicknesses are 0 nm, 10 nm, and 5 nm, and no treatment is performed for doping each layer with impurities. In addition, Si
On the cap layer 204, a gate insulating film 205 made of a silicon oxide film and a gate electrode 206 made of a polysilicon film are provided. Also, the Si buffer layer 20
2, SiGe channel layer 203 and Si cap layer 20
4, a region located on both sides of the gate electrode 206 includes a source region 207 and a drain region 208 containing a high-concentration p-type impurity (for example, boron).
Are formed. A source electrode 209 is provided on the source region 207, and a drain electrode 210 is provided on the drain region 208. Note that MO
The channel length and channel width of the S-type field effect transistor are, for example, 0.5 μm and 10 μm.

The profiles of the Ge and C compositions in the channel layer of the field-effect transistor of this embodiment are the same as those in the second embodiment indicated by the arrows in FIG. That is, the SiGeC-
In the pMOSFET, the channel layer 203 is made of silicon that does not contain Ge and C at the end on the silicon buffer layer 202 side, and the silicon cap layer 20 is formed.
The Ge composition and the C composition at the four end portions are 45% and 3.8%, respectively. The Ge composition and the C composition between the start point and the end point of the arrow in FIG. 7 change linearly. The band offset at the end of the arrow is about 250 meV, and the amount of distortion is about 0.5% (compression distortion).

FIGS. 20A and 20B show SiGeC-pMOSFETs according to the present embodiment and the second embodiment.
FIG. 9 is a diagram showing a band edge profile of a conduction band and a band edge of a valence band in a cross section taken along line AA ′ when a negative gate voltage Vg is applied to the gate electrode 206 of FIG.

As shown in FIG. 20A, in the SiGeC-pMOSFET according to the present embodiment, since the surface silicon layer 213 is completely depleted, the gate voltage V
Part of g (Vg, box) is also applied to the buried oxide film 212. Therefore, when the same gate voltage Vg is applied to the gate electrode 206, the voltage applied to the silicon cap layer 204 is the same as the voltage applied to the SiGeC-pM described in the first embodiment.
It is smaller than the OSFET (FIG. 20B). Therefore, SiGeC-pMO on a fully depleted SOI substrate
In the SFET, the bending of the band near the silicon cap layer 204 becomes gentle. At this time, as is apparent from FIG. 20A, the formation of the parasitic channel can be more strongly suppressed than in the second embodiment.

FIG. 21 shows a buried channel 203 and a parasitic channel 204 in the MOSFET of this embodiment.
FIG. 9 is a diagram showing the gate voltage dependence of each sheet carrier concentration.

As described above, S in the present embodiment is
Since the surface silicon layer of the SOI substrate is completely depleted, the SiGeC-pMOSFET on the OI substrate has a higher parasitic effect than the SiGeC-pMOSFET on the normal silicon substrate having the same gradient composition (not the SOI substrate). Channel formation can be more strongly suppressed, and it has a practical advantage.

Although the gate insulating film is an oxide film in all the embodiments described above, the same effect can be exerted by the present invention even if the gate insulating film is another insulating film such as a nitride film.

[0096]

According to the present invention, the channel layer is made of C-containing SiGe (or SiGeC).
While maintaining sufficient thermal stability by suppressing the amount of strain in the entire channel layer, it is possible to strongly confine the hole in the buried channel and strongly suppress the parasitic channel, thereby exhibiting practical advantages. Can be. Further, by the effect of adding C, a high current driving force can be realized by suppressing the diffusion of impurities into the channel layer in the modulated doping structure. Further, by forming the transistor of this embodiment on an SOI substrate, the effect of suppressing the parasitic channel can be further enhanced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a p-type field-effect transistor in which a channel layer is formed of a strained SiGe layer containing C.

2 (a), (b), (c), and (d) are, respectively, a composition profile of Ge and C in a depth direction along a cross section taken along line AA ′ of FIG. It is a figure which shows the energy level Ev (based on the upper end of Si) of the band upper end, and the profile of the amount of distortion.

FIG. 3 shows a strained Si formed on a silicon substrate.
_{For 1-xy} Ge _x C _y (0 ≦ x ≦ 1, 0 <Y ≦ 1),
It is a figure which shows the relationship between Ge composition, C composition, the amount of distortion, and Ev.

FIGS. 4A and 4B are a conduction band and a valence band in a cross section taken along line AA ′ of FIG. 1 when a negative gate voltage Vg is applied to the gate electrode 106 of the p-MOSFET. FIG. 6 is a diagram showing a profile of a band edge of the present invention.

FIG. 5 is a diagram showing the gate voltage dependence of the sheet carrier concentration (hole sheet concentration) of the buried channel and the parasitic channel.

FIG. 6 is a diagram showing Vd-Id characteristics of a field effect transistor of the present invention containing C in a SiGe channel layer and a conventional field effect transistor not containing C;

FIG. 7 shows a SiGeC-pMOSFE according to a second embodiment.
T, and first and second conventional SiGe-pMOS
FIG. 4 is a diagram showing changes in Ge composition and C composition in a channel layer of the FET.

FIGS. 8 (a), (b), (c), and (d) respectively show the Ge composition, C composition, and Si composition of the SiGe-pMOSFET of the present embodiment and the first and second conventional SiGe-pMOSFETs, respectively. It is a figure which shows the profile of Ev and distortion amount.

FIG. 9 shows a SiGeC-pMO according to a second embodiment of the present invention.
FIG. 4 is a diagram illustrating a Vd-Id characteristic of an SFET.

FIG. 10 is a diagram showing the gate voltage dependence of the buried channel and parasitic channel sheet carrier concentration of the second embodiment.

FIG. 11 shows a SiGeC-pMOSFE according to a third embodiment.
It is a figure which shows the profile of Ge composition and C composition in T and the channel layer of the conventional SiGe-pMOSFET.

FIGS. 12 (a), (b), (c), and (d) show the SiGeC-pMOSFET of the third embodiment, respectively.
FIG. 6 is a diagram showing profiles of Ge composition, C composition, Ev, and strain amount of a conventional SiGe-pMOSFET.

FIG. 13 shows Vd of the third embodiment and a conventional MOSFET.
It is a figure which shows -Id characteristic.

FIG. 14 is a diagram illustrating profiles of a Ge composition and a C composition in a channel layer of the field-effect transistors according to the fourth and fifth embodiments.

FIGS. 15 (a), (b), (c), and (d) show a Ge composition, a C composition, and a p-type, respectively, taken along line AA ′ of FIG. 1 in the fourth embodiment. FIG. 3 is a diagram showing the concentration of impurities (boron), and profiles of Ev and the amount of distortion.

FIG. 16 is a diagram showing Vd-Id characteristics in a SiGeC-pMOSFET with and without a p-type impurity doped layer in a silicon buffer layer.

17 (a), (b), (c), and (d) show a Ge composition, a C composition, and a p-type, respectively, taken along line AA ′ of FIG. 1 in the fifth embodiment. FIG. 3 is a diagram showing the concentration of impurities (boron), and profiles of Ev and the amount of distortion.

FIG. 18 shows a SiGeC-pMOSFE according to a fifth embodiment.
FIG. 9 is a diagram showing Vd-Id characteristics in T with and without a p-type impurity doped layer in the silicon cap layer.

FIG. 19 shows a SiGeC-pMO according to the sixth embodiment.
It is sectional drawing of SFET.

FIGS. 20 (a) and (b) are cross-sectional views taken along line AA ′ when a negative gate voltage Vg is applied to the gate electrodes of the SiGeC-pMOSFETs of the sixth and second embodiments. It is a figure which shows the profile of the band edge of a conduction band and a valence band, respectively.

FIG. 21 is a diagram showing the gate voltage dependence of the sheet carrier concentration of each of the buried channel and the parasitic channel in the MOSFET according to the sixth embodiment.

FIG. 22 is a cross-sectional view illustrating an example of a conventional p-channel field effect transistor (p-MOSFET).

FIGS. 23 (a) and (b) are diagrams showing a difference in lattice constant between a SiGe single crystal and a Si single crystal, and FIG.
FIG. 4 is a cross-sectional view showing a state when an iGe layer is epitaxially grown.

FIGS. 24A and 24B are band diagrams showing energy bands when a small voltage and a large voltage are applied in a vertical section of a conventional p-channel field effect transistor.

FIGS. 25A and 25B respectively show a conventional p
A profile of the Ge composition of the channel MOSFET;
It is a figure which shows the profile of the amount of distortion.

FIG. 26 is a diagram showing gate bias dependence of sheet carrier concentration of holes in a buried channel and a parasitic channel of a conventional p-channel field-effect transistor.

FIG. 27 is a diagram showing an example of a profile of a Ge composition and a p-type impurity concentration when a modulation doping structure is employed in a conventional p-channel field effect transistor.

FIG. 28 is a diagram showing drain voltage-drain current characteristics (Vd-Id characteristics) of a conventional p-channel type field effect transistor.

FIG. 29 is a diagram showing a relationship between a Ge composition of strained SiGe on a Si substrate and a critical film thickness.

30A and 30B are SiGeC-pMOSF.
FIG. 4 is a diagram showing a band structure when a gate bias is applied when a p-type impurity doped layer is provided in a buffer layer and a cap layer in ET, respectively.

[Explanation of symbols]

 101, 201, 301 --- Semiconductor substrate 102, 202, 302 --- Silicon buffer layer 103, 203, 303 --- Channel layer 104, 204, 304 --- Silicon cap layer 105, 205, 305 --- Gate insulating film 106, 206, 306 --- Gate electrode 107, 207, 307 --- Source region 108, 208, 308 --- Drain region 109, 209, 309 --- Source Electrodes 110, 210, 310 --- Drain electrode 211 --- Silicon substrate 212 --- Buried oxide film 213 --- Surface silicon layer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Minoru Kubo, 1006 Kazuma Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. Term (reference) 5F110 AA01 CC02 DD05 DD13 EE09 FF02 GG01 GG02 GG07 GG12 GG19 GG25 GG28 GG29 GG33 GG36 GG44 GG47 HJ01 5F140 AA01 AC01 AC28 AC36 BA01 BA05 BA17 BB06 BB13 BB16 BB18 BC12 BF01

Claims (13)

[Claims] 1. A field effect transistor formed on a semiconductor substrate, comprising: a first semiconductor layer made of silicon; and a Si _1-x Ge _x (0
A second semiconductor layer having a composition represented by <x <1), a third semiconductor layer made of silicon provided on the second semiconductor layer, and provided on the third semiconductor layer A gate insulating film, and a gate electrode provided on the gate insulating film, wherein the second semiconductor layer is formed in a p-channel region where holes travel when a negative voltage is applied to the gate electrode. A p-channel field-effect transistor comprising the above C in a region containing the maximum value of the Ge content. 2. The p-channel field-effect transistor according to claim 1, wherein the second semiconductor layer is at least one of a region in contact with the first semiconductor layer and a region in contact with the third semiconductor layer. A p-channel field effect transistor, wherein the lattice distortion in one of the portions is 0.5% or less. 3. The p-channel field-effect transistor according to claim 1, wherein said second semiconductor layer is provided in all regions of said first semiconductor layer.
A p-channel field effect transistor, which is configured to lattice-match with said semiconductor layer and said third semiconductor layer. 4. The p-channel field effect transistor according to claim 1, wherein said p-channel field effect transistor is provided in a portion of said first semiconductor layer adjacent to said second semiconductor layer, A p-channel field-effect transistor further comprising a δ-doped layer containing a p-type impurity at a concentration. 5. The field effect transistor according to claim 4, wherein at least a part of the second semiconductor layer containing C is adjacent to the first semiconductor layer. A p-channel field-effect transistor. 6. The p-channel field effect transistor according to claim 1, wherein said p-channel field effect transistor is provided in a portion of said third semiconductor layer adjacent to said second semiconductor layer, A p-channel field effect transistor, further comprising a δ-doped layer containing a concentration of p-type impurities. 7. The p-channel field effect transistor according to claim 6, wherein at least a part of the second semiconductor layer containing C is adjacent to the third semiconductor layer. A p-channel field effect transistor, characterized in that: 8. A field effect transistor formed on a semiconductor substrate, comprising: a first semiconductor layer made of silicon; and a Si _1-x Ge _x (0
A second semiconductor layer having a composition represented by <x <1), a third semiconductor layer made of silicon provided on the second semiconductor layer, and provided on the third semiconductor layer A gate insulating film, and a gate electrode provided on the gate insulating film, wherein the second semiconductor layer is formed in a p-channel region where holes travel when a negative voltage is applied to the gate electrode. Wherein at least a part of the third semiconductor layer contains C. 9. The p-channel field effect transistor according to claim 8, wherein the at least a part of the third semiconductor layer containing C is adjacent to the second semiconductor layer. A p-channel field effect transistor. 10. The p-channel field effect transistor according to claim 9, wherein the at least a part of the third semiconductor layer containing C is separated from the gate insulating film by 1 nm or more. A p-channel field-effect transistor characterized by the above-mentioned. 11. The p-channel field-effect transistor according to claim 10, wherein the at least a part of the third semiconductor layer containing C is at least 2 nm away from the gate insulating film. A p-channel field-effect transistor characterized by the above-mentioned. 12. A field-effect transistor formed on a semiconductor substrate, comprising: a first semiconductor layer made of silicon; and a Si _1-x Ge _x (0
A second semiconductor layer having a composition represented by <x <1), a third semiconductor layer made of silicon provided on the second semiconductor layer, and provided on the third semiconductor layer A gate insulating film, and a gate electrode provided on the gate insulating film, wherein the second semiconductor layer is formed in a p-channel region where holes travel when a negative voltage is applied to the gate electrode. And a Ge content in the second semiconductor layer is more than 30%. 13. The p-channel field effect transistor according to claim 1, wherein said semiconductor substrate is an SOI substrate having a semiconductor layer provided on an insulating layer. The first semiconductor layer is a semiconductor layer on the SOI substrate, and when a negative voltage is applied to the gate electrode,
A p-channel field effect transistor, wherein a depletion layer is configured to reach a lower end of the first semiconductor layer.