JP2002197868A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory incorporating a memory which can perform high speed operation. SOLUTION: In a memory incorporated in a semiconductor memory, a dummy word line to which dummy cells of the prescribed bits corresponding to the number of bits of one word are connected is driven by a dummy word driver, after a dummy word signal transmitting in a dummy word line is delayed by the prescribed time by a delay circuit, a stop signal stopping internal operation of a memory is generated in accordance with the delayed dummy word signal by a control circuit. In this delay circuit, as a delay time when the dummy word signal is varied to an active state is large and a delay time when the dummy word signal is varied to a non-active state is small, an operation period of a memory is made short and high speed operation can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed semiconductor memory device equipped with a memory.

[0002]

2. Description of the Related Art For example, an address signal or the like is input as in an SRAM (static random access memory) or a ROM (read only memory), and data corresponding to the address is output after a predetermined time. In the memory, for example, a stop signal is generated inside the memory from an input address signal or the like, and the internal operation of the memory is stopped (standby state) using the stop signal. As a result, the speed of the memory and the power consumption have been reduced.

Usually, in a memory having a fixed memory size,
A dummy word line having a heavier load than the word line is used, and a stop signal is generated from a dummy word signal propagating through the dummy word line. On the other hand, in a semiconductor memory device, such as an embedded type, in which a memory of an arbitrary memory size can be mounted, a desired operation time may not be obtained due to a load of a dummy word line. In some cases, it is more cost-effective to adjust the delay of the dummy word signal.

A memory having a delay circuit for adjusting the delay of a dummy word signal will be described below.

FIG. 5 is a schematic diagram showing an example of the internal structure of the memory. As shown in FIG. 1, the memory 10 includes a memory cell array 12, a word driver 14, a dummy cell 16, a dummy word driver 18, and a delay circuit 20.
And a control circuit 22. In the illustrated example, for ease of explanation, circuits such as an address signal decoding circuit and a sense amplifier for amplifying data read from the memory cell array 12 are omitted.

Here, the memory cell array 12 has a predetermined number of memory words composed of memory cells of a predetermined number of bits.

On the other hand, the dummy cells 16 are provided with the same number of dummy cells as the memory cells carried by one word line. In the illustrated example, each dummy cell 16 is an N-type MOS transistor (NMOS) whose source and drain are connected to ground, and its gate is connected to a dummy word line. The dummy word driver 18 drives the aforementioned dummy word line when any one of the memory words is accessed.

The above-mentioned dummy cell 16 applies a load to a dummy word line equivalent to that of a memory cell for one word. The dummy word line is routed from the dummy word driver 18 to the right in the drawing, turned around at the dummy cell 16 at the right end, routed to the left, and further extended to the control circuit in the vertical direction in the drawing. For this reason, the dummy word signal propagating through the dummy word line is delayed according to the number of cells of the memory cell array 12 as compared with the word signal propagating through the word line.

As described above, the delay circuit 20 further delays the dummy word signal by a predetermined time. In addition,
A detailed description of the delay circuit 20 will be described later. The control circuit 22 generates a stop signal for stopping the internal operation of the memory from the dummy word signal input through the delay circuit 20. Based on the stop signal, the word signal is made inactive, and the operation of the sense amplifier and the like (not shown) is also stopped.

In the illustrated memory 10, for example, when the address signal changes, the word driver 14 corresponding to the change of the address signal
Drives the corresponding word line. In the illustrated example, a word line corresponding to the address signal is driven to a high level, and data write and read accesses are made to the memory cell array 12. When the address signal changes, the dummy word driver 18 simultaneously drives the dummy word line to a high level.

The dummy word signal is input to the control circuit 22 after the dummy word lines are routed and the delay time of the delay circuit 20 is reached. In the control circuit 22, when the dummy word signal is driven to a high level, the stop signal goes to a high level, and accordingly, the word signal falls to a low level in an inactive state. Thereafter, when the dummy word signal becomes low level, the stop signal also becomes low level after a predetermined time, and the memory is stopped.

Next, the delay circuit will be described. FIG.
FIG. 1 is a configuration circuit diagram of an example of a conventional delay circuit. The delay circuit 20c shown in FIG. 3 has three buffers 46 connected in series.
The signal is supplied to the control circuit 22 via c.

In the control circuit 22, when the dummy word signal rises to a high level, the stop signal rises to a high level after a predetermined delay time by the delay circuit 20c, as shown in the timing chart of FIG. The rise of the stop signal causes the word signal to fall to a low level in an inactive state. Thereafter, when the dummy word signal falls to a low level, the stop signal also falls to a low level after a predetermined delay time by the delay circuit 20c.

FIG. 8 is a schematic diagram of another example of a conventional delay circuit. The delay circuit 20d shown in FIG. 2 is capable of selecting a delay time, and includes two delay units 20c.
And a selector 48. Note that the delay unit is the delay circuit 20c shown in FIG.

The selector 48 includes transfer gates 40 and 42 composed of a P-type MOS transistor (PMOS) and an NMOS, and an inverter 44. The selection signal E is input to the NMOS of the transfer gate 40 and the gate of the PMOS of the transfer gate 42, and the selection signal E is input to the PMOS of the transfer gate 40 and the NMOS of the transfer gate 42 via the inverter 44.

The dummy word signal is input to the delay unit 20c, and the output of the delay unit 20c is input directly to the transfer gate 40 and to the transfer gate 42 via another delay unit 20c. The outputs of the transfer gates 40 and 42 are short-circuited, and the output of the selector
Is input to

The operation of the delay circuit 20d is the same as the operation of the above-described delay circuit 20c except that the delay time can be selected. That is, as shown in the timing chart of FIG. 9, when the selection signal E = 'H', the transfer gate 40 is turned on, and the stop signal is delayed from the dummy word signal by a predetermined delay time by the delay unit 20c. Is done. On the other hand, when the selection signal E = 'L', the transfer gate 42 is turned on, and the stop signal is delayed by a predetermined delay time by the two delay units 20c with respect to the dummy word signal.

In the memory 10, the next operation (memory access) cannot be started until the stop signal goes to the low level, which is the inactive state. In the conventional delay circuits 20c and 20d, as described above, since the dummy word signal is simply delayed for a predetermined time, the time until the stop signal becomes inactive is similarly delayed. There is a problem that the operation cycle becomes longer, which hinders high-speed operation.

[0019]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device equipped with a memory capable of operating at high speed in view of the problems based on the conventional technology.

[0020]

According to one aspect of the present invention, there is provided a semiconductor memory device having a memory, comprising: a dummy word driver for driving a dummy word line; and a dummy word driver connected to the dummy word line. A dummy cell having a predetermined number of bits corresponding to the number of bits of one word, a delay circuit for adjusting a delay time of a dummy word signal propagating through the dummy word line, and a dummy word signal delayed by the delay circuit. A control circuit for generating a stop signal for stopping the internal operation of the memory, wherein the delay circuit has a long delay time when the dummy word signal changes to an active state and a delay time when the dummy word signal changes to an inactive state. It is an object of the present invention to provide a semiconductor memory device characterized in that time is short.

Here, the delay circuit has a first inverter whose output signal has substantially the same delay time as a rise and a fall, and a first inverter whose output signal has a long delay time and a short delay time. It is preferable that two inverters are alternately connected in series.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory device according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

In the semiconductor memory device of the present invention, the delay circuit 20
Except for the difference in the configuration, a memory having the same configuration as the memory (see FIG. 3) 10 mounted on a conventionally known semiconductor memory device is mounted. That is, as shown in the schematic diagram of FIG. 3, the memory 10 mounted on the semiconductor memory device of the present invention is
Are a memory cell array 12, a word driver 14,
It includes a dummy cell 16, a dummy word driver 18, a delay circuit 20, and a control circuit 22.

Each of the components 1 other than the delay circuit 20
2, 14, 16, 18, and 22 have already been described in the description of the related art, and any of the conventionally known ones can be used. Therefore, detailed description thereof is omitted here.

Hereinafter, the delay circuit 20 according to the present invention will be described.

The delay circuit 20 according to the present invention has a delay time of the dummy word signal such that the delay time when the dummy word signal changes to the active state is long and the delay time when the dummy word signal changes to the inactive state is short. Is to adjust. For example, when the active state of the dummy word signal is at the high level, the rise of the dummy word signal after being delayed by the delay circuit 20 is relatively delayed, and the delay time of its fall is relatively short.

FIG. 1 is a circuit diagram of a delay circuit according to an embodiment of the present invention. The delay circuit 20a shown in the figure is configured by alternately connecting a first inverter 24 and a second inverter 26 in series. In the illustrated example, two first and second inverters 24 and 26 are alternately connected. Thus, the first and second inverters 2
By alternately connecting the signal lines 4 and 26, malfunction due to signal penetration or the like can be prevented, and the rising edge of the dummy word signal can be reliably propagated.

Here, the first inverter 24 has a delay time between the rise and fall of the output signal which is substantially equal, and is connected in series between the power supply and the ground.
MOS transistor (PMOS) 28 and N-type MO
An S transistor (NMOS) 30 is provided. PMO
The gates of S28 and NMOS 30 are short-circuited to be the input terminal of the first inverter 24, and the drains thereof are also short-circuited to be the output terminal of the first inverter 24.

On the other hand, the second inverter 26 has a long delay time at the rise of the output signal and a short delay time at the fall of the output signal.
6, a PMOS 32 connected in series with the output terminal of
34, and NMOSs 36 and 38 connected in parallel between the output terminal of the second inverter 26 and the ground. The gates of the PMOSs 32 and 34 and the NMOSs 36 and 38 are short-circuited and used as the input terminals of the second inverter 26.
8 are also short-circuited, and the second inverter 2
6 output terminals.

In the illustrated example, the second and fourth stages of the second stage
Of the second inverter 26 of the fourth stage receives the same signal as that of the NMOS 38 of the second inverter 26 of the second stage. Thereby, the delay time of the fall of the output signal of the second inverter 26 of the fourth stage is further reduced, and the propagation of the signal in the delay circuit 20a is stopped when the input to the delay circuit 20a falls. Can be. On the other hand, the second-stage second inverter 26 and the fourth-stage second inverter 26 may be configured completely independently.

The number of inverter stages and the order of connection are not limited. For example, the number of inverters may be odd and the polarity of the output signal may be inverted. In the illustrated example,
Although the second inverter has two PMOSs and two NMOSs, the present invention is not limited to this configuration, and may be two or more as necessary. Further, the number of PMOSs and the number of NMOSs may be different.

In the example of the delay circuit 20a shown in FIG.
0a, as shown in the timing chart of FIG. 2, the dummy word signal is first inverted by the first inverter 24 of the first stage, and the low level is output from the first inverter 24 of the first stage. An output signal A is output. As described above, the delay time of the rise and fall of the output signal A of the first inverter 24 of the first stage is substantially equal.

Subsequently, the output signal A of the first inverter 24 at the first stage is inverted by the second inverter 26 at the second stage, and the output signal of the high level is output from the second inverter 26 at the second stage. B is output. The output signal B of the second inverter 26 in the second stage has a long delay time at the rise and a short delay time at the fall.

The operations of the first inverter 24 of the third stage and the second inverter 26 of the fourth stage are the same as those of the first inverter 24 of the first stage and the second inverter 26 of the second stage. Is exactly the same as The output signal of the second inverter 26 in the fourth stage, that is, the delay circuit 2
The fall of the output signal 0a is at the same timing as the fall of the output signal B of the second inverter 26 in the second stage. As a result, the output signal of the delay circuit 20a has a longer delay time at the rise and a shorter delay time at the fall as compared with the dummy word signal to be inputted.

Next, another example of the delay circuit 20 will be described.

FIG. 3 is a schematic diagram showing the configuration of another embodiment of the delay circuit. The delay circuit 20b shown in the figure can select a delay time similarly to the conventional delay circuit 20d shown in FIG. 8, and the difference between the two is that a delay unit is used instead of the delay circuit 20c shown in FIG. Second, the delay circuit 20a according to the present invention shown in FIG. 1 is used. Therefore,
Here, the same components as those of the delay circuit 20d shown in FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The operation of the delay circuit 20b is the same as the operation of the delay circuit 20a except that the delay time can be selected. As shown in the timing chart of FIG. 4, when the selection signal E = 'H', the transfer gate 40 is turned on, and the stop signal is delayed from the dummy word signal by a predetermined delay time by the delay unit 20a. . On the other hand, when the selection signal E = 'L', the transfer gate 42 is turned on, and the stop signal is delayed by a predetermined delay time by the two delay units 20a with respect to the dummy word signal.

As described above, the delay circuit 20b according to the present invention has a large delay time of the dummy word signal when the dummy word signal rises and changes to a high level which is an active state. The delay time when the dummy word signal falls and changes to the inactive low level is small. Therefore, the time until the stop signal becomes inactive is short, so that there is no waste, and the operation cycle of the memory is shortened, so that high-speed operation can be performed.

As described above, the semiconductor memory device of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course. For example, as the above embodiment, two specific examples of the delay circuit according to the present invention have been described. However, the present invention is not limited to these, and the delay circuit according to the present invention may have the same function. May be constituted by different means.

[0040]

As described above in detail, the semiconductor memory device of the present invention is provided with a memory for generating a stop signal based on a dummy word signal and stopping an internal operation in response to the stop signal. The circuit adjusts the delay time of the dummy word signal so that the delay time when the dummy word signal changes to the active state is large and the delay time when the dummy word signal changes to the inactive state is small. . Thus, according to the semiconductor memory device of the present invention, the time required for the stop signal to become inactive is short, and the operation cycle of the memory is shortened, so that the memory can be operated at high speed.

[Brief description of the drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of a delay circuit according to the present invention.

FIG. 2 is a timing chart of one embodiment showing an operation of the delay circuit shown in FIG. 1;

FIG. 3 is a schematic configuration diagram of another embodiment of the delay circuit according to the present invention.

FIG. 4 is a timing chart of one embodiment showing an operation of the delay circuit shown in FIG. 3;

FIG. 5 is a schematic diagram illustrating an example of an internal structure of a memory;

FIG. 6 is a configuration circuit diagram of an example of a conventional delay circuit.

FIG. 7 is a timing chart illustrating an example of an operation of the delay circuit illustrated in FIG. 6;

FIG. 8 is a schematic diagram of another example of a conventional delay circuit.

FIG. 9 is a timing chart illustrating an example of an operation of the delay circuit illustrated in FIG. 8;

[Explanation of symbols]

Reference Signs List 10 memory 12 memory cell array 14 word driver 16 dummy cell 18 dummy word driver 20, 20a, 20b, 20c, 20d delay circuit 22 control circuit 24, 26, 44 inverter 28, 32, 34 P-type MOS transistor (PMO
S) 30, 36, 38 N-type MOS transistor (NMO
S) 40, 42 transfer gate 46 buffer 48 selector

Claims (2)

[Claims] 1. A semiconductor memory device having a memory mounted thereon, comprising: a dummy word driver for driving a dummy word line; a dummy cell connected to the dummy word line and having a predetermined number of bits corresponding to the number of bits of one word; A delay circuit for adjusting a delay time of a dummy word signal propagating through the dummy word line, and a control circuit for generating a stop signal for stopping internal operation of the memory in accordance with the dummy word signal delayed by the delay circuit. Wherein the delay circuit has a long delay time when the dummy word signal changes to an active state, and a small delay time when the dummy word signal changes to an inactive state. 2. The delay circuit according to claim 1, wherein the delay time of the output signal is substantially equal to the delay time of the rise of the output signal, and the delay time of the rise of the output signal is large.
2. The method according to claim 1, wherein a second inverter having a short fall delay time is alternately connected in series, and at the same time as a fall of an input to the delay circuit, signal propagation in the delay circuit is stopped. 13. The semiconductor memory device according to claim 1.