JP2002196976A - Memory access control method and device in ic card equipped with flash memory, and program storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve renewal processing speed by eliminating any necessity for a program side determining whether being a writing processing or renewal processing and substituting the writing processing for the renewal processing. SOLUTION: The IC card 100 is provided with a control part 102, a logic memory reading and writing means 103, a garbage collection control means 104, a unit operation means 105, a final unit tracking means 106, a top unit control means 107, a memory access module 108, and a flash memory 109.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for controlling memory access in an IC card equipped with a flash memory and a program storage medium.

[0002]

2. Description of the Related Art An IC card in which a semiconductor chip is incorporated in a plastic card is used in various fields. I
As the demand and demand for C-cards increase, various functions
It has become desirable to include them in C cards. Therefore, an IC card equipped with a large-capacity and high-density flash memory is well known.

FIG. 9 is a diagram showing a memory access control system in a conventional flash memory IC card.
FIG. 10 is a diagram showing a flow of an update process in a conventional flash memory.

In FIG. 9, 900 is an IC card, 90
1 is an external device, 902 is a control unit in the IC card 900,
903, a memory access unit in the IC card 900;
Reference numeral 4 denotes a flash memory in the IC card 900; 905, a command transmission from the external device 901 to the control unit 902;
06 is a response reception from the control unit 902 to the external device 901, 907 is the control unit 902 and the memory access unit 903
908 is a memory access unit 903
And a flash memory 904.

In the conventional memory access control method for a flash memory-mounted IC card, as shown in FIG. 10, when a certain erase block is updated, an area other than the update address is copied to a new area 2 (step 1001). The original area 1 is erased (step 100
2) The original copied to the new area 2 is returned to the original area 1, and data to be updated is written, and the new area 2 is erased (step 1003).

[0006]

As a feature of the flash memory, there is a major problem that there is no complete bit changeability. Complete bit changeability means that a normal RAM or E
This means that bit or byte update processing can be performed like an EPROM or a hard disk. A flash memory without complete bit changeability has an irreversible property that conversion from "1" to "0" is possible, but cannot be updated from "0" to "1".

[0007] Another feature of the flash memory is a set unit called an erase block. This erase block represents a unit of erasure, and the above operation of “0” → “1” can be performed on the entire erase block.

The problem here is that the erasure unit is not a byte unit but an erase block unit (about 64 k
Bytes) and the erasing process takes time. In order to update one byte, the processing is as shown in FIG. Assuming that writing one byte takes 8 μs,
If you write to a 64k byte erase block,
It takes about 512 ms. Furthermore, since it takes about one second to erase the data in the erase block, it takes a total of about 1.5 seconds simply to update one byte.

As described above, the flash memory is high-speed in reading and writing due to its characteristics. However, the updating process can be performed only in erase block units, not in byte units, and processing time is required. It is desirable that the program handling the flash memory can perform the update processing at the same processing speed as the reading and writing as much as possible.

In order to perform such a process, conventionally, in order to perform an update process, as shown in FIG.
The erase block is erased twice (step 1002
And 1003), and the copy processing of the entire erase block must be performed twice (steps 1001 and 1003).

In the flash memory, when writing, a program determines whether a block to be written is a previously written block or a block to be written for the first time, and performs a writing process or an updating process, respectively. Needed.

The present invention has been made in view of the above-mentioned problems of the conventional system, and an object of the present invention is to make it possible for a program to show a logical space without directly showing a physical space, and to perform an update process. Devise so that the write process can be treated as the same process, eliminate the need for the program to determine whether the process is a write process or an update process, and
By substituting the update process with the write process,
An object of the present invention is to provide a method and an apparatus for controlling a memory access in a flash memory IC card at a high speed and a program storage medium by improving the update processing speed.

[0013]

In order to solve the above-mentioned problems, a memory access control method for an IC card equipped with a flash memory according to the present invention comprises the steps of dividing a memory space into a physical space and a virtual logical space; By mapping the space and the logical space, the update process to the memory is reflected only in the logical space, and the physical space is replaced with read and write processes.

In the mapping between the physical space and the logical space, the data at a certain logical address is constituted by a unit in which a next physical address part which is a physical address indicating the next unit and a real data part are combined. When reading, the first unit corresponding to that address is searched, the next physical address part is traced until the last unit, and the actual data part of the last unit is the data corresponding to the logical address. It is characterized by.

In the data management by the units, when writing, the head unit corresponding to the address is searched, the physical address portion is traced until the last unit, and the new data storing the data to be written in the real data portion is stored. A unit is generated, and the physical address of the unit is stored in the physical address section of the last unit.

Further, in the data management by the units, in order to sort out the garbage units generated by the number of times of the update processing and restore the state without the garbage units, only the address of the head unit and the last unit tracked are used. To generate a simple unit group, and finally perform a garbage collection to erase all garbage units.

Further, the flash memory mounted IC of the present invention
The memory access control device in the card includes a head unit management unit that manages a logical space address and a head unit of a unit corresponding thereto, a last unit tracking unit that sequentially tracks the next unit of the unit and returns a last unit. A unit operating means for reading, writing, and generating a unit from a memory in an IC card, a read / write request from an external program, and a logical operation in cooperation with the head unit managing means, the last unit tracking means, and the unit operating means. A logical memory read / write unit for reading / writing address data; and a garbage collection management unit for performing garbage collection in cooperation with the head unit management unit, the last unit tracking unit, and the unit operation unit.

Further, the flash memory mounted I of the present invention
The program storage medium storing the memory access control program in the C card separates the memory space into a physical space and a virtual logical space, and maps the physical space and the logical space to perform the update process to the memory. Reflecting only in the logical space, the physical space is replaced with read and write processing, and in the mapping of the physical space and the logical space, data at a certain logical address is represented by a physical address indicating the next unit. It consists of a unit that is a combination of a certain next physical address part and a real data part, and when reading, it searches for the first unit corresponding to that address, traces the next physical address part until it becomes the last unit, The actual data part of the last unit is the data corresponding to the logical address, and when writing it, Searches for the first unit corresponding to the address, traces the physical address part until it becomes the last unit, generates a new unit that stores the data to be written to the actual data part, and replaces the physical address of that unit with the physical address of the last unit A simple unit group that connects only the address of the first unit and the last unit tracked in order to organize the garbage units generated by the number of times of update processing and to restore the state without garbage units And finally performing a garbage collection to erase all garbage units.

That is, in the present invention, a logical space is provided without showing the physical space to the program side, and a read process and a write process that do not require an update process are provided as processes for the logical space. In the mapping from logical space to physical space, considering the unit consisting of the next physical address part and real data, if writing to a certain logical address occurs, search for the head unit corresponding to that logical address, and On the other hand, it checks whether the next unit exists, and if so, repeats the tracking of the next unit.If not, creates a new unit, writes the physical address to the next physical address part of the previous unit, and writes the new unit. Write the data to be written to the actual data section of. In the case of reading, similarly, the head unit corresponding to the logical address is searched, and the head unit is inspected for the next unit. If there is, the next unit is repeatedly traced. The data in the actual data section of the unit is read.

As described above, in the present invention, the program does not show the physical space in which the write process and the update process need to be distinguished from each other, but shows the logical space in which the write process and the update process do not need to be distinguished. Programming can be performed easily and simply.

Further, in the mapping between the logical space and the physical space, the updating process is substituted for the writing process,
The sum of the time to search for the head unit, which is the processing time for reading and writing, and the time to track the unit, and the total time to write a new unit during the update processing are determined by erasing two erase blocks for the conventional update processing. The overall writing speed is improved by the time subtracted from the copy processing of the entire two erase blocks.

Further, by erasing all dust units generated as many times as the number of times the updating process is performed, an area for generating a new unit can be secured.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings described below, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a diagram showing a system for memory access control in an IC card with a flash memory according to an embodiment of the present invention.

100 is an IC card, 101 is an external device,
102 is a control unit in the IC card 100, 103 is a logical memory read / write unit, 104 is a garbage collection management unit, 105 is a unit operation unit, 106 is a last unit tracking unit, 107 is a head unit management unit, 108 is a memory access module, 109 is a flash memory, 201 is a command transmission from the external device 101 to the control unit 102, 202 is a response reception from the control unit 102 to the external device 101, and 203 and 204 are memory reading and writing.

FIG. 2 is a diagram showing a flow of a logical space memory read / write process in the present embodiment, FIG. 3 is a diagram showing a flow of a write process in the present embodiment, and FIG. 4 is a diagram of a garbage collection process in the present embodiment. Diagram showing the flow,
FIGS. 5A and 5B are diagrams showing various formats in the present embodiment, FIG. 6 is a diagram showing an example of arrangement of units in the present embodiment, and FIG. 7 is a diagram after a write process in the present embodiment. FIGS. 8A and 8B are diagrams showing a state after the garbage collection processing in the present embodiment.

In the present embodiment, the IC card 10
It is assumed that the control unit 102 in 0 executes an internal program, and a read / write request to the logical space memory is generated from the program. It is also assumed that a garbage collection request is generated from the control unit 102 or an internal program.

<< Read / Write Process >> The flow of the read / write process for the logical space memory will be described below with reference to FIGS. 2, 1, 5, and 6.

Command transmission 201 from external device 101
As a result, the logical space memory read / write processing is started (step 2001 in FIG. 2), and the control unit 102 issues a read / write request to the logical space memory with the logical memory read / write unit
03 (FIG. 1), the head unit management means 10
7 is checked whether the logical address is registered in the registration format 501 of the head unit management means shown in FIG. 5A (step 2002).

The head unit management means 107 searches the flash memory 109 by using the memory access module 108 to check whether the logical address is registered in the registration table managed by the head unit management means 107 and returns the presence or absence.

When the logical address is% 1, in the case shown in FIG. 6, the logical address% 1 is registered, so that "Yes" is returned. In the case of the logical address% 3, "No" is returned because it is not registered.

If there is no unit format, a unit format 50 as shown in FIG.
A request is made to the unit operating means 105 to generate a new unit conforming to Step 2 (Step 2003).

The unit operating means 105 uses the memory access module 108 to search for a free area in the flash memory 109, stores a new unit, and returns its physical address. The head unit management unit 107 uses the set of the physical address and the logical address of the received new unit.
Request registration (step 2004).

The head unit management means 107 registers in a registration table managed by itself using the memory access module 108. If there is, nothing is performed, and the process proceeds to the next process.

Next, the last unit tracking unit 106 checks the physical address of the last unit. The last unit tracking means 106 determines whether the next physical address part of the unit is NULL,
The value of the next physical address part is registered with the unit operating means 105 (step 2005).

The unit operating means 105 returns the next physical address of the unit using the memory access module 108. If the next physical address is not NULL,
The unit indicated by the next physical address part is the current unit, and the next physical address part of the unit is NULL.
And returns the physical address of the last unit (step 2006). In the case of FIG. 6, when the physical address # 1 is passed, the physical address # 5 is returned.

Next, it is determined whether the process is a read process or a write process (step 2007).

In the case of the reading process, the value of the data part of the unit is returned to the execution of the internal program (step 200).
8).

In the case of writing, a writing process is performed (step 2009), and the process returns to the internal program.

<< Write Process >> The flow of the read process will be described below with reference to FIGS. 3, 1, 6, and 7.

Here, the writing process (step 3 in FIG. 3)
001) first requests the unit operating means 105 (FIG. 1) to generate a new unit (step 300).
2) Request the unit operating means 105 to store the generated physical address of the new unit in the physical address next to the current unit (step 3003).

The unit operation means 105 uses the memory access module 108 to store the physical address of the new unit in the physical address next to the current unit. Then, it requests the unit operating means 105 to store the data to be written in the actual data section of the new unit.

The unit operating means 105 stores data to be written in the real data section of the new unit by using the memory access module 108 (step 3004), and the writing process ends (step 3005).

In the case of FIG. 6, the result of the process of writing the value & 4 to the logical address% 1 is as shown in FIG.

<< Garbage Collection Process >> The flow of the garbage collection (deletion of dust unit) process will be described below with reference to FIGS. 4, 1, 7, and 8.

When the garbage collection management unit 104 receives a garbage collection request generated in the control unit 102 or the internal program, the garbage collection process is started (step 4001), and the unit registered in the head unit management unit 107 is deleted. Replace with a simple unit group. In this replacement process, first, a set of physical addresses and logical addresses of all the head units registered in the head unit management means 107 is received (step 4002).

Based on the physical address of each head unit, it requests the last unit tracking means 106 (FIG. 1) to return the last unit while erasing the unit. The processing content checks whether the next physical address of the current unit is NULL (step 400).
3).

If it is not NULL, the next unit indicated by the physical address next to the current unit is obtained from the unit operating means 105, it is made the current unit (step 4004), and the process is repeated until it becomes NULL. .

If it is NULL, a request is made to the unit operating means 105 to generate a new unit in a new area (step 4006).

A request is made to the head unit management means 107 to register a set of a logical address corresponding to the head unit and a physical address of the new unit in a new area (step 4007).

The unit operating means 1 stores the data section of the current unit in the data section of the next new unit.
05 (step 4008).

Next, a request is made to the unit operating means 105 to erase the current unit (step 4009), and the head unit management means 107 is to erase the set of the logical address and the physical address of the head unit in the original area. (Step 4010).

However, if the unit size is smaller than the erasable unit, only one unit cannot be erased. This is repeated until there is no more registration information managed by the head unit management means 107 in the original area. If there is no more registration information, step 4005 and step 4009
If the unit cannot be erased in step 4010, the original area where the unit that could not be erased exists is erased in erasable units (step 4).
011).

Thus, the garbage collection process ends (step 4012), and the process returns to the original request generation.

When the garbage collection process is performed in the case shown in FIG. 7, the result becomes as shown in FIG.

As described above, in the memory access control method in the IC card with a flash memory according to the present embodiment, the memory space is divided into a physical space and a virtual logical space, and the physical space and the logical space are mapped. Thus, the update process to the memory is reflected only in the logical space, and the read and write processes are replaced in the physical space.

In the mapping between the physical space and the logical space, the data at a certain logical address is, as shown in FIG. 5, a combination of the next physical address part which is the physical address indicating the next unit and the real data part. At the time of reading, as shown in FIG. 2, the head unit corresponding to the address is searched, the next physical address part is traced until the last unit, and the last unit is read. The actual data part is data corresponding to the logical address.

At the time of writing, as shown in FIG. 2, the head unit corresponding to the address is searched, the physical address part is traced until the last unit is reached, and the data to be written in the real data part is stored. A new unit is generated, and the physical address of that unit is stored in the physical address part of the last unit.

Further, in order to sort out garbage units generated by the number of times of update processing and restore the state without garbage units, a simple unit group is formed by connecting only the address of the head unit and the last unit tracked. Produces
Finally, perform a garbage collection to erase all garbage units.

The memory access control device in the flash memory IC card according to the present embodiment is shown in FIG.
As shown in (1), the head unit management means 107 for managing the address of the logical space and the head unit of the corresponding unit, the last unit tracking means 106 for sequentially tracking the next unit of the unit and returning the last unit, I
A unit operation unit 105 for reading, writing, and generating units from a memory in the C card 100; a read / write request from an external program of the external device 101; and a head unit management unit 107, a last unit tracking unit 106, and a unit operation unit Logical memory read / write means 1 for reading / writing data of a logical address in cooperation with the logical memory 105
And a garbage collection management unit 104 for performing garbage collection in cooperation with the head unit management unit 107, the last unit tracking unit 106, and the unit operation unit 105.

Further, the flash memory mounting I of the present invention
The program storage medium storing the memory access control program in the C card separates the memory space into a physical space and a virtual logical space, and maps the physical space and the logical space to perform the update process to the memory in the logical space. Reflecting only on the physical space, it is replaced with read and write processing, and in mapping between the physical space and the logical space, data at a certain logical address is replaced with the next physical address part which is a physical address pointing to the next unit. It is composed of units that are combinations of actual data parts, and when reading, it searches for the head unit corresponding to that address,
The next physical address part is traced until the last unit, and the actual data part of the last unit is set as data corresponding to the logical address.When writing, the first unit corresponding to the address is searched, and the last unit is searched. Tracks the physical address part until it becomes a unit, generates a new unit that stores the data to be written to the real data part, stores the physical address of that unit in the physical address part of the last unit, and occurs as many times as the number of update processing In order to sort out garbage units and restore the state without garbage units, a simple unit group is generated by connecting only the head unit address and the last unit tracked, and all garbage units are erased at the end A memory access control program for performing garbage collection is stored.

As described above, according to the present invention, the program does not show the physical space in which the write process and the update process must be distinguished from each other, but shows the logical space in which the write process and the update process do not need to be distinguished. Programming can be performed easily and simply. In addition, in the mapping of the logical space and the physical space, the update process is used as a substitute for the write process, so that the total time for searching the head unit, which is the read / write processing time, and the time for tracking the unit, and a newer unit for the update process. The overall writing speed is improved by the time obtained by subtracting the total writing time of the erase block from two erase block erase operations for performing the conventional update process and the two erase block entire copy processes. Further, by erasing all dust units generated by the number of times the update process is performed, an area for generating a new unit can be secured.

As described above, according to the present embodiment,
There is no need for the program to be conscious of whether it is write processing or update processing. Further, the updating process can be executed at the same processing speed as the reading or writing process. Further, there is an effect that all dust units when many update processes are performed can be erased.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it is needless to say that various modifications can be made without departing from the scope of the invention. It is.

[0065]

As described above, according to the present invention,
There is no need for the program to be conscious of whether it is write processing or update processing. Further, the updating process can be executed at the same processing speed as the reading or writing process. Further, there is an effect that all dust units when many update processes are performed can be erased.

[Brief description of the drawings]

FIG. 1 shows a flash memory mounted I according to an embodiment of the present invention.
FIG. 3 is a diagram showing a system for memory access control in a C card.

FIG. 2 is a diagram showing a flow of a logical space memory read / write process in the present embodiment.

FIG. 3 is a diagram showing a flow of a writing process according to the embodiment.

FIG. 4 is a diagram showing a flow of a garbage collection process in the present embodiment.

FIGS. 5A and 5B are diagrams showing various formats in the present embodiment.

FIG. 6 is a diagram showing an example of arrangement of units in the present embodiment.

FIG. 7 is a diagram showing a state after a write process according to the embodiment;

FIG. 8 is a diagram illustrating a state after a garbage collection process according to the present embodiment.

FIG. 9 is a diagram showing a memory access control system in a conventional flash memory IC card.

FIG. 10 is a diagram showing a flow of an update process in a conventional flash memory.

[Explanation of symbols]

100: IC card, 101: external device, 102: control unit, 103: logical memory read / write unit, 104: garbage collection management unit, 105: unit operation unit
106: last unit tracking means, 107: leading unit management means, 108: memory access module, 109
... flash memory, 201 ... command transmission, 202 ...
Response reception, 203, 204: Memory read / write.

Continuing on the front page (72) Inventor Shinsuke Yoshida 2-3-1 Otemachi, Chiyoda-ku, Tokyo Within Nippon Telegraph and Telephone Corporation (72) Inventor Huo Nihongo 2-3-1 Otemachi, Chiyoda-ku, Tokyo F-term in Nippon Telegraph and Telephone Corporation (reference) 5B035 AA02 BB09 BC00 CA11 CA29 5B060 AA07 AA08 AA10 AB26 AC11

Claims (6)

[Claims] A memory space is divided into a physical space and a virtual logical space, and the physical space and the logical space are mapped to reflect an update process to a memory only in the logical space. Above, a memory access control method in a flash memory-mounted IC card, which is replaced with read and write processing. 2. In the mapping of the physical space and the logical space, the data at a certain logical address is constituted by a unit which is a combination of a next physical address part which is a physical address indicating the next unit and a real data part. When reading, the first unit corresponding to that address is searched, the next physical address part is traced until the last unit, and the actual data part of the last unit is the data corresponding to the logical address. 2. The memory access control method in a flash memory-mounted IC card according to claim 1, wherein: 3. In the data management by the unit,
When writing, search for the head unit corresponding to that address, trace the physical address part until the last unit, generate a new unit storing the data to be written to the real data part, and change the physical address of that unit to the last. 3. The memory access control method for an IC card with a flash memory according to claim 2, wherein the memory access is stored in a physical address portion of the unit. 4. The data management by the unit,
In order to sort out garbage units generated by the number of update processes and restore the state without garbage units, a simple unit group is generated by connecting only the address of the top unit and the last unit tracked, 3. A flash memory-mounted IC card and a memory access control method according to claim 2, wherein a garbage collection for erasing all dust units is performed. 5. A head unit management means for managing an address in a logical space and a head unit of a unit corresponding thereto, a last unit tracking means for sequentially tracing a unit next to the unit and returning a last unit, and an IC card. Unit operation means for reading, writing, and generating units from an internal memory; accepting a read / write request from an external program; and linking the head unit management means, the last unit tracking means, and the unit operation means with logical address data. And a garbage collection management means for performing garbage collection in cooperation with the head unit management means, the last unit tracking means, and the unit operation means. Memory access on the card Access control device. 6. A physical space and a virtual logical space are separated from each other, and the physical space and the logical space are mapped to reflect an update process to a memory only in the logical space. The upper part is replaced with read and write processing. In the mapping between the physical space and the logical space, data at a certain logical address is replaced with a next physical address part and a real data part which are physical addresses indicating the next unit. When reading, the first unit corresponding to that address is searched, the next physical address part is traced until the last unit is reached, and the actual data part of the last unit is When writing as data corresponding to an address, search for the first unit corresponding to that address and continue until it becomes the last unit. Tracks the physical address part, generates a new unit that stores the data to be written to the real data part, stores the physical address of that unit in the physical address part of the last unit, and generates garbage generated by the number of update processing In order to organize the units and restore them to a state without garbage units, a garbage collection that creates a simple unit group by connecting only the address of the first unit and the last unit tracked, and finally erases all garbage units A program storage medium storing a memory access control program in an IC card with a flash memory, wherein the program is executed.