JP2002196722A - Matrix display device and driving method and electronic equipment therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make low power consumption and high quality display compatible in a case of sector display. SOLUTION: A scanning line driving circuit 350 supplies each of the scanning lines 312 belonging to a display area with a selection signal in a latter half period of one horizontal scanning period and a non-selection signal in the other period with the polarity inverted in each vertical scanning period, and on the other hand, it supplies each of the scanning lines 312 belonging to a non-selection area with the non-selection signal with the polarity inverted in each vertical scanning period with one or more non-selection signals. In a data line driving circuit 250, data signals inverted at a relatively short period are supplied to data lines 212 when the scanning liens 312 belonging to the first non-display area adjacent to the display area are selected, and on the other hand, data signals inverted at a relatively long period are supplied the data lines 212 when the scanning lines 312 belonging to the second non-display area adjacent to the first non-display area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a matrix type display device, which suppresses the occurrence of image quality degradation and extremely low power consumption, a matrix type display device, and electronic equipment.

[0002]

2. Description of the Related Art In a matrix type display panel, a switching element is provided for each of pixel electrodes arranged in a matrix and an element substrate provided with a plurality of data lines to which one ends of the switching elements are connected. And a counter substrate on which scanning lines and color filters are formed, and a liquid crystal filled between the two substrates.

In such a configuration, a thin film diode (TFD) is used as a switching element.
When a voltage exceeding the threshold voltage of the switching element is supplied between the data line and the scanning line using a two-terminal nonlinear element such as the above, the switching element is turned on and a predetermined charge is accumulated in the liquid crystal layer. Then, even if a voltage lower than the threshold voltage is applied to turn off the switching element after the charge accumulation, the charge accumulation in the liquid crystal layer is maintained if the resistance of the liquid crystal layer is sufficiently high. As described above, when each switching element is driven to control the amount of charge to be stored, the alignment state of the liquid crystal changes for each pixel, and it is possible to display predetermined information. At this time, since it is sufficient to apply a signal voltage that is turned on to the liquid crystal layer of each pixel to accumulate charges during a part of the period, the scanning lines and the scanning lines can be selected by time division. Multiplex driving in which a data line is shared by a plurality of pixels is possible.

By the way, the number of display dots is increasing year by year on a matrix type display panel used for a portable electronic device such as a portable telephone so that more information can be displayed. On the other hand, since portable electronic devices are driven by a battery in principle, low power consumption is strongly required.
Therefore, such a matrix type display panel includes:
At first glance, two seemingly contradictory characteristics of higher resolution and lower power consumption are required. In order to solve this problem, when high resolution is required, full screen display is used. In other cases, only a partial area of the screen is displayed and other areas are not displayed. Attempts have been made to reduce power consumption by using a partial drive method.

FIG. 14 is a timing chart showing driving waveforms of a display panel in a conventional partial driving method.
In this example, the total number of scanning lines is 220, and the region from the 101st scanning line to the 120th scanning line is used as the display region, while the region from the 1st scanning line to the 100th scanning line is used. Area and the 121st scan line to the second
It is a non-display region a region up to 20 th scan line.
The display panel operates in the normally white mode, and displays black in the display area.

[0006] The scanning signal Y101 supplied to the 101st scanning line is generated during the 101st horizontal scanning period.
The selection voltage (VSP in this example) is taken in a half period thereafter. It should be noted that other scanning signals corresponding to the display area also take a selection voltage (VSP or VSN) in the latter half of each horizontal scanning period, similarly to the scanning signal Y101. On the other hand, a non-selection voltage (VHP or VHN) is always supplied to the scanning line corresponding to the non-display area.

A data signal X supplied to a certain data line, as shown in FIG.
While the signal waveform has a small number of inversions and a long cycle, it has a normal signal waveform in a period corresponding to the display area.

Thus, it is possible to display an image only in a display area and not to display an image in a non-display area. In addition, first, power is not written in the liquid crystal layer in the non-display area, and second, the period of inversion of the data signal X is increased in a period corresponding to the non-display area, thereby reducing power consumption. it can.

[0009]

By the way, the effective value waveform X 'of the data signal X greatly fluctuates in the non-display period due to the influence of the low frequency component in the non-display period as shown in FIG. On the other hand, the effective value waveform X ′ immediately after the start of the display period
Is affected by the non-display period, and then converges to an intermediate value. That is, the effective value of the data signal X supplied to the data line is different immediately after the start and the end of the display period.

On the other hand, since the transmittance of the liquid crystal layer changes according to the effective value of the voltage applied thereto, when the effective value of the data signal X changes, the display gradation changes under the influence. Therefore, immediately after the start and immediately before the end of the display period,
There is a problem that the gray scale actually displayed differs when trying to display the same gray scale, and the image quality deteriorates.

The present invention has been made in view of such a problem, and its object is to reduce the power consumption and to simplify the configuration while suppressing the occurrence of image quality deterioration. It is an object of the present invention to provide a driving method of a matrix type display device capable of performing the same, a matrix type display device including the driving circuit, and an electronic device including the display device.

[0012]

In order to achieve the above object, in a method of driving a matrix type display device according to the present invention, a method for driving a matrix type display device corresponding to each intersection of a plurality of scanning lines and a plurality of data lines is provided. A driving unit that drives a pixel provided by a switching element, wherein a display area including a part of the plurality of scanning lines is set to a display state, and is adjacent to the display area including another scanning line. When the first non-display area and the second non-display area adjacent to the first non-display area are set to the non-display state, each of the scanning lines belonging to the first non-display area and the second non-display area In response, a non-selection signal for bringing the switching element into a non-conductive state is supplied with the polarity inverted every one or more vertical scanning periods with respect to an intermediate value of the signal supplied to the data line, and the second non-selection signal is supplied. The scanning line belonging to the display area is selected. Then, for each of the data lines, the polarity of the data signal composed of the positive voltage level and the negative voltage level based on the intermediate value of the signal amplitude is inverted in the first cycle based on the intermediate value. And when a scanning line belonging to the first non-display area is selected,
Supplying a data signal composed of the positive voltage level and the negative voltage level to each of the data lines in a second cycle shorter than the first cycle with reference to an intermediate value thereof; Features.

According to the present invention, when a scanning line in the first non-display area is selected, a data signal which is inverted in a short cycle is supplied. Therefore, when a scanning line in the second non-display area is selected, a long cycle is selected. Even when the data signal is supplied, the effective value waveform of the data signal can be made to converge to an intermediate voltage level between the positive voltage level and the negative voltage level when selecting the scanning line in the display area. Therefore, it is possible to suppress the image quality of the display area from being deteriorated due to the influence of the non-display area. Note that the second cycle is preferably one horizontal scanning period cycle.

Further, considering only the viewpoint of suppressing power consumption, it is desirable to supply a signal corresponding to an intermediate value of signals supplied to the data lines to each of the scanning lines belonging to the non-display area. it is conceivable that. However, in this configuration, a voltage corresponding to the intermediate value needs to be separately generated, and further, a signal of a voltage corresponding to the intermediate value needs to be separately selected in a circuit for driving the scanning line. The structures of the circuit and the scan line driver circuit are complicated. On the other hand, according to the present invention, for each of the scanning lines belonging to the first non-display area and the second non-display area, the non-selection signal is output every one or more vertical scanning periods based on the intermediate value. , It is not necessary to generate a signal having a voltage corresponding to an intermediate value, and it is not necessary to select a signal. Therefore, the configuration is simplified. Further, since the voltage level is switched every one or more vertical scanning periods, more preferably, every period longer than one vertical scanning period, the frequency of the signal supplied to the scanning line also decreases. For this reason,
In a circuit for driving a scanning line, power consumption accompanying a voltage switching operation is suppressed, and power consumed by charging and discharging of a capacitance associated with the scanning line and the driving circuit by voltage switching is also suppressed.

Further, in the present invention, for each of the scanning lines belonging to the display area, in one of the divided periods of one horizontal scanning period, a selection signal for turning on the switching element is provided. In the period of
A non-selection signal to make the switching element non-conductive,
It is preferable that the polarity of the signal supplied to the data line be inverted every predetermined period based on the intermediate value of the signal and supplied. According to this configuration, the signal supplied to each of the scanning lines belonging to the display area does not change at all in comparison with a normal state in which all the scanning lines are used as the display area. For this reason,
The configuration is not complicated due to the change of the duty ratio, and the display quality of the display area is not reduced as compared with the normal state.

Further, in the present invention, the polarity inversion cycle of the positive side voltage level and the negative side voltage level when a scanning line belonging to the second non-display area is selected is set to the second non-display area. It is desirable that the horizontal scanning period be a substantial quotient obtained by dividing the number of scanning lines belonging to the integer by 2 or more. With this configuration, when the scanning line belonging to the second non-display area is selected, the period during which the signal at the positive voltage level is supplied and the period during the signal at the negative level are supplied are equal to each other. If the horizontal scanning period is a quotient obtained by dividing the number of scanning lines belonging to the second non-display area by 2, the polarity inversion cycle becomes the longest, so that the power consumed by the voltage switching operation or the voltage As a result, the power consumed by charging and discharging the capacitance associated with the circuit and the wiring is minimized.

Next, in the matrix type display device according to the present invention, pixels provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines are driven by switching elements. A display area including a part of the plurality of scanning lines in the display state, and a first non-display area including another scanning line and adjacent to the display area, and a first non-display area. In a case where an adjacent second non-display area is set to a non-display state, non-selection of setting the switching element to a non-conductive state for each of the first non-display area and the scanning line belonging to the second non-display area. A scanning line driving circuit for supplying a signal by inverting the polarity every one or more vertical scanning periods with respect to an intermediate value of the signal supplied to the data line, and a scanning line belonging to the second non-display area; The data , A data signal comprising a positive voltage level and a negative voltage level based on an intermediate value of the signal amplitude is supplied in a first cycle with respect to the intermediate value, and the data signal is inverted. When a scanning line belonging to the display area is selected, for each of the data lines,
A data line driving circuit for supplying a data signal comprising the positive side voltage level and the negative side voltage level by inverting the polarity of the data signal in a second cycle shorter than the first cycle with reference to an intermediate value thereof. Features.

According to the present invention, the above-described effects can be obtained on both the scanning line side and the data line side. Therefore, by this synergistic effect, it is possible to further reduce the power consumption, further increase the resolution, and simplify the configuration while suppressing the occurrence of image quality deterioration. Here, in the present invention, it is preferable that the scanning line drive circuit alternately inverts the polarity of the selection signal supplied to the adjacent scanning lines based on the intermediate value. The current-voltage characteristic of the switching element that drives the pixel is slightly different between the case where the positive voltage is applied and the case where the negative voltage is applied, and the voltage applied to the pixel may be different. According to the present invention, the polarity of the selection voltage supplied to the adjacent scanning line is inverted, and the polarity of the data signal also corresponds to the polarity of the selection signal. The polarity of the voltage applied to the pixel located on the second scanning line is alternately inverted. For this reason, display unevenness of the pixel is inconspicuous, and since the polarity inversion driving frequency is high, flicker is also inconspicuous.

Further, in the present invention, the data line drive circuit includes a memory having an area corresponding to the pixel, and when a scanning line belonging to the display area is selected, reads out display data from the memory. Generating a signal consisting of the positive voltage level and the negative voltage level based on the display data, and selecting a scanning line belonging to the first non-display area and the second non-display area, It is desirable to stop reading from the memory. In this configuration, the case where a scan line belonging to the first non-display area and the second non-display area is selected is a case where display is not required. According to the present invention, in such a case, the reading of the memory is stopped. As a result, the power consumption is reduced.
Further lower power consumption can be achieved.

Further, in the present invention, the switching element is a two-terminal type switching element, and the matrix type display device comprises an electro-optic material sandwiched between a pair of substrates, and the pixel comprises the pair of substrates. Wherein the two-terminal switching element and the electro-optical material are connected in series between a plurality of scanning lines provided on one substrate and a plurality of data lines provided on the other substrate. Is desirable. In the present invention, it is possible to use a three-terminal type such as a transistor as a switching element. However, it is necessary to form a scanning line and a data line so as to cross each other on one substrate. There is a difficulty in the point that becomes higher. In addition, the manufacturing process becomes complicated. On the other hand, the use of the two-terminal type is advantageous in that a scanning line is formed on one substrate and a data line is formed on the other substrate, so that a wiring short circuit does not occur in principle. Further, the manufacturing process is simplified as compared with the case where the three-terminal type is used.

Further, in the present invention, the two-terminal switching element preferably has a conductor / insulator / conductor structure connected to either the scanning line or the data line. Among them, the conductor of the first layer can be directly used as a scanning line or a data line, and the insulator is formed by anodizing the conductor of the first layer. The process can be further simplified.

In addition, in order to achieve the above object, an electronic apparatus according to the present invention is provided with the above matrix type display device. Therefore, in this electronic device, as described above, in the display device, it is necessary to increase the resolution, further reduce the power consumption, and further simplify the configuration while suppressing the image quality deterioration. Becomes possible.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. <Electrical Configuration> First, the electrical configuration of the display device according to the embodiment of the present invention will be described. FIG. 1 is a block diagram showing this electrical configuration. As shown in this figure, on the liquid crystal panel 100, a plurality of data lines (segment electrodes) 212 are formed extending in the column (Y) direction, while a plurality of scanning lines (common electrodes) 312 are formed. Is line (X)
The pixel 116 is formed so as to extend in the direction, and corresponds to each intersection of the data line 212 and the scanning line 312. Further, each pixel 116 includes an electro-optical material (liquid crystal layer) 118 and a TFD which is an example of a switching element.
It is connected in series with a two-terminal switching element (hereinafter referred to as TFD) 220 such as a (Thin Film Diode). Here, in the present embodiment, for convenience of explanation, the total number of the scanning lines 312 is assumed to be 200, and the total number of the data lines 212 is assumed to be 160. it is not intended to limit the present invention to this. The data line driving circuit 250 supplies data signals X1 to X160 to each data line 212, and the scanning line driving circuit 350 supplies scanning signals Y1 to Y200 to each scanning line 312, respectively. Things.

In FIG. 1, the TFD 220 is connected to the data line 212, and the liquid crystal layer 118 is connected to the scanning line 31.
2 but on the contrary, the TFD 22
0 is on the scanning line 312 side, and the liquid crystal layer 118 is on the data line 21 side.
Alternatively, a configuration may be employed in which each of them is connected to the second side.

Next, the control circuit 400 supplies various control signals and clock signals to be described later to the data line driving circuit 250 and the scanning line driving circuit 350. The data line driving circuit 250 and the scanning line driving circuit 3
The details of the control circuit 50 and the control circuit 400 will also be described later.

Further, the drive voltage forming circuit 500 includes voltage levels VDP and VDN used as data signals and voltage levels VSP and VH used as scanning signals.
P, VHN, and VSN are respectively generated. The voltage levels VDP and VHP are shared as the same level, and similarly, the voltage levels VDN and VHN are shared at the same level. However, in the present embodiment, for convenience of explanation,
These voltage levels will be described separately. The power supply circuit 600 supplies power to the control circuit 400 and the drive voltage forming circuit 500.

<Panel Configuration> Next, the detailed configuration of the liquid crystal panel 100 will be described. FIG. 2 is a partially broken perspective view showing the structure. As shown in this figure, the liquid crystal panel 100 includes an element substrate 200 and an opposing substrate 300 disposed opposite to the element substrate 200. Among them, a pixel electrode 234 made of a transparent conductor such as ITO (Indium Tin Oxide) is provided on the opposing surface of the element substrate 200 in the X direction and the Y direction.
The pixel electrodes 234 arranged in the same column are connected to one of the data lines 212 extending in the Y direction through the TFD 220, respectively. Here, when viewed from the substrate side, the TFD 220 is formed of tantalum alone or a tantalum alloy, and is formed by anodizing the first conductor 222 branched from the data line 212 and the first conductor 222. It is composed of an insulator 224 and a second conductor 226 such as chromium or the like, and adopts a conductor / insulator / conductor sandwich structure. Therefore, the TFD 220 has a diode switching characteristic in which the current-voltage characteristic is non-linear in both positive and negative directions.

The insulator 201 has transparency and insulating properties. The reason why the insulator 201 is provided is to prevent the first conductor 222 from peeling off by heat treatment after the deposition of the second conductor 226. And the first
This is to prevent impurities from diffusing into the conductor 222. So if these are not a problem,
The insulator 201 can be omitted.

On the other hand, on the opposing surface of the opposing substrate 300, the scanning lines 312 are formed so as to extend in the X direction and to oppose the pixel electrodes 234. A constant gap is maintained between the element substrate 200 and the opposing substrate 300 thus configured by a sealing material and a spacer (both are not shown). In this closed space, for example, TN (Twisted) is used as an electro-optical material. Nematic) type liquid crystal 105 is sealed, whereby the liquid crystal layer 118 in FIG. 1 is formed. That is, at the intersection of the data line 212 and the scanning line 312, the liquid crystal layer 118
12, the pixel electrode 234, and the liquid crystal 105 sandwiched between the two electrodes.

Therefore, in such a configuration, when a selection voltage is applied as a scanning signal via the scanning line 312, the TFD becomes conductive. When a data signal is applied via the data line 212 during this conduction state,
Predetermined charges are stored in the liquid crystal layer connected to the TFD. Even after the charge is accumulated and a non-selection voltage is applied to make the TFD non-conductive, if the leak (off-leak) of the TFD is small and the resistance of the liquid crystal layer is sufficiently high,
The accumulation of charges in the liquid crystal layer is maintained. As described above, by controlling the amount of electric charge to be stored by driving each TFD, the alignment state of the liquid crystal changes for each pixel, and predetermined information can be displayed.

In addition, the opposite substrate 300 is provided with, for example, color filters arranged in a stripe shape, a mosaic shape, a triangle shape, or the like, depending on the use of the liquid crystal panel 100, and further includes a metal material or resin. Is provided. In addition, element substrate 2
Each of the opposing surfaces of the counter substrate 300 and the opposing substrate 300 is provided with an alignment film or the like that has been rubbed in a predetermined direction, and a polarizing plate corresponding to the alignment direction is provided on each back surface thereof (both are not shown). ).

However, in the liquid crystal panel 100, if a polymer-dispersed liquid crystal in which the liquid crystal is dispersed as fine particles in a polymer is used, the above-described alignment film and polarizing plate are not required, and the light use efficiency is reduced. This is advantageous in terms of higher brightness and lower power consumption of the liquid crystal panel. When the liquid crystal panel 100 is of a reflective type, the pixel electrode 2
34 may be made of a metal film having a high reflectivity such as aluminum, or the element substrate 200 may be made of an opaque semiconductor substrate.

The TFD 220 is an example of a two-terminal switching element. Alternatively, an element such as a ZnO (zinc oxide) varistor or an MSI (Metal Semi-Insulator) may be used as the two-terminal switching element. . Also,
Two of these elements may be connected in series or in parallel in opposite directions. In this case, the diode switching characteristics
There is also an advantage that symmetry is made in both positive and negative directions.

<Control Circuit> Next, the detailed configuration of the control circuit 400 will be described. FIG. 3 is a block diagram showing a configuration of the control circuit 400. In the figure, a high-frequency oscillation circuit 4006 generates a high-frequency pulse signal used as a source signal of a later-described gradation code pulse GCP. For this reason, the frequency of the high-frequency pulse signal is much higher than that of the low-frequency pulse signal that defines a half horizontal scanning period, and is about 3 MHz. Also, the frequency dividing circuit 4004
The frequency of the high-frequency pulse signal output from the high-frequency oscillation circuit 4006 is divided to generate a low-frequency pulse signal serving as a reference for horizontal scanning. Here, in the present embodiment, one horizontal scanning period is divided into a first half period and a second half period, and the driving is performed. Used to specify. Therefore, the frequency of the low-frequency pulse signal is 30 kHz.
about z. The control signal generation circuit 4002 generates a signal based on the low frequency panel signal output from the frequency division circuit 4004.
Various control signals and clock signals (PD1, PD2, YD,
YCLK, MY, INH, LP, MX, RES, SP
Etc.).

Here, the gradation control signal generation circuit 4008
Is a high-frequency oscillation circuit 40 in a half horizontal scanning period defined by a low-frequency pulse signal by the frequency dividing circuit 4004.
The high-frequency pulse signals according to G.06 are arranged according to the weight of the display data indicating the gray scale to generate a gray scale code pulse (gray scale control signal) GCP as shown in FIG. In FIG. 10, the gradation code pulses GCP are arranged at equal pitches for convenience of explanation, but may actually have different pitches.

The control signal generation circuit 4002 generates the following various control signals and clock signals according to the low frequency pulse signal from the frequency dividing circuit 4004.
First, the first partial display control signal PD1 is output from a certain scanning line 3
In a case where only the area included in the display area 12 is displayed and the other area included in the scanning line 312 is set as the non-display area (in the case of partial display), the scanning line 312 included in the display area is selected. Only at the H level and at the L level in other periods. Second, the second
The partial display control signal PD2 is a signal that becomes H level only during a period when the scanning line 312 included in a certain region adjacent to the display region in the non-display region is selected, and becomes L level during other periods.

Third, as shown in FIG. 5, the start pulse YD is a pulse output at the beginning of one vertical scanning period (one frame). Fourth, the clock signal YCLK
Is a reference signal on the scanning line side, and has a period of 1H corresponding to one horizontal scanning period as shown in FIG. Fifth, the AC drive signal MY is a signal used for AC driving the liquid crystal pixels on the scanning line side, and as shown in FIG. 5, the signal level is inverted every horizontal scanning period 1H, and In the horizontal scanning period in which the same scanning line is selected, the signal level is inverted every frame. Therefore, the AC drive signal MY controls the polarity of the voltage applied to the liquid crystal pixels every one horizontal scanning period, and controls the driving of the polarity every one vertical scanning period.

Sixth, the control signal INH is a signal for selecting the latter half of one horizontal scanning period, and becomes H-active during the latter half as shown in FIG. Seventh
The latch pulse LP is for latching a data signal on the data line side, and is output at the beginning of one horizontal scanning period as shown in FIG. Eighth,
The reset signal RES is a pulse for defining the first half period and the second half period of one horizontal scanning period on the data line side, and is output at the beginning of the first half period and the second half period as shown in FIG. Ninth, AC drive signal MX is a signal used for AC-driving the liquid crystal pixels in the data line side, as shown in FIG. 10, the next horizontal scanning period 1H from the latter half period of a horizontal scanning period 1H The signal is maintained at the same level until the first half of the period, and then the level is inverted. The AC drive signal MX in the latter half of one horizontal scanning period and the AC drive signal MY in the same period are:
The levels are set so as to be mutually inverted levels.

Further, the control signal generation circuit 4002
When the partial display control signal PD1 is set to the L level, the gradation code pulse GC is supplied to the gradation control signal generation circuit 4008.
Control to stop generation of P is performed. Note that the frequency dividing circuit 40
04 is replaced by a low-frequency oscillation circuit.
006 may be provided with two oscillation circuits.

[0040] <scanning line driving circuit> Next, details of the scanning line driving circuit 350. FIG. 4 is a block diagram showing a configuration of the scanning line driving circuit 350. In this figure, a shift register 3502 is a 200-bit shift register corresponding to the number of scanning lines, and sequentially shifts a start pulse YD supplied at the beginning of one frame according to a clock signal YCLK having a cycle of one horizontal scanning period. Then, the transfer signals YS1, YS2,.
Is output as Here, the transfer signals YS1 to YS1
The YS 200 has a one-to-one correspondence with each scanning line,
This specifies which scanning line 312 is to be selected.

Subsequently, a voltage selection signal forming circuit 3504
Outputs a voltage selection signal that determines a voltage to be applied to each scanning line 312 from the AC drive signal MY and the control signal INH. Here, in the present embodiment,
The voltages of the scanning signals applied to the scanning lines 312 included in the display area include VSP (positive-side selection voltage), VHP (positive-side non-selection voltage), VHN (negative-side non-selection voltage), and VSN (negative-side selection voltage). ), And among these, the selection voltage VS
The period during which P or VSN is actually applied is the latter half of one horizontal scanning period. Further, the non-selection voltage applied after the selection voltage is applied is VHP if the selection voltage is VSP, and VHN if the selection voltage is VSN, and is uniquely determined by the selection voltage. . Further, an intermediate voltage between VSP and VSN and an intermediate voltage between VHP and VHN match the reference voltage VR. In addition, the reference voltage VR matches an intermediate voltage between a positive data voltage VDP and a negative data voltage VDN of a data signal described later.

When the first partial display control signal PD1 is at the H level, the voltage selection signal forming circuit 3504 generates a voltage selection signal so that the voltage level of the scanning signal has the following relationship. That is, first, when a transfer signal corresponding to a certain scanning line becomes H level and the scanning line is selected, the control signal INH becomes H level (the latter half period of one horizontal scanning period). Secondly, the control voltage is set to a non-selection voltage corresponding to the selection voltage after the control signal INH transitions to the L level.
The voltage selection signal forming circuit 3504 generates a voltage selection signal. Specifically, the voltage selection signal forming circuit 3504 outputs a voltage selection signal for selecting the positive side selection voltage VSP during the period in which the control signal INH is active at H level if the AC drive signal MY is at H level. And after this,
While outputting a voltage selection signal for selecting the positive non-selection voltage VHP, if the AC drive signal MY is at the L level, a voltage selection signal for selecting the negative selection voltage VSN is output during the period, and thereafter, the negative selection voltage VSN is output. so that the outputs a voltage selection signal for selecting the non-selection voltage VHN.

In the embodiment of the present invention, the positive potential (positive polarity) and the negative potential (negative polarity) of the potential applied to the scanning line and the data line are determined based on the intermediate potential of the signal applied to the data line. The high potential side is positive and the low potential side is negative.

On the other hand, in the present embodiment, the voltage of the scanning signal applied to the scanning line 312 included in the non-display area is
There are only two values, VHP and VHN. Therefore, when the first partial display control signal PD1 is at the L level, the voltage selection signal forming circuit 3504 generates the voltage selection signal so that the voltage level of the scanning signal has the following relationship. That is, first, the transfer signal corresponding to a certain scanning line becomes H level, the scanning line is selected, and the control signal INH becomes H level, so that the latter half of one horizontal scanning period is selected. Then, the voltage selection signal forming circuit 3504 generates a voltage selection signal so that one of the positive side non-selection voltage VHP and the negative side non-selection voltage VHN is inverted from the other.

The level shifter 3506 expands the voltage amplitude of the voltage selection signal output by the voltage selection signal forming circuit 3504. And selector 3
508 selects a voltage indicated by the voltage selection signal whose voltage amplitude has been enlarged and selects the corresponding scanning line 3
12 are supplied.

<Voltage Waveform of Scanning Signal> Next, the voltage waveform of the scanning signal supplied by the scanning line driving circuit 350 having the above configuration will be examined. First, for convenience of explanation, the case where full screen display is performed, that is, the first partial display control signal PD
1 is always assumed that it is H level. In this case, the voltage waveform of the scanning signal is as shown in FIG. That is, the start pulse YD is sequentially shifted for each horizontal scanning period 1H by the clock signal YCLK, is output as the transfer signals YS1 to YS200, and the second half period of the one horizontal scanning period 1H is selected by the control signal INH. , And the AC drive signal M in the latter half period.
Since the selection voltage of the scanning signal is determined according to the level of Y, the voltage of the scanning signal supplied to one scanning line is set in the latter half of the horizontal scanning period in which the scanning line is selected.
If the AC drive signal MY is at the H level, for example, it becomes the positive-side selection voltage VSP, and then holds the positive-side non-selection voltage VHP corresponding to the selection voltage. After the lapse of one frame, in the latter half of one horizontal scanning period, the level of the AC drive signal MY is inverted to the L level, so that the voltage of the scanning signal supplied to the scanning line is negative selection. Voltage V
SN, and thereafter, the negative non-selection voltage VHN corresponding to the selection voltage is held. For example, as shown in FIG. 5, the voltage of the scanning signal Y1 of the scanning line selected first in a certain n-th frame becomes the positive-side selection voltage VSP in the latter half of the horizontal scanning period, and thereafter, the non-selection voltage VHP is held, and in the next (n + 1) th frame, a cycle is repeated in which the negative selection voltage VSN is maintained in the latter half of the first horizontal scanning period, and then the negative nonselection voltage VHP is held.

On the other hand, since the signal level of the AC drive signal MY is inverted every horizontal scanning period 1H, the polarity of the voltage of the scanning signal supplied to the adjacent scanning line is alternately changed every horizontal scanning period 1H. The relationship is reversed. For example, as shown in FIG. 5, if the voltage of the scanning signal Y1 to the scanning line selected first in a certain n-th frame is the positive selection voltage VSP in the latter half of the horizontal scanning period, 2
The voltage of the scanning signal Y2 to the scanning line selected at the end is the negative selection voltage VSN in the latter half of the horizontal scanning period.
Becomes

Next, a scan signal in the case of performing partial display will be discussed. Here, as an example, a partial display as shown in FIG. 6, specifically, in the liquid crystal panel 100, a pixel area scanned by the 1st to 80th scanning lines counted from the top and the 121st to 200th scanning lines It is assumed that a pixel region scanned by a line is a non-display region, and a partial display in which a pixel region scanned by the 81st to 121st scan lines is a display region is performed.

Also in the case of partial display, the start pulse Y
D is one horizontal scanning period 1H by the clock signal YCLK.
The transfer signals YS1 to YS2 are sequentially shifted every time.
The point output as 00 is the same as in the case of full screen display. However, the first partial display control signal PD1 is, as shown in FIG.
In the 180th horizontal scanning period, the transfer signals YS1 to YS80 corresponding to the 0th and next frames are at the L level during a total of 160 horizontal scanning periods in which the 1st to 80th scanning lines are selected. And Y
S121 to YS200 transition to the H level,
When the control signal INH becomes H level, the voltage levels of the scanning signals supplied to the 1-80th and 121-200th scanning lines are changed from the non-selection voltage VHP to VHN or from the non-selection voltage VHN to VHP. Will be switched.

On the other hand, the first partial display control signal PD1 is 1
Of the vertical scanning periods, from the H level in the meter 40 horizontal scanning periods 81-120 -th scanning line is selected, in the 40 horizontal scanning period, the scanning signal supplied to the 81-120 -th scan line In other words, it is the same as the case of full screen display.

Therefore, the scanning signal for performing the partial display as shown in FIG. 6, particularly the scanning signal supplied to the scanning line near the boundary between the non-display area and the display area, is as shown in FIG. Becomes That is, non-display areas 1 to 8
The scanning signals Y1 to Y80 and Y121 to Y200 to the 0th scanning line and the 121st to 200th scanning lines are respectively applied from one of the non-selection voltages VHP and VHN to the other during the horizontal scanning period of the corresponding scanning line. Can be switched. For this reason, in the present embodiment, the polarity of the non-selection voltage of the scanning signal to the non-display area is inverted every frame.

Here, from the standpoint of reducing power consumption only, it is desirable that the scanning signal to the non-display area be an intermediate voltage between the voltages VDP and VDN applied as the data signal. Now, the drive voltage forming circuit 5
00 (see FIG. 1) not only needs to separately form an intermediate voltage, but also requires an extra number of bits in the voltage selection signal by the voltage selection signal forming circuit 3504 (see FIG. 4). Since the selection range is widened, the configuration becomes complicated. On the other hand, according to the present embodiment, the configuration itself is not much different from the conventional configuration in which only full-screen display is performed, so that complication of the configuration is prevented. In addition, since the scanning signal to the non-selection area is generated only by switching the low voltage of the non-selection voltage at an extremely long interval of 1 V corresponding to one frame, the scanning line is used when the partial display is performed. The power consumed by the drive circuit 350 can be suppressed as low as the configuration for supplying the intermediate voltage of the data signal.

The switching interval of the non-selection voltage is
In the present embodiment, the period is 1 V corresponding to one frame. However, when the interval is longer, the power consumption due to switching is suppressed. For this reason, the switching interval of the non-selection voltage is 2 as shown in FIG.
The voltage may be 2 V corresponding to a frame or a longer period. However, fixing the scanning signal to the non-display area to one of the non-selection voltages VHP and VHN is not preferable in a display device on the premise of AC driving.

On the other hand, the scanning signals Y81 to Y120 to the 81st to 120th scanning lines, which are the display areas, become one of the selection voltages VSP and VSN in the latter half of the horizontal scanning period, and then become non-selected corresponding to the selection voltage. The cycle of holding the selection voltage, setting the other selection voltage in the latter half of the horizontal scanning period after the lapse of one frame, and then setting the non-selection voltage corresponding to the selection voltage is repeated. Therefore, regarding the scanning signal supplied to the scanning line in the display area, there is no difference from the conventional configuration in which only the full-screen display is performed. There is no problem that the display quality is deteriorated as compared with the screen display.

<Data Line Driving Circuit> Next, details of the data line driving circuit 250 will be described. FIG. 9 is a block diagram showing a configuration of the data line driving circuit 350. In this figure, an address control circuit 2502 is for generating a row address used for reading out display data, resetting the row address by a start pulse YD supplied at the beginning of one frame, and resetting the row address for one horizontal line. The configuration is such that a step is made by a latch pulse LP supplied every scanning period. However, the first partial display control signal P
When D1 goes low, the address control circuit 2502
Prohibits the supply of row addresses.

The display data RAM 2504 has 200 rows ×
This is a dual port RAM having an area corresponding to pixels arranged in 160 columns.
Is written at a predetermined address, while the read side reads display data of an address specified by a row address for one row.

Next, the PWM decoder 2506 is for performing pulse width modulation on the data signal in accordance with the gradation, and outputs a voltage selection signal for selecting the voltage of the data signals X1 to X160 in accordance with the display data. It is generated for each data line 212 from the AC drive signal MX, the reset signal RES, and the gradation code pulse GCP. Here, in the present embodiment, the voltage of the data signal applied to the data line 212 is
VDP (positive data voltage), VDN (negative data voltage)
Are two values. In this embodiment, the display data is 3 bits (8 gradations).

First, when the first partial display control signal PD1 is at the H level, the PWM decoder 2506 generates a voltage selection signal so that the voltage level of the data signal has the following relationship. That is, the voltage level of the data signal becomes firstly opposite to the level of the AC drive signal MX by the reset signal RES supplied at the beginning of one horizontal scanning period, and secondly, it corresponds to the display data. At the rise of the gradation code pulse GCP, P is inverted to the same level as the AC drive signal MX.
The WM decoder 2506 generates a voltage selection signal. FIG.
0 indicates a binary representation of the display data signal input to the PWM decoder 2506, and a voltage selection signal resulting from decoding the display data signal. However, the PWM decoder 2506
Is the AC drive signal M if the display data is (000).
The PWM decoder 2506 generates a voltage selection signal so that X has an inverted level, and if the display data is (111), it has the same level as the AC drive signal MX.

Next, when the first partial display control signal PD1 is at the L level, the PWM decoder 2506 generates a voltage selection signal so that the voltage level of the data signal has the following relationship. When the second partial display control signal PD2 is at the L level, the PWM decoder 2506 changes the voltage level of the data signal from one of the positive data voltage VDP and the negative data voltage VDN to the other regardless of the display data.
A voltage selection signal is generated such that the voltage selection signal is inverted every predetermined period. On the other hand, when the second partial display control signal PD2 is at the H level, the PWM decoder 2506 generates a voltage selection signal with a data value of (000) regardless of the supplied display data. Well, selector 2508
Is to actually select the voltage indicated by the voltage selection signal from the PWM decoder 2506 and supply it to each of the corresponding data lines 212.

<Voltage Waveform of Data Signal> Next, the data signal supplied by the data line driving circuit 250 having the above configuration will be examined. First, for convenience of description, it is assumed that full screen display is performed, that is, a case where the first partial display control signal PD1 is always at the H level. In this case, the voltage waveform of the data signal Xi (i is an integer satisfying 1 ≦ i ≦ 160) is as shown in FIG. That is, if the display data is other than (000) or (111), P
By the voltage selection signal of the WM decoder 2506, the voltage level of the data signal Xi is reset to the level of the AC drive signal MX and the inverted level by the reset signal RES supplied at the beginning of one horizontal scanning period, and corresponds to the display data. At the rise of the gradation code pulse GCP, it is inverted to the same level as the AC drive signal MX. However, the voltage level of the data signal Xi is (000)
If the display data is (111), the AC drive signal MX is inverted.
Is made the same level. Therefore, the data signal Xi
As shown in the figure, in the period 1H corresponding to one horizontal scanning period, the period of the positive data voltage VDP and the period of the negative data voltage VDN are equal to each other regardless of the display data, as shown in the figure. .

In the latter half of one horizontal scanning period, the AC drive signal MX for defining the polarity of the data signal is:
Since the AC drive signal MY that defines the polarity of the scanning signal is set to the inversion level in the latter half period, it is also understood that the data signal Xi corresponds to the polarity of the scanning signal.

Next, the data signal Xi when performing partial display will be discussed. Here, too, a partial display as shown in FIG. 6 is assumed. In the following description, a certain area of the non-display area B that is adjacent to the display area A is referred to as a first non-display area B1.
The area obtained by subtracting the non-display area B1 is referred to as a second non-display area B2.
I will call it.

In this case, the first partial display control signal PD1
Is 81 out of one frame as shown in FIG.
It becomes H level in a total of 40 horizontal scanning periods in which the 120th to the 120th scanning line is selected. On the other hand, the 1st to 80th and 1st
It becomes L level in a total of 160 horizontal scanning periods in which the 21st to 200th scanning lines are selected.

In the period in which the first partial display control signal PD1 is at the H level, that is, in the period in which the scanning lines included in the display area A are selected, it can be regarded as the above-described full-screen display. Is in accordance with the AC drive signal MX and the display data. FIG.
This indicates this in the region a. Therefore, according to such a data signal Xi, in one horizontal scanning period, the period of the positive data voltage VDP and the period of the negative data voltage VDN are equal to each other, so that the first partial display control signal PD1 is Also during the H-level period, the period during which the positive data voltage VDP and the period during which the negative data voltage VDN is obtained are equal to each other.

Next, during the period when the first partial display control signal PD1 is at L level and the second partial display control signal PD2 is at L level, that is, the scanning lines included in the second non-display area B2 are selected. Consider a period of time. During this period, the voltage of the data signal Xi is
6, regardless of the display data, as shown in FIG. 11, the positive data voltage VDP or the negative data voltage VDP.
From one side of DN to the other, 35 horizontal scanning periods 35H obtained by dividing the total 140 horizontal scanning periods of the L level by “4”
It is inverted every time. Also in this period, it can be seen that the period during which the positive side data voltage VDP becomes equal to the period during which the negative side data voltage VDN is obtained.

Next, during the period when the first partial display control signal PD1 is at the L level and the second partial display control signal PD2 is at the H level, that is, the scanning lines included in the first non-display area B1 are selected. Consider a period of time. During this period, the voltage of the data signal Xi is
6 outputs the same voltage selection signal as the display data of the data value (000). As a result, the data signal Xi matches the inverted version of the AC drive signal MX, and its cycle is 1
The horizontal scanning period is 1H. The area b shown in FIG. 11 indicates this.

Now, the effective voltage waveform X of the data signal Xi
Although i ′ fluctuates greatly during the period corresponding to the second non-display area as shown in FIG. 11, the intermediate voltage of the positive data voltage VDP and the negative data voltage VDN during the period corresponding to the first non-display area. Converges to the reference voltage VR.
At the start of the display period, the effective voltage waveform Xi takes the reference voltage VR. As a result, the effective value of the data signal Xi can be maintained at the reference voltage VR over the entire display period, even in the case of partial display, as in the case of full screen display. As a result, the image quality in the display area A can be improved.

Here, from the viewpoint of reducing power consumption only, the voltage of the data signal Xi during the period in which the scanning line included in the non-display area B is selected is equal to the reference voltage V.
In this configuration, the drive voltage forming circuit 500 (see FIG. 1) not only needs to separately form the reference voltage VR, but also has a PWM decoder 2506.
The number of bits is additionally required in the voltage selection signal (see FIG. 9), and the selection range of the selector 2508 is expanded, so that the configuration is complicated. On the other hand, according to the present embodiment, the configuration itself is not much different from the conventional configuration in which only full-screen display is performed, so that complication of the configuration is prevented. Then, the data signal Xi during the period when the scanning line in the non-selected area is selected is the positive data voltage VDP.
Alternatively, since the negative data voltage VDN is generated only by switching every 30 horizontal scanning periods, which is much longer than the case where the scanning line of the display area is selected, the data line driving circuit is used in the case of performing partial display. 2
The power consumed by the power supply 50 can be suppressed as low as the configuration for supplying the reference voltage VR.

Further, when the first partial display control signal PD1 is at L
In the case of the level, in the present embodiment, as described above, the supply of the row address from the address control circuit 2502 is prohibited. Here, during a period in which the first partial display control signal PD1 is at the L level, no display is performed during that period, and thus display data is unnecessary. Therefore, the first partial display control signal PD
1 is at the L level, the PWM decoder 250
6 may ignore the display data read from the display data RAM, but if the supply of the row address is actively prohibited as in the present embodiment, the power consumed for reading the display data is also reduced. It can be suppressed.

Similarly, when the first partial display control signal PD1 is L
In a certain level period, no display is performed in that period, so that the gradation code pulse GCP is unnecessary. Therefore, a configuration in which the PWM decoder 2506 simply ignores the gradation code pulse GCP is sufficient. However, the gradation code pulse GCP, as described above,
In the half horizontal scanning period, the high-frequency oscillation circuit 4006
Is a signal obtained by arranging high-frequency pulse signals according to the weight of the display data indicating the gray scale, so that the frequency is much higher than other clock signals and control signals serving as a 水平 horizontal scanning reference. High. For this reason, the power consumed due to the wiring capacitance and the like is often not negligible as a whole.

On the other hand, according to the present embodiment, when the first partial display control signal PD1 is at the L level, as described above, the control signal drive circuit 4002 (see FIG. 3) operates as shown in FIG. Since the generation of the grayscale code pulse GCP is actively stopped with respect to 4006, the power consumed due to the wiring capacitance and the like,
It is also possible to suppress the power consumed by the operation according to the gradation code pulse GCP.

<Others> In the above embodiment,
As shown in FIG. 11, in 10 horizontal scanning periods 10H before and after 40 horizontal scanning periods 40H corresponding to the display area A,
The data signal is inverted every horizontal scanning period. However, the present invention is not limited to this. The data signal is inverted by one horizontal scanning only in 10 horizontal scanning periods 10H before 40 horizontal scanning periods 40H. The inversion may be performed every period. That is, the first non-display area B shown in FIG.
1 (B1u) adjacent to the upper side of the display area A
May be set as the first non-display area B1, and the lower adjacent part (B1d) may be included in the second non-display area B2.

In the above-described embodiment, during the period in which the scanning line belonging to the second non-display area B2 is selected (second period), the signal level of the data signal is inverted every 35 horizontal scanning periods. On the other hand, in the period (first period) in which the scanning line belonging to the first non-display area B1 is selected, 1
Although the signal level of the data signal is inverted every horizontal scanning period, the present invention uses the effective value of the data signal as the reference voltage V
In order to approach R, the data signal is inverted every horizontal scanning period in the first period. The shorter the inversion cycle of the data signal, the smaller the amplitude of the effective voltage waveform. Therefore, in order to converge the effective value of the data signal, it is sufficient that the inversion cycle of the data signal in the first period is shorter than the inversion cycle of the data signal in the second period.

[0074] In the embodiment described above, the element substrate 200 of the liquid crystal panel 100, a transparent insulating substrate such as glass, here, to form a two-terminal switching element such as a TFD, a pixel 116 Although it was configured to drive,
The present invention is not limited to this. For example, a TFT (Thin Film Transistor) in which a silicon thin film is formed on the substrate and a source, a drain, and a channel are formed in the thin film.
The pixel 116 may be driven by a tor (thin film transistor). Further, for example, the element substrate 200 may be a semiconductor substrate, and the driving element of the pixel 116 may be an insulated gate field effect transistor having a source, a drain, and a channel formed on the surface of the semiconductor substrate. In this case, the pixel electrode 234 is formed of a reflective electrode made of a metal such as aluminum, and is used as a reflective type. Further, the element substrate 101 may be a transparent substrate, or the pixel electrode 234 may be made of a reflective metal to be of a reflective type.

However, in the configuration in which the pixel 116 is driven by the transistor, not only one of the data line 212 and the scanning line 312 but also both of the data line 212 and the scanning line 312 need to be formed on the element substrate 200 so as to cross each other. In addition, the TFT is disadvantageous in that the configuration of the TFT itself is more complicated than that of the TFD, so that the manufacturing process is complicated. Further, in the embodiment, the display device using liquid crystal as an electro-optical material has been described as an example, but electroluminescence, a fluorescent display tube,
The present invention is applicable to a display device that performs display by an electro-optic effect, such as a plasma display. That is, the present invention
The present invention is applicable to all electro-optical devices having a configuration similar to that of the above-described liquid crystal display device.

<Electronic Apparatus> Next, a case where the above-described display device is applied to a portable electronic apparatus will be described. In this case, as shown in FIG. 12, the electronic device mainly includes a display information output source 1000, a display information processing circuit 1002, a drive circuit 1004, a liquid crystal panel 100, and a clock generation circuit 1.
008 and a power supply circuit 1010. The display information output source 1000 is a ROM (Read Onl
y Memory), RAM (Random Access Memory) and other storage units, such as optical disk drives,
It includes a tuning circuit for tuning and outputting an image signal, and outputs display information such as an image signal in a predetermined format to the display information processing circuit 1002 based on a clock signal from the clock generation circuit 1008. The display information processing circuit 1002 has a higher-level configuration including the control circuit 400 in FIG. 1, and further includes a well-known circuit such as a serial-parallel conversion circuit, an amplification / polarity inversion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit. A digital signal is sequentially generated from display information input based on a clock signal, including various processing circuits, and the driving circuit 100 generates a digital signal together with a timing signal such as a clock signal CLK and a control signal.
4 is output. Further, the drive circuit 1004 corresponds to the above-described data line drive circuit 250, scan line drive circuit 350, control circuit 400, and the like, and further includes an inspection circuit used for inspection in a manufacturing process. The power supply circuit 1010 supplies a predetermined power to each circuit. Here, the power supply circuit 1010 has a concept including the above-described drive voltage forming circuit 500.

<Cellular Phone> Next, an example in which the above-described display device is applied to a cellular phone will be described. FIG. 13 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1300 includes a plurality of operation buttons 1302, an earpiece 1304, a mouthpiece 1306, and a liquid crystal panel 1
00 is provided. In this liquid crystal panel 100,
When an incoming call or outgoing call is made, full screen display is performed with the entire area as the display area, while in standby mode, partial display is performed with only the area that displays necessary information such as electric field strength, numbers, characters, etc. Become. Thus, the power consumed by the display device during standby can be reduced, so that the standby time can be lengthened.

In some cases, the electronic apparatus to which the display device according to the present embodiment is applied needs to display a full screen, but in other cases, it is possible to display only a partial area. Devices that have a strong demand for low power consumption, such as the above-described mobile phone, a pager,
A clock, a PDA (personal information terminal) and the like are suitable.
However, besides this, it is also applicable to LCD TVs, viewfinder type, monitor direct view type video tape recorders, car navigation devices, calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, etc. It is possible.

[0079]

As described above, according to the present invention, it is possible to reduce the power consumption and to simplify the structure of the display device while suppressing the occurrence of image quality deterioration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a display device according to an embodiment of the present invention.

FIG. 2 is a partially cutaway perspective view showing a configuration of a liquid crystal panel.

FIG. 3 is a block diagram illustrating a configuration of a control circuit.

FIG. 4 is a block diagram illustrating a configuration of a scanning line driving circuit.

FIG. 5 is a timing chart for explaining an operation of the scanning line driving circuit.

FIG. 6 is a plan view illustrating a partial display in the liquid crystal panel.

FIG. 7 is a timing chart showing a voltage waveform of a scanning signal in the case of partial display.

FIG. 8 is a timing chart showing a voltage waveform of a scanning signal in the case of partial display.

FIG. 9 is a block diagram illustrating a configuration of a data line driving circuit.

FIG. 10 is a timing chart for explaining an operation of the data drive circuit.

FIG. 11 is a timing chart showing a voltage waveform of a data signal in the case of partial display.

FIG. 12 is a block diagram illustrating a schematic configuration of an electronic apparatus to which the display device according to the embodiment is applied.

FIG. 13 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the display device is applied.

FIG. 14 is a timing chart showing a driving waveform of a display panel in a conventional partial driving method.

[Explanation of symbols]

 100 liquid crystal panel 116 pixel 118 liquid crystal layer 200 element substrate 212 data line 220 TFD 222 first conductor 224 insulator 226 second conductor 234 ... Pixel electrode 250 Data line drive circuit 300 Counter substrate 312 Scan line 350 Scan line drive circuit 400 Control circuit 500 Drive voltage forming circuit 600 Power supply circuit 2504 Display data RAM 4006 high-frequency oscillation circuit 4008 gradation control signal generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 621 G09G 3/20 621D 621K 623 623C F-term (Reference) 2H093 NA16 NA34 NA46 NA56 NB11 NC37 NC38 NC39 ND09 ND39 5C006 AC02 AC24 AC27 AF31 AF42 AF68 AF69 AF71 BB17 BC03 BC07 BC13 EC13 FA04 FA05 FA47 5C080 AA10 BB05 CC10 DD26 EE29 EE32 FF07 JJ01 JJ02 JJ04 JJ07 KK07

Claims (10)

[Claims] 1. A method for driving a matrix display device, wherein pixels provided at respective intersections of a plurality of scanning lines and a plurality of data lines are driven by switching elements, wherein: A display area including a part of the scanning lines is set to a display state, and a first non-display area including another scanning line and adjacent to the display area and a second non-display area adjacent to the first non-display area. And supplying a non-selection signal for turning off the switching element to each of the scanning lines belonging to the first non-display area and the second non-display area to the data line. The polarity is inverted every one or more vertical scanning periods based on the intermediate value of the signal to be supplied, and when a scanning line belonging to the second non-display area is selected, the signal amplitude is applied to each of the data lines Based on the intermediate value of A data signal comprising a positive voltage level and a negative voltage level is supplied with its polarity inverted in a first cycle based on the intermediate value thereof, and when a scan line belonging to the first non-display area is selected, A data signal comprising the positive side voltage level and the negative side voltage level is supplied to each of the data lines with its polarity inverted in a second cycle shorter than the first cycle with respect to an intermediate value thereof. the driving method of a matrix type display device according to. 2. The method according to claim 1, wherein the second period is one horizontal scanning period period. 3. A selection signal for turning on the switching element in one period obtained by dividing one horizontal scanning period for each of the scanning lines belonging to the display area, and a period other than the one period includes: 2. The matrix according to claim 1, wherein a non-selection signal for turning off the switching element is supplied with a polarity inversion every predetermined period based on an intermediate value of a signal supplied to the data line. Method of driving the display device. 4. The polarity inversion cycle of the positive voltage level and the negative voltage level when a scanning line belonging to the second non-display area is selected is determined by the number of scanning lines belonging to the second non-display area. 2. The driving method of a matrix type display device according to claim 1, wherein the horizontal scanning period is a period of substantially a quotient divided by an integer of 2 or more. 5. A matrix type display device in which pixels provided corresponding to respective intersections of a plurality of scanning lines and a plurality of data lines are driven by switching elements, wherein a part of the plurality of scanning lines is provided. While the display area consisting of the scan lines is in a display state, and the first non-display area consisting of other scan lines and adjacent to the display area and the second non-display area adjacent to the first non-display area are not displayed. A signal supplied to the data line for each of the scanning lines belonging to the first non-display area and the second non-display area, the non-selection signal causing the switching element to be non-conductive. A scanning line driving circuit for supplying a polarity inversion every one or more vertical scanning periods based on an intermediate value of the scanning line driving circuit, and when a scanning line belonging to the second non-display area is selected, for each of the data lines, Intermediate value of signal amplitude And a data signal composed of a positive voltage level and a negative voltage level based on the first non-display area is supplied with the polarity inverted in a first cycle based on an intermediate value thereof, and a scanning line belonging to the first non-display area is selected. In some cases, a data signal composed of the positive voltage level and the negative voltage level is supplied to each of the data lines with a polarity inverted in a second cycle shorter than the first cycle based on an intermediate value thereof. A matrix type display device comprising a data line driving circuit. 6. The matrix according to claim 5, wherein said scanning line driving circuit alternately inverts the polarity of a non-selection signal supplied to adjacent scanning lines based on said intermediate value. Type display device. 7. The data line driving circuit includes a memory having an area corresponding to the pixel, and when a scan line belonging to the display area is selected, reads out display data from the memory and stores the read data in the display data. And generating a signal comprising the positive side voltage level and the negative side voltage level, and reading out from the memory when a scanning line belonging to the first non-display area and the second non-display area is selected. 6. The matrix-type display device according to claim 5, wherein the display is stopped. 8. The switching element is a two-terminal switching element; the matrix type display device includes an electro-optic material sandwiched between a pair of substrates; and the pixel is one of the pair of substrates. The two-terminal switching element and the electro-optical material are connected in series between a plurality of scanning lines provided on one substrate and a plurality of data lines provided on the other substrate. A matrix-type display device according to claim 5. 9. The matrix according to claim 8, wherein said two-terminal switching element has a conductor / insulator / conductor structure connected to one of said scanning line and said data line. type display device. 10. An electronic apparatus comprising the matrix type display device according to claim 5.