JP2002196067A - Frequency modulation data determining device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To carry out high performance computing for input signal frequency modulation determination, a chirp inclination (frequency fluctuation ratio), the number of encoding phase modulation bits and the like without causing any frequency error due to temperature fluctuation. SOLUTION: This frequency modulation data determination device is provided with a DRFM circuit sampling an input signal and storing a digital amplitude value measured by this sampling, a reading circuit sequentially reading the digital amplitude values stored in the DRFM circuit and outputting them in time sequence, an amplitude memory circuit storing the digital amplitude values outputted from the reading circuit in time sequence, and a frequency modulation data computing circuit determining frequency modulation data of the input signal on the basis of the digital amplitude values stored in the amplitude memory circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency modulation specification judging device which receives radio waves from a radar or the like and judges frequency modulation specifications.

[0002]

2. Description of the Related Art FIG. 12 shows a conventional IF signal frequency measuring device (IFM: Instantaneous Frequancy Measurement).
1 is an input terminal for inputting an IF signal, 17 is a duplexer for distributing an input signal to a plurality of delay circuits, and 18 to 21 are delay lengths of 1: m: m ² : m, respectively. ³ , a delay circuit, 22 is a phase detector, 23 is a frequency calculation circuit, and 24 is an output terminal.

Next, the operation of the conventional example shown in FIG. 12 will be described. The radio wave input to the input terminal 1 is split by the splitter 17 into eight signal lines, of which four signals are output to the delay circuits 18-21. Each of the delay circuits gives a predetermined time delay (1: m: m ² : m ³ ), and then outputs 4
It outputs to the two phase detectors 22.

The other four signals output from the demultiplexer 17 are directly output to four phase detectors 22. Phase detector 2
Numeral 2 compares the direct signal from the duplexer 17 with the delayed waves from the delay circuits 18 to 21 to detect the phase difference between the sine waves. Next, the frequency calculation circuit 23 calculates a frequency value from the phase difference information output from each phase detector 22 and outputs the frequency value to the output terminal 24.

FIG. 22 shows an example of a configuration of a conventional IF signal intra-pulse frequency modulation measuring apparatus, particularly in a case where intra-pulse frequency modulation using a channelized receiver is determined. In the figure, 1 is an input terminal for inputting an IF signal, 38
Is a duplexer that distributes an input signal to a plurality of filter circuits.
9 is a filter circuit having different center frequencies, and 40 is an A /
D converter, 41 is an instantaneous frequency calculation circuit for calculating an instantaneous frequency from the A / D converted signal, 42 is an instantaneous frequency storage memory for storing the instantaneous frequency, 43 is output information of each filter circuit converted into a digital value. , An intra-pulse modulation determining circuit 44 for performing intra-pulse (or CW signal) frequency modulation determination, and 44 is an intra-pulse modulation specification storage memory.

Next, the operation of the conventional example shown in FIG. 22 will be described. The radio wave input to the input terminal 1 is split into a plurality of signal lines by a splitter 38 and passes through filter circuits 39 having different center frequencies.

[0007] The IF signal that has passed through each filter is the characteristic of the filter (center frequency, bandwidth, filter pattern).
, The amplitude changes. That is, the amplitude of the passing output of a filter whose filter center frequency is close to the input signal does not decrease, but the amplitude of the passing output of a filter whose filter center frequency is far from the input signal decreases.

A signal passed through each filter is converted by an A / D converter 40
As a result, the amplitude value and the measurement time are converted into digital values.
Next, the instantaneous frequency calculation circuit 41 calculates the instantaneous frequency at the time from the amplitude value (digital value) after passing through each filter at the same time, and outputs the instantaneous frequency to the instantaneous frequency storage memory in pair with the time.

Next, an intra-pulse frequency modulation determination circuit 43
Calculates the chirp signal slope from the frequency change amount one unit time before at each time in the pulse, and outputs it to the intra-pulse modulation specification storage memory 44.

[0010]

Since the conventional frequency modulation specification judging device is constructed as described above, it is impossible to detect phase inversion of a waveform (encoded phase modulation of a Barker signal or the like). There was a point. The response characteristics of a plurality of filters should be uniform except for the center frequency (output amplitude value response characteristics corresponding to the relative frequency with respect to the center frequency). There has been a problem that a frequency calculation error increases and as a result, a modulation specification error increases. Further, there is a problem that the characteristics of the filter are affected by the temperature change of the device itself. In addition, the technique of sampling an input signal is about 500 kHz, and there has been a problem that sampling of a signal of several hundred MHz, such as an IF signal of a radar or the like, does not satisfy the purpose for the subsequent analysis.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and there is no occurrence of a frequency error due to a temperature change, frequency modulation determination of an input signal, chirp gradient (frequency change rate), code It is an object of the present invention to obtain a frequency modulation specification judging device for calculating the number of generalized phase modulation bits and the like with high performance.

[0012]

According to a first aspect of the present invention, there is provided a frequency modulation specification measuring apparatus which samples an input signal and stores a digital amplitude value measured by the sampling, and stores the digital amplitude value in the DRFM circuit. A readout circuit that sequentially reads out the read digital amplitude values and outputs the digital amplitude values in a time series, an amplitude memory circuit that stores the digital amplitude values output from the readout circuit in a time series, and a digital amplitude value stored in the amplitude memory circuit. And a frequency modulation specification calculation circuit that determines the frequency modulation specification of the input signal based on the

The frequency modulation specification determining circuit according to a second aspect of the present invention, in the frequency modulation specification calculating circuit according to the first aspect, calculates a time at which an amplitude value becomes zero from a plurality of the digital amplitude values. The frequency modulation data is determined based on the time.

The frequency modulation specification determining circuit according to a third aspect of the present invention is the frequency modulation specification calculating circuit according to the first aspect of the present invention, wherein a time at which an amplitude value has a peak value is calculated from a plurality of the digital amplitude values. The frequency modulation data is determined based on the time.

A frequency modulation specification determining circuit according to a fourth invention is the frequency modulation specification calculation circuit according to the first invention, wherein the first time at which the digital amplitude value becomes zero is:
Based on a change in a time difference from the second time at which the digital amplitude value becomes zero, phase inversion is detected to determine frequency modulation specifications.

A frequency modulation specification determining circuit according to a fifth invention is the frequency modulation specification calculation circuit according to the first invention, wherein the first time at which the digital amplitude value has a peak value, and the digital amplitude value Is to detect phase inversion based on a change in time difference from the second time at which a peak value is reached, and determine frequency modulation specifications.

The frequency modulation specification determining circuit according to a sixth invention is the frequency modulation specification calculation circuit according to the first invention, wherein the first time at which the digital amplitude value becomes zero is:
A change in time difference from a second time at which the digital amplitude value becomes zero, a time difference between a first time at which the digital amplitude value has a peak value, and a second time at which the digital amplitude value has a peak value. Is used to detect the inversion of the phase and determine the frequency modulation specifications.

According to a seventh aspect of the invention, there is provided a frequency modulation specification determining circuit, wherein the frequency modulation specification calculating circuit includes a period calculating circuit for calculating a period based on the digital amplitude value; An inversion estimating circuit for estimating the time and direction of the inversion of the phase based on the cycle calculated by the circuit; and a digital amplitude value at the same time as the inversion direction at the inversion time estimated by the inversion estimation circuit. And a circuit for comparing the calculated inversion direction to determine frequency modulation data.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a frequency measuring apparatus according to an embodiment of the present invention will be described with reference to the drawings. The first to tenth embodiments relate to an invention relating to a frequency measuring apparatus, and the first to eleventh embodiments relate to an invention relating to a frequency modulation specification determining apparatus.

In FIG. 1, reference numeral 1 denotes an input terminal for inputting an IF signal, and 2 denotes a DRFM (Digital RF M) for sampling an input signal input from the input terminal 1 at a high speed and storing an amplitude value.
emory) circuit, 3 is a timer, 4 is a readout circuit for sequentially reading the storage contents of the DRFM circuit 2 and outputting amplitude information together with time information, and 5 is a time-series storing information on the amplitude value and time output by the readout circuit 4 An FFT circuit for fast Fourier transforming the amplitude value and time stored in the amplitude memory 5, and an F memory 7 for storing values equal to or higher than a specified spectrum level after the fast Fourier transform.

Next, the operation will be described. When an IF signal is input to the input terminal 1, the DRFM circuit 2 samples the input signal at high speed, that is, measures the amplitude of the sine wave signal at specified time intervals, and obtains an n-bit digital value (n is an integer of 2 or more). ) And store it in digital memory. The sampling frequency at this time is twice or more the IF frequency bandwidth.

Next, the read circuit 4 immediately receives the DRFM signal.
The amplitude value stored in the circuit 2 is read and the timer 3
Is read and the amplitude value and the time are written to the amplitude memory 5 as a pair of data. At this time, the read circuit 4 sequentially updates the write address of the amplitude memory each time a pair of data is written to the amplitude memory 5.

When the above operation is repeated for a predetermined time (T), time-series amplitude and time information is input to the amplitude memory 5 as shown in FIG. The upper diagram of FIG. 2 shows input signals when the vertical axis represents amplitude and the horizontal axis represents time, and the input signals are sampled at predetermined times by the DRFM circuit 2 and the obtained amplitude values are shown in FIG. It is a figure below.

Next, the FFT circuit 6 performs a fast Fourier transform on the information in the amplitude memory 5. As a result of the fast Fourier transform,
If there is a frequency value equal to or higher than the specified spectrum level, this frequency value (if there is more than one) is output to the F memory 7 as the frequency value of the time (T). Thereby, the frequency value of the first time section (time 0 to T) is calculated. Similarly, the frequency values after the second time interval (time T to 2 × T) are calculated and sequentially output to the F memory.

As described above, according to the invention described in the first embodiment, the sine waveform of the input IF signal is reproduced by a digitized amplitude value sequence, and the frequency value of the original sine wave is time-divided. Each component is calculated separately, and since there is no element that fluctuates due to temperature conditions in the device, it is possible to discriminate sine wave components of multiple signals and to measure frequency with high reliability that is not affected by device temperature. It becomes possible.

Embodiment 2 FIG. In the first embodiment, the frequency value is calculated by subjecting the (amplitude value, time) of the amplitude memory 5 to fast Fourier transform. In the second embodiment, the zero point is detected and the cycle of the sine wave is calculated. The frequency is obtained by calculating and converting the frequency. FIG. 3 is a block diagram showing a frequency measuring apparatus according to the second embodiment. In the drawing, reference numeral 8 denotes a zero detection circuit connected to the amplitude memory 5 and 9 denotes a zero point history memory connected to the zero detection circuit 8. Reference numeral 10 denotes an F calculation circuit connected to the zero point history memory 9 and the F memory 7.

The operation of the second embodiment will be described. Until the data on the amplitude value and the time of the input IF signal is output to the amplitude memory 5, the configuration is the same as that of the frequency measuring apparatus described in the first embodiment. Next, the zero detection circuit 8 sets the section start time on the amplitude memory 5 (the time =
0) to the end time of the section (for the first time section, the time =
Until T), the time at which the sign changes from the amplitude value one unit time (sampling interval) earlier is searched for, and the calculation is performed by interpolating the cross point of zero amplitude.

The specific procedure is as follows. (1) Let t be a sample interval, and time 0, t, 2t
When the amplitude values in ... are P0, P1, and P2,
An m that satisfies Pm> 0 and Pm + 1 <0 is searched. (2) Approximate (Pm, m × t) and (Pm + 1, (m + 1) × t) with a straight line to calculate a time corresponding to zero amplitude. Zero point time = m × t + (t × Pm) / | Pm + 1−P
m ｜

The time obtained as the zero point time is sequentially output to the zero point history memory 9. Thus time 0
From the time T to the time T are stored. 0
Let the zero point times of ~ T be Z0, Z1, Z2 and then F
The calculation circuit 10 calculates the interval between the zero point times (Z1-Z
0, Z2-Z1,...), Calculate a frequency having a half cycle of these representative values (average value, median value, etc.), and output it to the F memory 7.

In the second embodiment, the output frequency in the time section (T) is one, but since the Fourier transform is not performed, the time section (T) is set smaller than in the first embodiment. It is possible to calculate the frequency for each subdivided section.

Embodiment 3 In the second embodiment, the DRF
Interpolating the zero cross point of the output of the M circuit 2,
Although the half cycle of the sine wave is converted to the frequency, in the third embodiment, the peak is detected and the cycle of the sine wave is calculated and converted to the frequency. FIG. 4 is a block diagram showing a frequency measuring apparatus according to the third embodiment. In the figure, reference numeral 11 denotes a peak detection circuit connected to the amplitude memory 5, reference numeral 12 denotes a peak history memory connected to the peak detection circuit 11, Reference numeral 13 denotes an F calculation circuit connected to the peak history memory 12.

The operation of the frequency measuring device according to the third embodiment will be described. The operation until the (amplitude value, time) data of the input IF signal is output to the amplitude memory 5 is the same as the operation of the frequency measuring apparatus described in the first embodiment. Next, the peak detection circuit 11 causes the section start time (the first
The sign of the difference from the amplitude value one unit time (sampling interval) has changed from the time = 0 in the case of the time section to the end time of the section (time = T in the case of the first time section). The time is searched and set as the maximum / minimum amplitude value point (peak point).

The time obtained as the peak point time is sequentially output to the peak history memory 12. In this way, all peak times from time 0 to time T are stored. The zero point times of 0 to T are defined as Z0, Z1, and Z2, and then the F calculation circuit 13 determines the interval between the maximum peak times (Z2-Z0, Z3-Z).
1, Z4-Z2,...), Calculate a frequency having a cycle of these representative values (average value, median value, etc.), and output it to the F memory 7.

Also in the case of the third embodiment, although the output frequency in the time section (T) is one, since the Fourier transform is not performed, T can be set smaller than that of the first embodiment. The frequency for each subdivided section can be calculated.

Embodiment 4 FIG. In the first embodiment, the frequency value is calculated by subjecting the (amplitude value, time) of the amplitude memory 5 to fast Fourier transform. In the fourth embodiment, a Kalman filter circuit is provided instead of the FFT circuit, and the sine wave is calculated. The wave period is calculated and converted to frequency. FIG.
Is a block diagram showing a frequency measuring apparatus according to the fourth embodiment. In the figure, reference numeral 14 denotes a Kalman filter circuit connected to the amplitude memory 5 and the F memory 7.

The operation of the frequency measuring device according to the fourth embodiment will be described. The operation until the (amplitude value, time) data of the input IF signal is output to the amplitude memory 5 is the same as the operation of the frequency measuring apparatus described in the first embodiment. Next, the Kalman filter circuit 14 calculates a sine wave period (Tk) from the amplitude data sequence by an extended Kalman filter using the following equation as an identification model. P = sin {(2πt / Tk) + α} The sine wave cycle Tk is converted into a frequency and output to the F memory 7.

As described above, since the frequency is calculated based on the digital amplitude value based on the Kalman filter circuit, the Fourier transform is not performed. Therefore, the time section (T) can be set small, and each of the subdivided sections can be set. The frequency can be calculated.

Embodiment 5 In the first embodiment, the amplitude value of one time section (time 0 to T) is stored in the single amplitude memory 5 and the frequency value is calculated by performing the fast Fourier transform. However, a plurality of amplitude memories 5 are provided. In the first amplitude memory, the amplitude values at times 0 to T are stored in the first amplitude memory, and at the time t
The amplitude value of T to t + t is stored as ‥‥, and each section (0 to T, t to T + t, 2 × t to T + 2 × t, ‥) is subjected to fast Fourier transform to calculate a frequency value for each section. Alternatively, a configuration may be adopted in which a frequency match between adjacent sections is detected, and the frequency values of both sections are detected. FIG. 6 is a block diagram showing a configuration of the frequency measuring device according to the fifth embodiment. In the figure, reference numeral 15 denotes a section F memory connected to the FFT circuit 6, 1
Reference numeral 6 denotes an adjacent F calculation circuit 16 connected to the section F memory 15 and the F memory 7.

The operation of the fifth embodiment will be described. Outputting the (amplitude value, time) data of the input IF signal to the amplitude memory 5 is the same as in the first embodiment. At this time, time 0 is output to the amplitude memory 1 and time t is output to the amplitude memories 1 and 2. I do. In this manner, the amplitude history from time 0 to time T is output to the amplitude memory 1, the amplitude history from time t to time T + t is output to the amplitude memory 2, and the time (i-1) × t to time T + is output to the amplitude memory i.
(I-1) × t amplitude history is output.

Next, the FFT circuit 6 converts the result of the fast Fourier transform of each section into the section F memory 15 as in the first embodiment.
Output to Next, when the calculation F of the adjacent section matches, the adjacent F calculation circuit 16 sets the frequency as a continuous section F.
Output to the F memory 7.

According to this embodiment, it is possible to reduce the influence of the frequency component of the specific portion and calculate the start and end times of the occurrence of each frequency component.

Embodiment 6 FIG. In the second embodiment, a zero cross point in one hour section (time 0 to T) is searched, and a representative value (average value, median value, etc.) of the zero cross point interval is set to 1
Although the frequency value was calculated from the number, as shown in FIG. 7, a plurality of section F memories 15 were provided, and the F representative values of times 0 to T were stored in the first section F memory, and the time F was stored in the second section F memory. t ~ T
The F representative value of + t may be stored as ‥‥, and thereafter the continuous section F may be calculated as in the fifth embodiment.

In this case, only by changing the number of samples for calculating the F representative value, the F accuracy and the noise reduction performance can be flexibly adjusted according to the performance of the DRFM.

Embodiment 7 FIG. In the third embodiment, the frequency value is calculated from one representative value (average value, median value, etc.) of the peaks (maximum value / minimum value, etc.) of the peak (maximum / minimum point) in one hour section (time 0 to T). However, as shown in FIG. 7, a plurality of section F memories 15 are provided, a first section F memory has F representative values at times 0 to T, a second section F memory has F representative values at times t to T + t, ‥‥ may be stored, and thereafter the continuous section F may be calculated as in the fifth embodiment.

In this case, just by changing the number of samples for calculating the F representative value as in the sixth embodiment, the F precision and the noise reduction performance can be flexibly adjusted according to the performance of the DRFM.

Embodiment 8 FIG. In the fourth embodiment, the amplitude value history of one time section (time 0 to T) is calculated as one frequency value using the extended Kalman filter.
, A plurality of amplitude memories 5 and a plurality of section F memories 15 are provided, and the first amplitude memory stores the amplitude values at times 0 to T, the second amplitude memory stores the amplitude values at times t to T + t, and
、, and each section (0 to T, t to T + t, 2
× t to T + 2 × t, ‥) by the extended Kalman filter to calculate a frequency value for each section, detect a frequency match between adjacent sections, and use the frequency value for both sections (after calculating the frequency for each section, (Similar to Embodiment 5).

Embodiment 9 FIG. In the fifth embodiment, one FFT circuit 6 sequentially calculates the frequency value of a plurality of sections and outputs each section frequency to the plurality of section F memories 15. However, as shown in FIG. 5, the same number of FFT circuits 6 as the section F memory 15 are provided, and as soon as the input to the corresponding amplitude memory 5 is completed, the fast Fourier transform is executed (while the output to the other amplitude memories is still being executed). ) May be adopted.

When this configuration is used, there is an effect that a plurality of fast Fourier transform processes are executed in parallel, and the frequency can be calculated at a high speed.

Embodiment 10 FIG. In the eighth embodiment, one Kalman filter circuit 14 sequentially calculates the frequency values of a plurality of sections, and stores each section frequency in a plurality of section F memories 1.
5, the same number of Kalman filter circuits 1 as the amplitude memory 5 and the section F memory 15 as shown in FIG.
4 as soon as the input to the corresponding amplitude memory 5 is completed.
The configuration may be such that each of the extended Kalman filterings is executed (while output to another amplitude memory is still being executed).

When this configuration is used, there is an effect that a plurality of extended Kalman filter processes are executed in parallel, and the frequency can be calculated at high speed.

Embodiment 11 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a block diagram showing a frequency modulation specification determining apparatus according to the eleventh embodiment. In FIG. 13, 1 is an input terminal for inputting an IF signal, 2 is a DRFM (Digital RF Memory) circuit for sampling an input signal at high speed and storing an amplitude value, 3 is a timer, 4
Is a reading circuit for sequentially reading the stored contents of the DRFM and outputting the amplitude information together with the time information, and 5 is an amplitude memory for storing (amplitude value, time) information output by the reading circuit in time series.

Reference numeral 6 denotes an FFT circuit for performing a fast Fourier transform of the (amplitude value, time) stored in the amplitude memory, 7 an F memory for storing, in a time series, a center value in a range equal to or higher than a specified spectrum level after the fast Fourier transform. Is a least squares approximation circuit for calculating a frequency change rate based on a model in which a time series (time, frequency) changes at a constant speed, and 26 is a chirp specification storage memory for storing a frequency change rate which is a least squares approximation result. is there.

Next, the operation will be described. When an IF signal is input to the input terminal 1, a DRFM (Digital RF Memor
y) samples the input signal at a high speed (measures the amplitude of the sine wave signal at specified time intervals), converts it into an n-bit digital value (n is an integer of 2 or more), and stores it in a digital memory.
The sampling frequency at this time is set to an integer multiple of the IF frequency bandwidth or more.

Next, the read circuit 4 immediately receives the DRFM signal.
And the time of the timer 3 is read at the same time, and (amplitude value, time) is written to the amplitude memory 5 as a pair of data. At this time, the read circuit 4 sequentially updates the write address of the amplitude memory each time a pair of data is written to the amplitude memory 5.

When the above operation is repeated for a predetermined time (T), time-series (amplitude, time) information is input to the amplitude memory 5 as in the example shown in FIG. Next, the FFT circuit 6
Performs a fast Fourier transform of the information in the amplitude memory 5. As a result of the fast Fourier transform, if there is a frequency value equal to or higher than the specified spectrum level, the center value of this frequency range is set as the frequency value of the center time of the time section (FFT target time zone) as F
Output to the memory 7.

For the sampling period Δt (Δt is the reciprocal of the sampling frequency), the first time interval (time 0
The center frequency (f1) of the frequency range of the FFT result of (.about.m.times..DELTA.t) is defined as the frequency value at time m.times..DELTA.t / 2. FF
The T circuit outputs this result to the F memory 7. The output content is (time: m × Δt / 2, frequency: f1).

The FFT circuit further includes a second time section (time Δ
t to (m + 1) × Δt), third time interval (time 2 × Δt)
高速 (m + 2) × Δt) and ‥‥ are also subjected to fast Fourier transform and are sequentially output to the F memory. Thus, in the F memory 7, (f1, m / 2 × Δt), (f2, (m +
1) / 2 × Δt), (f3, (m + 2) / 2 × Δt),
‥‥ is output.

Next, the least-squares approximation circuit 25 outputs the F memory 7
Is subjected to least squares approximation using the following equation as a model. Equation f = k × t + f0 f: frequency at time t f0: initial frequency value k: frequency change rate The least squares approximation circuit 25 uses the result of the least squares approximation (k in the above equation) as a chirp signal slope and stores chirp specification data. 26. If the input signal is a non-chirp signal, the chirp signal slope is set to zero.

As described above, according to the invention described in this embodiment, it is possible to determine the frequency modulation of an input signal without causing a frequency error due to a temperature change.

Embodiment 12 FIG. In the eleventh embodiment, the frequency value is calculated by subjecting the (amplitude value, time) of the amplitude memory 5 to fast Fourier transform and input to the least square approximation circuit at the subsequent stage. A point is detected and the cycle of a sine wave is calculated and converted to a frequency. FIG. 15 is a block diagram showing a frequency modulation specification determining apparatus according to the twelfth embodiment. In FIG.
Is a zero detection circuit, and 9 is a zero point history memory.

The operation of the frequency modulation specification determining apparatus according to Embodiment 12 will be described. The operation until the (amplitude value, time) data of the input IF signal is output to the amplitude memory 5 is the same as the operation of the frequency modulation specification determining apparatus described in the eleventh embodiment. Next, the zero detection circuit 8 performs one unit time from the section start time (time = 0 for the first time section) to the section end time (time = T for the first time section) on the amplitude memory 5. (Sampling interval) The time at which the sign changes from the previous amplitude value is searched, and the calculated value is obtained by interpolating the cross point of zero amplitude.

Specifically, the operation is performed as follows. (1) When the sample interval is t and the amplitude values at time 0, Δt, 2Δt} are P0, P1, and P2, Pm> 0, Pm +
Search for m where 1 <0. (2) (Pm, m × Δt), (Pm + 1, (m + 1) × Δt)
Is approximated by a straight line, and a time equivalent to zero amplitude is calculated. Zero point time = m × Δt + Δt × Pm / | Pm + 1−P
m ｜

The time obtained as the zero point time is sequentially output to the zero point history memory 9. Thus time 0
From the time T to the time T are stored. 0
The zero point time of T is set to Z0, Z1, Z2}, and then the least squares approximation circuit 25 performs the least squares approximation of the contents of the zero point history memory 9 using the following equation as a model.

Expression f = k × t + f0 f: frequency at time t f0: initial frequency value k: frequency change rate ti = (Zi−1 + Zi) / 2 fi = 1/2 (Zi−Zi−1)

The least squares approximation circuit 25 outputs the result of the least squares approximation (k in the above equation) to the chirp specification storage memory 26 as a chirp signal gradient. If the input signal is a non-chirp signal, the chirp signal slope is set to zero. In the twelfth embodiment, since Fourier transform is not performed as in the eleventh embodiment, T can be set smaller than that in the eleventh embodiment, and chirp specifications for each subdivided section can be calculated. .

Embodiment 13 FIG. In the twelfth embodiment, D
The zero-cross point of the RFM output is obtained by interpolation, and the chirp signal slope is calculated by the least squares approximation from the half cycle equivalent time (Zi-Zi-1) of the sine wave. As shown in FIG. A peak detection circuit 11 and a peak history memory 12 may be provided instead of the point history memory 9, and the chirp signal slope may be calculated from the time corresponding to one cycle of the sine wave by least square approximation.

The operation of the thirteenth embodiment will be described.
It is the same as the first embodiment until the (amplitude value, time) data of the input IF signal is output to the amplitude memory (5). Next, the peak detection circuit 11 sets a value of 1 between the segment start time (time = 0 for the first time segment) and the segment end time (time = T for the first time segment) on the amplitude memory (5).
The time at which the sign of the difference from the amplitude value before the unit time (sampling interval) has changed is retrieved, and is set as the maximum / minimum amplitude value point (peak point).

The time obtained as the peak point time is sequentially output to the peak history memory 12. In this way, all peak times from time 0 to time T are stored. The peak point times of 0 to T are defined as P0, P1, P2}, and then the least squares approximation circuit 25 performs the least squares approximation on the contents of the peak history memory 12 using the following equation as a model. At this time, the least squares approximation is performed on the time series of the minimum point and the time series of the maximum point, and the average value is used.

Equation f = k × t + f0 f: frequency at time t f0: initial frequency value k: frequency change rate ti = (Pi-1 + Pi) / 2 fi = 1 / (Pi-Pi-1)

The least squares approximation circuit 25 outputs the result of the least squares approximation (k in the above equation) to the chirp specification storage memory 26 as a chirp signal gradient.

When the input signal is a non-chirp signal, the chirp signal slope is set to zero. In the thirteenth embodiment as well, the Fourier transform as in the eleventh embodiment is not performed, so that T can be set smaller than that in the eleventh embodiment, and the chirp specifications for each subdivided section can be calculated. it can.

Embodiment 14 FIG. In the twelfth embodiment, D
The zero-cross point of the RFM output is obtained by interpolation, and the chirp signal slope is calculated by the least squares approximation from the half cycle equivalent time (Zi-Zi-1) of the sine wave. As shown in FIG. Chirp specification storage memory 2
If a period change detection circuit 27, a phase inversion point history memory 28, an encoded phase modulation determination circuit 29, and an encoded phase modulation specification storage memory 30 are provided instead of 6, a change in time series corresponding to a half cycle can be obtained. Upon detection, phased code modulation can be determined.

The operation of the fourteenth embodiment will be described.
(Amplitude value, time) data of the input IF signal is stored in an amplitude memory 5
To the zero point history memory 9 until the zero crossing time is output. Next, the cycle change detection circuit 27 determines a change (JUMP of the cycle value) of the sine wave for a half cycle. The determination method is as follows.

1. The half cycle equivalent time (Zi-Zi-1) is calculated for each i
Is calculated. (Calculate the first difference between the zero cross point times) Half cycle time difference [(Zi + 1−Zi) − (Zi−Zi−
1)] (Calculate the second difference between the zero crossing point times) If the absolute value of the half cycle time difference is equal to or greater than the specified value, it is determined that phase inversion has occurred during this period. (Zi ~ Zi-1 or
Zi + 1 to Zi) 4. A section where the difference from the half cycle time calculated in the vicinity is larger is set as the phase inversion occurrence time.

The cycle change detection circuit 27 obtains the phase inversion time in the above manner and outputs it to the phase inversion point history memory 28 (when inverted in the sections Zi to Zi-1, the center time of the section ((Zi + Zi-1) / 2) ) Is output as the change point time. Next, the encoded phase modulation determination circuit 29 outputs the phase inversion time interval to the encoded phase modulation specification storage memory 30.

According to the invention described in this embodiment, since the Fourier transform is not performed, T can be set smaller than that in the first embodiment, and the chirp specifications for each subdivided section can be calculated. Can be.

Embodiment 15 FIG. In the fourteenth embodiment, D
The zero cross point of the RFM output is obtained by interpolation, the JUMP of the time-series period value is determined from the half-cycle equivalent time (Zi-Zi-1) of the sine wave, and the phase inversion time is calculated.
As shown in FIG. 8, a peak detection circuit 11 and a peak history memory 12 are provided in place of the zero detection circuit 8 and the zero point history memory 9 to detect a change in a sine wave in a time series corresponding to one period of time, and Coding modulation can be determined.

The operation of the fifteenth embodiment will be described.
(Amplitude value, time) data of the input IF signal is stored in an amplitude memory 5
Is the same as that of the third embodiment until the maximum and minimum points of the amplitude are determined and output to the peak history memory 12. Next, the cycle change detecting circuit 27 changes the time corresponding to one cycle of the sine wave (minimal to minimal, maximum to maximum change (JUM of cycle value).
P) is determined. The determination method is as follows.

1.1 The period corresponding to the period (Pi−Pi−1) is calculated for each i
Is calculated. (Calculate the first-order difference of peak point time) 2.1 Difference of cycle time [(Pi + 1−Pi) − (Pi−Pi−
1)] (Calculate the second difference between the peak point times) 3. If the absolute value of the one-cycle time difference is equal to or greater than a specified value, it is determined that phase inversion has occurred during this period. (Pi ~ Pi-1 or P
i + 1 to Pi) 4. A section where the difference from the one cycle time calculated in the vicinity is larger is set as the phase inversion occurrence time. The cycle change detection circuit 27 obtains the phase inversion time in the manner described above and outputs it to the phase inversion point history memory 28 (section Pi).
To the time of the center of the section ((Pi + Pi-
1) / 2) is output as the change point time. Next, the encoded phase modulation determination circuit 29 outputs the phase inversion time interval to the encoded phase modulation specification storage memory 30.

According to the invention described in this embodiment, since the Fourier transform is not performed, T can be set smaller than that in the first embodiment, and the chirp specifications for each subdivided section can be calculated. Can be.

Embodiment 16 FIG. In the fourteenth and fifteenth embodiments, a half cycle or one cycle is calculated from the interval of only the zero cross point or only the peak point.
Although the phase inversion point is determined from the UMP point, as shown in FIG. 19, both the zero detection circuit 8 and the peak detection circuit 9 are held in parallel, and the zero point history memory 9 and the peak history memory 12 are used instead. A 1 / 2π time memory 31 is provided, and the zero cross point and the minimum / maximum point times are stored in the 1 / 2π time memory 31 in the order of appearance,
The phase inversion time is determined from the period value JUMP of 1 / 2π,
The encoding phase modulation data may be calculated.

According to this embodiment, the time error of the phase determination time is １ ／ of that in the fourteenth and fifteenth embodiments.
Can be reduced.

Embodiment 17 FIG. In the fourteenth embodiment, a point where the difference between the half cycle values of adjacent sine waves detected by the zero cross point is equal to or larger than a specified value is set as a phase inversion point in all of the target time segments. However, as shown in FIG. 32, a cycle extrapolation circuit 33, a cross point estimation memory 34, and a cross direction inversion determination circuit 35, and in a part of the target time section, the difference of the half cycle value is continuously less than the specified value in the time section. The arithmetic mean is calculated, and the subsequent zero crossing point estimation time is calculated by extrapolation,
The point of cross direction inversion (measured value − → + with respect to estimated value + → −) may be determined as the phase inversion time.

The operation of the seventeenth embodiment will be described.
Embodiment 4 is the same as Embodiment 4 until the (amplitude value, time) data of the input IF signal is output to the amplitude memory (5) and the zero-cross time is output to the zero point history memory 9. Next, the cycle change detection circuit 27 continuously calculates a time interval (T1 to T2) in which the half cycle difference is within a specified value, and outputs it to the cycle calculation circuit 32.

Next, the cycle calculating circuit 32 calculates the arithmetic mean value (referred to as tav) of the half cycle values of this time section. Next, the cycle extrapolation circuit 33 estimates the zero cross point after T2 (T2 + tav, T2 + 2 × tav, ‥‥) and the cross direction (minus → plus or plus → minus in amplitude).
Are sequentially estimated and output to the cross point estimation memory 34.

Next, the cross direction inversion determination circuit 35 determines the cross direction at the time in the zero point history memory 9 and
Compare the cross direction of the cross point estimation memory 34,
An intermediate time between the time when the direction is inverted and the zero cross point one point before is determined as the phase inversion time. (When the phase is inverted by 180 °, the zero-cross direction is inverted.) Also, once the phase is inverted, the time at which the phase returns to the original (the cross direction returns to the same) is determined in the same manner as the phase inversion time, and the inversion time interval is set. Output to the encoded phase modulation introduction storage memory 30.

In the fourteenth embodiment, when the phase inversion time is near zero, the phase determination may not be able to be determined.
In the present embodiment, there is an effect that determination is possible.

Embodiment 18 FIG. In the seventeenth embodiment, the half-period value obtained from the zero-cross point history is extrapolated, and the phase inversion time is calculated by comparing the zero-cross direction with the extrapolation estimation direction. However, as shown in FIG. , A peak estimation memory 36 and a minimum / maximum inversion determination circuit 37 are provided in place of the cross direction inversion determination circuit 35, and extrapolation is performed using one cycle value calculated at the minimum or maximum peak point, and the estimated maximum point reaches the peak. The time when the minimum peak point and the estimated minimum point become the maximum peak point in the peak history memory 12 in the history memory 12 may be determined as the phase inversion time.

The operation of the eighteenth embodiment will be described.
The operation from the output of the (amplitude value, time) data of the input IF signal to the amplitude memory (5) to the output of the peak history memory 12 is the same as that of the fifth embodiment. Next, the cycle change detection circuit 27 continuously performs the time division (T
1 to T2), and outputs the result to the cycle calculation circuit 32.

Next, the cycle calculation circuit 32 calculates an arithmetic mean value (referred to as tav) of one cycle value of this time section. The cycle is calculated from the minimum point time series and the maximum point time series, and the arithmetic mean of all cycle values is used.
Assuming that the last minimum point between T1 and T2 is TV and the last maximum point is TH, the periodic extrapolation circuit 33 then calculates the minimum point estimation time (TV + tav, TV + 2 × tav,
‥), the maximum point estimation time after TH (TH + tav, T
H + 2 × tav, ‥‥) are sequentially estimated and output to the peak estimation memory 36.

Next, the minimum / maximum inversion determination circuit 37 compares the minimum / maximum point time in the peak history memory 12 with the estimated minimum / maximum point time in the peak estimation memory 36,
An intermediate time between the time when the minimum and the maximum are inverted and the zero cross point one point before is determined as the phase inversion time.
(When the phase is inverted by 180 °, the minimum becomes minimum → maximum, the maximum becomes → minimum.)

Also, the time when the phase returns to the original state after the inversion (the estimation / history minimum / maximum coincides again) is determined in the same manner as the phase inversion time, and the inversion time interval is stored in the coded phase modulation instruction storage memory. Output to 30.

In the fourteenth embodiment, the phase determination cannot be determined when the phase inversion time is near the peak. On the other hand, the present embodiment has an effect that the determination is possible.

[0094]

As described above, the frequency modulation specification measuring apparatus according to the first invention has a DRFM circuit that samples an input signal and stores a digital amplitude value measured by the sampling. A reading circuit for sequentially reading the stored digital amplitude values and outputting the digital amplitude values in a time series; an amplitude memory circuit for storing the digital amplitude values output from the reading circuit in a time series; and a digital amplitude stored in the amplitude memory circuit. A frequency modulation specification calculation circuit that determines the frequency modulation specification of the input signal based on the value; therefore, the frequency modulation of the input signal can be determined without causing a frequency error due to a temperature change. .

A frequency modulation specification measuring device according to a second aspect of the present invention is the frequency modulation specification calculating circuit according to the first aspect of the invention, which calculates a time at which the amplitude value becomes zero from a plurality of the digital amplitude values. Since the frequency modulation data is determined based on the time, the Fourier transform is not performed. Therefore, the time section (T) can be set small, and the data for each subdivided section can be determined.

A frequency modulation specification measuring device according to a third aspect of the present invention is the frequency modulation specification calculating circuit according to the first aspect of the present invention, wherein a time at which an amplitude value has a peak value is calculated from a plurality of the digital amplitude values. Since the frequency modulation data is determined based on the time, the Fourier transform is not performed, so that the time section (T) can be set small, and the data can be determined for each subdivided section.

A frequency modulation specification measuring device according to a fourth invention is the frequency modulation specification calculation circuit according to the first invention, wherein the first time at which the digital amplitude value becomes zero is:
Based on the change in the time difference from the second time at which the digital amplitude value becomes zero, phase inversion is detected and frequency modulation parameters are determined, so that Fourier transform is not performed.
The time section (T) can be set small, and specifications for each subdivided section can be determined.

The frequency modulation specification measuring device according to a fifth aspect of the present invention is the frequency modulation specification calculating circuit according to the first invention, wherein the first time at which the digital amplitude value has a peak value and the digital amplitude value Is to detect the phase inversion based on the change in the time difference from the second time at which the peak value is reached, and determine the frequency modulation specifications. Therefore, the time section (T) should be set small because Fourier transform is not performed. Can be
The specifications for each subdivided section can be determined.

A frequency modulation specification measuring device according to a sixth aspect of the present invention is the frequency modulation specification calculating circuit according to the first aspect, wherein the first time at which the digital amplitude value becomes zero,
A change in time difference from a second time at which the digital amplitude value becomes zero, a time difference between a first time at which the digital amplitude value has a peak value, and a second time at which the digital amplitude value has a peak value. , The phase inversion is detected and the frequency modulation data is determined, so that the error of the phase inversion time can be reduced.

A frequency modulation specification measuring device according to a seventh invention is the frequency modulation specification calculation circuit according to the first invention, wherein the period calculation circuit for calculating a period based on the digital amplitude value; An inversion estimating circuit for estimating the time and direction of the inversion of the phase based on the cycle calculated by the circuit; and a digital amplitude value at the same time as the inversion direction at the inversion time estimated by the inversion estimation circuit. Since it has a circuit for determining the frequency modulation data by comparing the calculated inversion direction, the phase can be determined even when the phase inversion time is near zero.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a frequency measurement device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of an amplitude memory input according to an embodiment of the present invention;

FIG. 3 is a configuration diagram of a frequency measuring device according to another embodiment of the present invention.

FIG. 4 is a configuration diagram of a frequency measuring device according to another embodiment of the present invention.

FIG. 5 is a configuration diagram of a frequency measuring device according to another embodiment of the present invention.

FIG. 6 is a configuration diagram of a frequency measurement device according to another embodiment of the present invention.

FIG. 7 is a configuration diagram of a frequency measurement device according to another embodiment of the present invention.

FIG. 8 is a configuration diagram of a frequency measurement device according to another embodiment of the present invention.

FIG. 9 is a configuration diagram of a frequency measurement device according to another embodiment of the present invention.

FIG. 10 is a configuration diagram of a frequency measurement device according to another embodiment of the present invention.

FIG. 11 is a configuration diagram of a frequency measuring device according to another embodiment of the present invention.

FIG. 12 is a configuration diagram of a conventional frequency measurement device.

FIG. 13 is a configuration diagram of a frequency modulation specification determining device according to an embodiment of the present invention.

FIG. 14 is a diagram showing an example of an amplitude memory input according to the embodiment of the present invention;

FIG. 15 is a configuration diagram of a frequency modulation specification determining apparatus according to another embodiment of the present invention.

FIG. 16 is a configuration diagram of a frequency modulation specification determining apparatus according to another embodiment of the present invention.

FIG. 17 is a configuration diagram of a frequency modulation specification determining apparatus according to another embodiment of the present invention.

FIG. 18 is a configuration diagram of a frequency modulation specification determining apparatus according to another embodiment of the present invention.

FIG. 19 is a configuration diagram of a frequency modulation specification determining apparatus according to another embodiment of the present invention.

FIG. 20 is a configuration diagram of a frequency modulation specification determining apparatus according to another embodiment of the present invention.

FIG. 21 is a configuration diagram of a frequency modulation specification determining apparatus according to another embodiment of the present invention.

FIG. 22 is a configuration diagram of a conventional frequency modulation specification determination device.

[Explanation of symbols]

1 IF signal input terminal, 2 DRFM circuit, 3 timer, 4 readout circuit, 5 amplitude memory, 6 FFT circuit, 7F memory, 8 zero detection circuit, 9 zero point history memory, 10 F calculation circuit, 11 peak detection circuit, 12 peak history memory, 13 F calculation circuit (using peak), 14 Kalman filter circuit, 15 section F
Memory, 16 adjacent F calculation circuit, 17 duplexer, 18
Delay circuit A, 19 Delay circuit B, 20 Delay circuit C, 2
1 delay circuit D, 22 phase detector, 23 IFM frequency calculation circuit, 24 output terminal, 25 least squares approximation circuit, 26 chirp specification storage memory, 27 period change detection circuit, 28 phase inversion point history memory, 29 encoding phase Modulation determination circuit, 30 encoded phase modulation specification storage memory, 31π / 2 time memory, 32 cycle calculation circuit, 33 cycle extrapolation circuit, 34 cross point estimation memory, 35 cross direction inversion determination circuit, 36 peak estimation memory, 37 minimum / maximum inversion judgment circuit, 37 duplexer, 38 filter circuit, 39 A / D converter, 40
Instantaneous frequency calculation circuit, 41 Instantaneous frequency storage memory, 4
2 Intra-pulse modulation determination circuit, 43 Intra-pulse modulation specification storage memory.

Claims (7)

[Claims] 1. A DRF that samples an input signal and stores a digital amplitude value measured by the sampling.
An M circuit; a read circuit for sequentially reading digital amplitude values stored in the DRFM circuit and outputting the digital amplitude values in a time series; an amplitude memory circuit for storing digital amplitude values output from the read circuit in a time series; A frequency modulation specification determining device comprising: a frequency modulation specification calculation circuit that determines frequency modulation specifications of the input signal based on a digital amplitude value stored in a memory circuit. 2. The frequency modulation specification calculation circuit calculates a time at which the amplitude value becomes zero from a plurality of the digital amplitude values, and determines the frequency modulation specification based on the time. Item 3. The frequency modulation specification determining device according to Item 1. 3. The frequency modulation specification calculating circuit calculates a time at which the amplitude value has a peak value from the plurality of digital amplitude values, and determines the frequency modulation specification based on the time. The apparatus for determining frequency modulation specifications according to claim 1. 4. The frequency modulation specification calculation circuit, based on a change in a time difference between a first time at which the digital amplitude value becomes zero and a second time at which the digital amplitude value becomes zero, calculates a phase The frequency modulation specification determining apparatus according to claim 1, wherein the frequency modulation specification is determined by detecting the inversion. 5. The frequency modulation specification calculating circuit, based on a change in a time difference between a first time at which the digital amplitude value has a peak value and a second time at which the digital amplitude value has a peak value, The frequency modulation specification judging device according to claim 1, wherein the frequency modulation specification is determined by detecting a phase inversion. 6. The frequency modulation specification calculating circuit, comprising: a change in a time difference between a first time at which the digital amplitude value becomes zero, and a second time at which the digital amplitude value becomes zero; Detecting a phase inversion based on a change in a time difference between a first time at which the value takes a peak value and a second time at which the digital amplitude value takes a peak value, and determining frequency modulation specifications. The apparatus for determining frequency modulation specifications according to claim 1. 7. The frequency modulation specification calculation circuit includes: a period calculation circuit that calculates a period based on the digital amplitude value; Inversion estimation circuit for estimating the direction of the inversion, the frequency modulation specifications by comparing the inversion direction at the inversion time estimated in the inversion estimation circuit and the inversion direction calculated based on the digital amplitude value at the same time, The frequency modulation specification judging device according to claim 1, further comprising a judging circuit.