JP2002183079A - Input/output data transferring method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technique capable of transferring a large capacity of data efficiently in the case of transferring data between a main storage device and an input/output device. SOLUTION: An input/output data transferring method for transferring data between the main storage device and the input/output device has a step for securing a data area for inputting and outputting data, a step for assigning real storage to the secured data area, a step for deciding whether continuous real storage is assigned or not as the result of the assignment, a step for generating an input/output command setting the DMA length of the length and the indirect data address of the data area to which the continuous real storage is assigned when the continuous real storage is assigned, a step for generating the input/output command setting only the indirect data address when the continuous real storage is not assigned and a step for carrying out the generated input/output command to transfer the input/output data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output data transfer method for transferring input / output data between a main storage device and an input / output device, and particularly to an input / output data transfer method for efficiently transferring input / output data in a computer system. The present invention relates to a technology effective when applied to a transfer method.

[0002]

2. Description of the Related Art Generally, when data is transferred between a main storage device and an input / output device in a computer system, an input / output command specifying an address of the main storage device is generated and executed by an input / output control device. Is performing data transfer.

An input / output control device accesses data in a main storage device without intervention of a central processing unit. This is called direct memory access (DMA). In consideration of the fact that the addresses of the main memory used at this time are non-contiguous, an indirect data address can be specified. In this case, the transfer length of the data specified by the indirect data address is fixed. Therefore, when data specified by the indirect data address is transferred, DMA processing is performed several times of the specified indirect data address.

When all data addresses are continuous, it is not necessary to specify an indirect data address. However, if there is any discontinuous address, an indirect data address must be specified. At this time, the data of the address which is continuous to some extent is subjected to the DMA processing for the number of times of the designated indirect data address, and the data transfer efficiency is reduced.

[0005] As a conventional technique for reducing the number of times of the DMA processing, for example, a technique described in Japanese Patent Publication No. 6-5520 is known. In this conventional technique, the maximum DMA transfer length is defined in advance in the system, and the content of the indirect data address is read before executing the input / output command specified by the indirect data address. The DMA length for each indirect data address is extended. This expansion is performed until the maximum DMA transfer length is exceeded, there is no input / output command specifying the indirect data address, or the indirect data address becomes discontinuous. As described above, in this technique, the number of times of the DMA processing is reduced by performing the DMA processing of the maximum DMA transfer length.

[0006]

In the technique described in the above-mentioned publication, the DMA length given from the continuous number of indirect data addresses or the predetermined maximum DMA transfer length, whichever is smaller, is used. Since the length is used, data transfer exceeding the maximum DMA transfer length is not performed, and there is a problem that the effect of improving the data transfer efficiency is not so high.

In the technology described in the above-mentioned publication,
In order to generate I / O commands for specifying indirect data addresses even when data addresses are continuous, a large amount of indirect data address storage area is required when performing large-capacity data transfer with continuous addresses. Have.

An object of the present invention is to solve the above-mentioned problem and to provide a technique capable of efficiently transferring a large amount of data when data is transferred between a main storage device and an input / output device.

[0009]

According to the present invention, there is provided an input / output data transfer method for transferring input / output data between a main storage device and an input / output device, wherein a DMA having a length of a data area to which continuous real storage is allocated is provided. Input / output data transfer is performed by length.

In the input / output data transfer method of the present invention, first, a data area for input / output is secured, and real storage is allocated to the data area. Then, it is determined whether or not continuous real storage is allocated as a result of the allocation. If continuous real storage is allocated, the DMA length and the indirect data address of the length of the data area to which the continuous real storage is allocated are set. Generates input / output commands. If continuous real storage is not assigned, an input / output command in which only an indirect data address is set is generated.

When the input / output command is generated as described above, the generated input / output command is executed, and the DMA length of the data area to which the continuous real storage is allocated is assigned to the input / output command. If set, input / output data of the DMA length is transferred between the main storage device and the input / output device.

As described above, according to the input / output data transfer method of the present invention, the input / output data transfer is performed according to the DMA length of the data area to which the continuous real storage is allocated. It is possible to efficiently transfer a large amount of data when performing data transfer between.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An input / output data transfer method according to an embodiment for transferring input / output data between a main storage device and an input / output device will be described below.

FIGS. 1 to 3 are diagrams showing examples of input / output command groups for performing data transfer between the main storage device 20 and the input / output device 40 according to the present embodiment. To perform input / output processing, an operation request block (ORB), a channel command word (CCW), an indirect data address word (IDAW)
Need to be created.

FIG. 1 is a diagram showing an outline of an input / output command group in which a data transfer length (DMA length) for an indirect data address is set in the ORB of this embodiment. As shown in FIG.
The indirect data address extension flag 101 of the RB 100 is O
N (in the case of "1") indicates that the DMA length is specified in the input / output command, and when the DMA setting flag 102 is "00", the DMA length is common to the input / output command group. It is shown that.

FIG. 2 is a diagram showing an outline of an input / output command group in which a data transfer length for an indirect data address is set in the CCW of this embodiment. As shown in FIG. 2, when the indirect data address extension flag 111 of the ORB 110 is ON, it indicates that the DMA length is specified in the input / output command, and when the DMA setting flag 112 is “10”, the DM length is specified.
This indicates that the A length is specified for each CCW 210.

FIG. 3 is a diagram showing an outline of an input / output command group in which a data transfer length for an indirect data address is set in the IDAW of this embodiment. As shown in FIG.
When the indirect data address extension flag 121 is ON, it indicates that the DMA length is specified in the input / output command, and when the DMA setting flag 122 is “01”,
This indicates that the MA length is specified for each IDAW 320.

FIG. 4 is a diagram showing an outline of a group of input / output commands for performing data transfer between the main storage device 20 and the input / output device 40 according to the prior art. As shown in FIG.
B130 indirect data address extension flag 131 is OF
The case of F (in the case of “0”) indicates that the DMA length is not specified in the input / output command.

FIG. 5 is a diagram showing a schematic configuration of the input / output data transfer method of the present embodiment. As shown in FIG. 5, the computer system of this embodiment has an input / output command generation processing unit 21 and an input / output data transfer processing unit 31.

When continuous real storage is allocated to a data area for performing input / output, the input / output command generation processing unit 21 determines the DMA length of the data area to which the continuous real storage is allocated and the indirect data address. Is a processing unit that generates an input / output command in which only an indirect data address is set when continuous real storage is not allocated. I / O data transfer processing unit 31
Is a processing unit that executes the generated input / output command to transfer input / output data.

A program for causing the computer system to function as the input / output command generation processing unit 21 and the input / output data transfer processing unit 31 is recorded on a recording medium such as a CD-ROM, stored on a magnetic disk or the like, and then stored in a memory. It shall be loaded and executed. The recording medium for recording the program may be a recording medium other than the CD-ROM.

As shown in FIG. 5, the central processing unit 10, the main storage device 20, and the input / output control device 30 include a system bus 50.
The input / output control device 30 and the input / output device 40 are connected by an I / O bus 60.

The computer system of the present embodiment executes an operating system and application programs stored in the main storage device 20, updates data, and, if necessary, via the input / output control device 30. And data transfer between the input and output device 40.

In the present embodiment, a process of generating an input / output command for designating a data transfer length for an indirect data address and performing input / output data transfer will be described below.

FIG. 6 is a flowchart showing a processing procedure of processing for generating an input / output command group for performing data transfer between the main storage device 20 and the input / output device 40 according to the present embodiment. In step 1000, the input / output command generation processing unit 21 of the present embodiment first secures a data area for input / output on virtual storage, and in step 1100, stores the data area in the data area secured on the virtual storage. Call the process to allocate memory.

In step 1200, the contents of the continuous real storage presence flag returned as the result of the real storage allocation are checked to determine whether continuous real storage has been allocated to the data area on the virtual storage. Yes flag is O
If N, that is, if continuous real storage is allocated to the data area, the process proceeds to step 1300. If the continuous real storage presence flag is OFF, that is, if continuous real storage is not allocated, the process proceeds to step 1400. .

In step 1300, the data transfer length for the indirect data address is specified in common for a plurality of input / output commands, the data transfer length for the indirect data address is specified for each input / output command, or the data transfer length for the indirect data address is specified. By referring to definition information indicating whether an input / output command is to be generated by designating a data transfer length for each indirect data address, it is determined which type of input / output command to generate. Here, it is assumed that the definition information is set in advance when the input / output command generation processing unit 21 is installed.

As a result of the determination, when the data transfer length for the indirect data address is commonly specified for a plurality of input / output commands, the 8K data defined in advance in the definition information is used.
B, etc., the DMA length is set to ORB, the IDAW address is set to CCW, and the indirect data address is set to IDAW.
Set to.

As a result of the determination, when the data transfer length for the indirect data address is designated for each input / output command, the continuous memory returned from the real memory allocation process together with the continuous real memory presence flag as the real memory allocation result. The information indicating the length of the data area to which the real storage is allocated is referred to, the DMA length of the continuous real storage length and the address of IDAW are set to CCW, and the indirect data address is set to ID.
Set to AW.

As a result of the determination, when an input / output command is generated by designating the data transfer length for the indirect data address for each indirect data address, the IDAW address is set to CCW and the continuous real storage is allocated. The DMA length corresponding to the length of the data area and its indirect data address are set in IDAW.

In step 1400, for the conventional IDAW for each DMA length such as 2 KB, the address of the IDAW is set to CCW, and the indirect data address of the DMA length unit is set to IDAW.

In step 1500, the generated input / output command is issued to the input / output control device 30, and the input / output data transfer processor 31 executes the input / output command to transfer the input / output data.

The real storage allocation process in the step 1100 will be described below. In step 1600, a continuous real storage page to be replaced is searched for in the real storage page, and can be allocated to the data area secured on the virtual storage, which is longer than the conventional DMA length. Check if there is a continuous real storage area.

In step 1700, it is determined whether or not a continuous real storage area that can be allocated to the data area on the virtual storage is found. If the continuous real storage area that can be allocated is found, the process proceeds to step 1800. If the assignable continuous real storage area is not found, the process proceeds to step 1900.

In step 1800, after allocating the data area on the virtual storage to the found continuous real storage area, the continuous real storage existence flag is set to ON, and the continuous real storage existence flag and the continuous real storage are set. Returns the length of the allocated data area to the caller.

In step 1900, after the data area on the virtual storage is allocated to the discontinuous real storage area, the continuous real storage existence flag is set to OFF, and the continuous real storage existence flag is returned to the caller.

The input / output commands of FIGS. 1 to 3 generated as described above are executed by the input / output data transfer processing unit 31 of the input / output control device 30 by the following operation.

In FIG. 1, when the indirect data address extension flag 101 of the ORB 100 is ON, it means that the DMA length is designated, and the DMA setting flag 1
When 02 is "00", it means that the DMA length is common to the input / output command group.

Therefore, the input / output data transfer processing section 31 of the input / output control device 30 takes in the DMA length 103 set in the ORB 100 and uses it as the DMA length at the time of data transfer. In the CCW 200, when the indirect data address flag 202 is ON, it means that the address set in the CCW is not the data address but the IDAW address, and the transfer length 203 of the data area is CCW2.
00 and the IDAW 300 has the data area 400
Is stored.

In this embodiment, since 16 KB of data is transferred by one CCW, a value of 16 KB is stored in the transfer length 203 of the data area. 8K in the data area 400
Since there are two continuous areas of B, a value of 8 KB is stored in the DMA length 103 of the ORB 100, and 2 bytes are stored in the IDAW 300.
Have been created.

In FIG. 2, when the indirect data address extension flag 111 of the ORB 110 is ON, it means that the DMA length is specified, and the DMA setting flag 1
When 12 is "10", it means that the DMA length is specified for each input / output command.

Therefore, the input / output data transfer processing unit 31 of the input / output control device 30 takes in the DMA length 211 set in the CCW 210 and uses it as the DMA length at the time of data transfer. In the CCW 210, when the indirect data address flag 212 is ON, it means that the address set in the CCW is not the data address but the IDAW address, the transfer length 213 of the data area is set in the CCW, and the IDAW 310 Indicates the address of the data area 410.

In this embodiment, since 16 KB of data is transferred by one CCW, a value of 16 KB is stored in the transfer length 213 of the data area. 4K in the data area 410
Since there are four continuous areas of B, a value of 4 KB is stored in the DMA length 211 of the CCW 210, and the IDAW 310 has a value of 4 KB.
Have been created.

In FIG. 3, when the indirect data address extension flag 121 of the ORB 120 is ON, it means that the DMA length is designated, and the DMA setting flag 1
When 22 is "01", it means that the DMA length is specified for each indirect data address.

Therefore, the input / output data transfer processing unit 31 of the input / output control device 30
The length 321 is fetched and used as the DMA length at the time of data transfer. In the CCW 220, when the indirect data address flag 222 is ON, it means that the address set in the CCW is not the data address but the IDAW address, and the transfer length 223 of the data area is the CCW.
, And the address of the data area 420 is stored in the IDAW 320.

In this embodiment, since 16 KB of data is transferred by one CCW, a value of 16 KB is stored in the transfer length 223 of the data area. Data area 420 is 4K
Since there is a continuous area of B, 8 KB and 4 KB, IDAW3
20 DMA lengths 321 are 4 KB, 8 KB, 4
The value of KB is stored, and three IDAWs 320 are created.

The input / output data transfer processing unit 31 of this embodiment
In this way, when there is continuous real storage in this way, the I / O data with the DMA length set is executed to transfer the I / O data, thereby reducing the number of DMA processes and improving the efficiency of the I / O data transfer. Can be done Further, the indirect data address storage area can be reduced.

Next, in the present embodiment, when executing the conventional input / output command in which the DMA length of the continuous real storage is not set as described above, the data transfer length is obtained from the continuous state of the indirect data address. The process of performing input / output data transfer will now be described.

In FIG. 4, when the indirect data address extension flag 131 of the ORB 130 is OFF, it means that the DMA length is not specified, that is, the input / output command is an input / output command created by the prior art. are doing.

When the indirect data address flag 232 is ON, it means that the address set in the CCW is not a data address but an IDAW address.
The transfer length 233 of the data area is set to CCW, and IDA
The address of the data area 430 is stored in W330.

In this embodiment, since 16 KB of data is transferred by one CCW, a value of 16 KB is stored in the transfer length 233 of the data area. The IDAW 330 has a fixed D
Data addresses are stored in units of 2 KB of the MA length.

FIG. 7 is a flowchart showing a processing procedure of processing for generating each optimum transfer length when indirect data addresses are consecutive in this embodiment.

In step 2000 of FIG. 7, the input / output data transfer processing section 31 of the input / output control device 30 sets 1 to the position i of the IDAW as an initial setting of various information,
Set the number of MA processes j to 1 and set the minimum DMA length k to 204
Set 8.

Next, in step 2100, when the DMA processing
DMA length L as information used for _j, First data address
Less E_jSet.

In step 2200, the data address (A _i ) stored in the IDAW is obtained. Step 230
At 0, it is checked whether or not the subsequent IDAW exists. If the subsequent IDAW exists, the process proceeds to step 2400, and the data address (A _{i + 1} ) stored in the IDAW is obtained.

[0056] At step 2500, for determining whether data address are consecutive, and A i _{+ 1,} compares a value obtained by adding the minimum DMA length k to A _i, the result of the comparison, if equal data Since it means that the addresses are continuous, the process proceeds to step 2600, and the IDAW position i
Adding the minimum DMA length k to DMA length L _j by adding 1 to. Step 2200 for referring to the next IDAW
Return to the processing of

As a result of the comparison in step 2500, A _{i + 1}
If the value obtained by adding the minimum DMA length k to A and A _i is not equal, it means that the data addresses are not continuous, so the process proceeds to step 2700, and 1 is added to the position i of the IDAW.
And 1 is added to the number of times of DMA processing j. And
The process returns to the DMA processing information setting processing of step 2100.

[0058] the process proceeds to step 2800 if the subsequent IDAW does not exist in step 2300, and performs I / O processing by using top data address E _{1 ~ j,} the DMA length L _{1 ~ j,} which has been processed so far.

FIG. 8 is a diagram showing the state of data and IDAW in this embodiment. A specific example of the above processing will be described in detail with reference to FIG.

(1) Set 1 to i. (2) Set 1 to j. (3) Set 2048 to k. (4) setting the L ₁ to 2048. (5) to set the contents X'4000 'of E ₁ to IDAW1. (6) to set the contents X'4000 'of A ₁ to IDAW1. (7) X'1800 'of IDAW2 exists. (8) set the contents X'1800 'of A ₂ to IDAW2. (9) with the contents of the A ₂ X'1800 ', the contents of the A ₁ X'40
A value X'4800 'obtained by adding 2048 to 00' is compared. (10) Since they are not equal, 1 is added to i and 2 is set. (11) 2 is set by adding 1 to j.

(12) 2048 is set to L ₂ . (13) set the contents X'1800 'of E ₂ to IDAW2. (14) set the contents X'1800 'of A ₂ to IDAW2. (15) X'2000 'of IDAW3 exists. (16) set the contents X'2000 'of A ₃ to IDAW3. (17) the contents of the A ₃ X'2000 ', the contents of the A ₂ X'1
A value X'2000 'obtained by adding 2048 to 800' is compared. (18) Since they are equal, 1 is added to i and 3 is set. (19) by adding the L ₂ in 2048 to set 4096.

[0062] (20) the contents of the A ₃ to IDAW3 X'20
Set 00 '. (21) X'3800 'of IDAW4 exists. (22) set the contents X'3800 'in A ₄ to IDAW4. (23) the contents of the A ₄ X'3800 ', the contents of the A ₃ X'2
A value X'2800 'obtained by adding 2048 to 000' is compared. (24) Since they are not equal, 1 is added to i and 4 is set. (25) Add 1 to j to set 3.

[0063] (26) to set the L ₃ in 2048. (27) set the contents X'3800 'of E ₃ to IDAW4. (28) set the contents X'3800 'of A ₄ to IDAW4. (29) X'5800 'of IDAW5 exists. (30) set the contents X'5800 'of A ₅ to IDAW5. (31) with the contents of the A ₅ X'5800 ', the contents of the A ₄ X'3
A value X'4000 'obtained by adding 2048 to 800' is compared. (32) Since they are not equal, 1 is added to i and 5 is set. (33) Add 1 to j to set 4.

[0064] (34) to set the L ₄ in 2048. (35) set the contents X'5800 'of E ₄ to IDAW5. (36) set the contents X'5800 'of A ₅ to IDAW5. (37) X'6000 'of IDAW6 exists. (38) set the contents X'6000 'of A ₆ to IDAW6. (39) the contents of the A ₆ X'6000 ', the contents of the A ₅ X'5
A value X'6000 'obtained by adding 2048 to 800' is compared. (40) Since they are equal, 1 is added to i, and 6 is set. (41) by adding the L ₄ 2048 set 4096.

[0065] (42) the contents of the A ₆ to IDAW6 X'60
Set 00 '. (43) X'6800 'of IDAW7 exists. (44) set the contents X'6800 'of A ₇ to IDAW7. And (45) the contents of the A ₇ X'6800 ', the contents of the A ₆ X'6
A value X'6800 'obtained by adding 2048 to 000' is compared. (46) Since they are equal, 1 is added to i and 7 is set. (47) to set the 6144 by adding the L ₄ in 2048.

[0066] (48) the contents of the A ₇ to IDAW7 X'68
Set 00 '. (49) X'7000 'of IDAW8 exists. (50) set the contents X'7000 'of the A ₈ IDAW8. (51) the contents of A ₈ X'7000 ', the contents of A ₇ X'6
A value X'7000 'obtained by adding 2048 to 800' is compared. (52) Since they are equal, 1 is added to i, and 8 is set. (53) by adding the L ₄ 2048 set 8192. (54) set the contents X'7000 'of the A ₈ IDAW8. (55) IDAW9 does not exist. _{(56) E 1, L 1} (X'4000 ', 2048),
E ₂ , L ₂ (X′1800 ′, 4096), E ₃ , L ₃ (X
'3800', 2048), E ₄ , L ₄ (X'580
0 ', 8192).

As described above, even for the input / output command created by the conventional technique, the transfer length is obtained for each continuous data, so that the number of DMAs can be reduced and the input / output data transfer can be performed efficiently.

As described above, according to the present embodiment, the input / output data transfer can be efficiently performed by executing the input / output command specifying the indirect data address and the transfer length. Further, according to the present embodiment, when performing large-capacity data transfer, the indirect data address storage area can be reduced. Further, according to the present embodiment, the input / output command generated by the operating system of the prior art is executed by obtaining the transfer length for each continuous data, and thus the compatibility is ensured and the input / output data transfer is efficiently performed. It can be carried out.

As described above, according to the input / output data transfer method of the present embodiment, input / output data transfer is performed according to the DMA length of the length of the data area to which continuous real storage is allocated. When data is transferred between output devices, large-capacity data can be transferred efficiently.

[0070]

According to the present invention, since the input / output data transfer is performed by the DMA length of the length of the data area to which the continuous real storage is allocated, the data transfer between the main storage device and the input / output device is performed. It is possible to efficiently transfer a large amount of data.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an outline of an input / output command group in which a data transfer length (DMA length) for an indirect data address is set in an ORB according to an embodiment.

FIG. 2 is a diagram illustrating an outline of an input / output command group in which a data transfer length for an indirect data address is set in a CCW according to the embodiment;

FIG. 3 is a diagram illustrating an outline of an input / output command group in which a data transfer length for an indirect data address is set in an IDAW of the embodiment;

FIG. 4 is a diagram showing an outline of an input / output command group for performing data transfer between a main storage device 20 and an input / output device 40 according to a conventional technique.

FIG. 5 is a diagram illustrating a schematic configuration of an input / output data transfer method according to the embodiment;

FIG. 6 illustrates a main storage device 20 and an input / output device 40 according to the present embodiment.
9 is a flowchart showing a processing procedure of a process of generating an input / output command group for performing data transfer between the server and the server;

FIG. 7 is a flowchart showing a processing procedure of processing for generating each optimum transfer length when indirect data addresses are consecutive in the embodiment.

FIG. 8 is a diagram illustrating a state of data and IDAW according to the present embodiment.

[Explanation of symbols]

100: ORB, 101: indirect data address extension flag, 102: DMA setting flag, 103: DMA length, 2
00: CCW, 202: Indirect data address flag, 2
03: transfer length, 300: IDAW, 400: data area, 110: ORB, 111: indirect data address extension flag, 112: DMA setting flag, 210: CCW,
211 DMA length, 212 indirect data address flag, 213 transfer length, 310 IDAW, 410 data area, 120 ORB, 121 indirect data address extension flag, 122 DMA setting flag, 220 CC
W, 222: indirect data address flag, 223: transfer length, 320: IDAW, 321: DMA length, 420: data area, 130: ORB, 131: indirect data address extension flag, 230: CCW, 232: indirect data address flag 233: transfer length, 330: IDAW, 4
30 data area, 10 central processing unit, 20 main storage device, 30 input / output control device, 40 input / output device, 50
... System bus, 60 I / O bus, 21 input / output command generation processing unit, 31 input / output data transfer processing unit

Claims (3)

[Claims] In an input / output data transfer method for transferring input / output data between a main storage device and an input / output device, a step of allocating a data area for performing input / output is performed, and an actual storage is performed in the allocated data area. And determining whether or not continuous real storage has been allocated as a result of the allocation. If continuous real storage has been allocated, the DMA length and the indirect length of the data area to which the continuous real storage has been allocated. Generating an input / output command in which a data address is set, generating an input / output command in which only an indirect data address is set when continuous real storage is not allocated, and executing the generated input / output command. Performing an input / output data transfer by using the input / output data transfer method. 2. When continuous real storage is allocated, a data transfer length for an indirect data address is specified in common for a plurality of input / output commands, or a data transfer length for an indirect data address is specified for each input / output command. 2. The input / output data transfer method according to claim 1, wherein the input / output command is generated by designating a data transfer length for the indirect data address for each indirect data address. 3. The data transfer method according to claim 1, wherein a data transfer length is obtained for each continuous data of the indirect data address, and data transfer is performed for each obtained data transfer length. I / O data transfer method.