JP2002176362A - Method and device for transmitting digital signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently multiplex-transmit the digital video signals of a plurality of systems and the digital audio signals of a plurality of systems by a means which is comparatively easily arranged and to reduce cost. SOLUTION: S/P conversion is performed on the serial digital video signals of a plurality of systems and a plurality of pieces of parallel video data making transmission rates to be substantially equal are formed. multiplex parallel audio data making the transmission rate substantially equal to a plurality of pieces of parallel video data is formed based on the serial digital audio signals of a plurality of systems. A plurality of pieces of parallel video data and multiplex parallel audio data are multiplexed and composite parallel data is formed. Composite parallel data is P/S-converted, composite serial data is formed and the composite serial data is transmitted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The invention described in the claims of the present application relates to a digital video signal of a plurality of systems and a digital audio signal of a plurality of systems. The present invention relates to a digital signal transmission method for transmitting data in an independent relationship or in a content-related relationship, and a digital signal transmission device used for implementing the method.

[0002]

2. Description of the Related Art In recent years, with respect to video signals obtained from a video camera such as a television camera used for recording broadcast program information by a television broadcasting station, recently, diversification of transmitted information and high quality of reproduced images have been promoted. Digitization has been attempted from the viewpoint of realization, and a video camera (digital video camera) that generates a digitized video signal, that is, a digital video signal has been put to practical use. A digital video signal obtained from a digital video camera is generally formed of digital data according to a standardized data format. As digital video signals formed by digital data conforming to such a standardized data format, 4: 2: 2 component digital video signal (D1 signal), 4fsc composite digital video signal (D2 signal) and the like are known. ing.

For example, the D1 signal is formed of digital data according to a data format in which one line period is repeated as shown in FIG. This figure 2
The digital data conforming to the data format shown in FIG. 3 is 10-bit word string data in which words each formed of 10 bits are continuous. Each line period corresponds to a timing reference code data EAV (End of Active Video) consisting of four words, an auxiliary data part consisting of 268 words, timing reference code data SAV (Start of Active Video) consisting of four words and 1 , 4
A video data section composed of 40 words is sequentially arranged.

When digital data according to the data format shown in FIG. 23 is transmitted, the LSB (Least Significant Bit) is used for each word.
: Least significant bit), and is serial digital data with a bit transmission rate of 270 Mbps, for example. A system interface in which serial digital data for transmission is formed based on such digital data according to the data format shown in FIG. 23 is an SDI (Serial Digital Interface).
And standardized as SMPTE259M. Hereinafter, a serial digital video signal formed by digital data according to the SDI data format is referred to as an SDI video signal.

[0005] Further, even in the case of an audio signal related to a video signal or an independent audio signal, digitization has been attempted from the viewpoint of diversifying transmitted information and improving the quality of reproduced sound. A digital audio signal of the following method has been proposed. For example, one of such digital audio signals conforms to the AES / EBU format which is a unified standard for the serial digital audio format.

A serial digital audio signal conforming to the AES / EBU format (hereinafter referred to as AES / EBU audio signal) is assumed to have been subjected to bi-phase mark modulation during transmission, but not to bi-phase mark modulation. In the state, it follows the data format as shown in FIG.
In the data format shown in FIG.
The audio signal information of two channels of 1 and CH2 is
Each of the sub-frames is composed of 32 bits and is arranged alternately. Two consecutive frames form one frame, and 192 frames from frame 0 to frame 191 form one block. Each subframe has a preamble Z, X or Y, 4 consisting of 4 bits.
An auxiliary data section consisting of bits, an audio data section consisting of 20 bits, and a valid flag V, user data U, channel status C, and parity bit P, each consisting of 1 bit, are sequentially arranged. The preamble Z indicates the beginning of each block (192 frames), the preamble X indicates that the content of the audio data portion is CH1, and the preamble Y indicates that the content of the audio data portion is CH2.

An AES / EBU audio signal conforming to a data format as shown in FIG. 24 is one frame = 1 sample. For example, the sampling frequency is fs = 48 kHz and the bit transmission rate is 64 fs = 64 fs.
3.07 Mbps.

The AES / EBU audio signal obtained by subjecting the AES / EBU audio signal according to the data format shown in FIG. 24 to bi-phase mark modulation follows the data format shown in FIG. . The AES / EBU audio signal according to the data format shown in FIG. 25 has a sampling frequency of fs = 48 kHz and a bit transmission rate of AE according to the data format shown in FIG.
Twice the S / EBU audio signal, ie, 128 fs =
6.144 Mbps, each sub-frame is composed of 64 bits, and each frame is composed of 128 bits.

[0009]

In the digital video signal and the digital audio signal in the above-described situation, it is of course required that each of them is transmitted independently. Opportunity for multiplex transmission of digital video signals and digital audio signals in a content-independent relationship or in content-related relationships Is increasing. Furthermore, for example, each digital video signal stored on a digital video disk (DVD) is accompanied by a multi-system digital audio signal corresponding to audio surround sound or multilingualization. There is also a demand for multiplex transmission of a plurality of digital video signals and a plurality of digital audio signals.

In such single transmission or multiplex transmission of the digital video signal and the digital audio signal, the transmission of the digital video signal and the digital audio signal is efficiently performed by means that can be arranged relatively easily, and the cost is reduced. Therefore, it is necessary to ensure that the original digital video signal and digital audio signal are reproduced on the receiving side. However, in the related art, for example, there is no digital signal transmission system that can perform multiplex transmission of a plurality of systems of digital video signals and a plurality of systems of digital audio signals while satisfying such requirements. .

In view of the above, the invention described in the claims of the present application can perform multiplex transmission of a plurality of digital video signals and a plurality of digital audio signals, and furthermore, the multiplex transmission. The transmission at
Efficiently done by means that are relatively easy to arrange,
Digital signal transmission method capable of reducing costs and ensuring that original digital video signals of a plurality of systems and digital audio signals of a plurality of systems are reproduced on a receiving side, and such a method. The present invention provides a digital signal transmission device used for implementing the method.

[0012]

A digital signal transmission method according to the invention described in any one of claims 1 to 14 in the claims of the present application provides a method for transmitting serial digital video signals of a plurality of systems. A serial / parallel conversion is performed to form a plurality of parallel video data having transmission rates substantially equal to each other, and the transmission rate is substantially equal to each of the plurality of parallel video data based on a plurality of serial digital audio signals. To form multiple parallel audio data
A plurality of parallel video data and multiple parallel audio data are multiplexed to form composite parallel data, and the obtained composite parallel data is subjected to parallel / serial conversion to form composite serial data. It is assumed that data is transmitted.

In particular, in the digital signal transmission method according to the second aspect of the present invention, prior to performing parallel / serial conversion on the composite parallel data, the composite parallel data is subjected to an 8-bit / 10-bit conversion process. Is applied.

The digital signal transmission apparatus according to any one of claims 15 to 25 in the claims of the present application provides a serial / parallel conversion for each of a plurality of serial digital video signals. And a serial / parallel converter for forming a plurality of parallel video data having transmission rates substantially equal to each other, and a transmission rate substantially corresponding to each of the plurality of parallel video data based on a plurality of serial digital audio signals. An audio multiplexing unit for forming multiplexed parallel audio data for equalization, a video / audio multiplexing unit for multiplexing a plurality of parallel video data and multiplexed parallel audio data to form composite parallel data, and a composite parallel data To parallel / serial conversion Forming a composite serial data constituted by a parallel / serial converter for transmitting the composite serial data.

In particular, in the digital signal transmission apparatus according to the present invention, the composite parallel data formed by the video / audio data multiplexing section is subjected to an 8-bit / 10-bit conversion process to obtain an 8-bit data. / 10
There is provided an 8-bit / 10-bit converter for transmitting the composite parallel data subjected to the bit conversion processing to the parallel / serial converter.

The digital signal transmission method according to any one of the first to fourteenth aspects of the present invention as described above, or the fifteenth aspect of the present invention. In the digital signal transmission apparatus according to the invention as set forth in any one of claims 25 to 25, a plurality of serial digital video signals are converted into a plurality of parallel video data having transmission rates substantially equal to each other. Multiplexed parallel audio data based on a plurality of serial digital audio signals and having a transmission rate substantially equal to each of the plurality of parallel video data is formed. Multiplexed by being transmitted as data .

Under the circumstances, each of the plural serial digital video signals is, for example, an SDI video signal, and each of the plural serial digital audio signals is, for example, an AES / EBU audio signal. It is said. In this case, a plurality of systems of serial digital video signals are converted to a plurality of parallel video data, a plurality of parallel audio data are formed based on the plurality of serial digital audio signals, a plurality of parallel video data and a plurality of parallel audio data are formed. For example, the multiplexing process and the formation and transmission of the composite serial data can be performed relatively efficiently by using an existing digital signal processing integrated circuit device, etc. It is supposed to be able to be performed under planning. In the composite serial data to be transmitted, the original plurality of serial digital video signals and the plurality of serial digital audio signals are reliably reproduced on the receiving side.

Therefore, multiplex transmission of a plurality of serial digital video signals, each of which is, for example, an SDI video signal, and a plurality of serial digital audio signals, each of which is, for example, an AES / EBU audio signal, is performed. In addition, transmission in the multiplex transmission is performed efficiently by means that can be arranged relatively easily, cost is reduced, and the original plurality of serial digital video signals and the plurality of serial The digital audio signal is reliably reproduced.

[0019]

1 and 2 show an example of a digital signal transmission method according to the invention described in any one of claims 1 to 9 in the claims of the present application. Claim 15 in the claims of the present application
21 shows an example of a digital signal transmission device according to the invention described in any one of claims 21 to 21.

The examples shown in FIGS. 1 and 2 show six systems of SDI as a plurality of serial digital video signals.
Video signals DSVA1 to DSVA6 and 15 AESs as a plurality of serial digital audio signals
The multiplex transmission with the / EBU audio signals DAA1 to DAA15 is performed from the transmission / reception system A shown in FIG. 1 to the transmission / reception system B side shown in FIG. Video signal D
FIG. 2 shows multiplex transmission of SVB1 to DSVB6 and 15 AES / EBU audio signals DAB1 to DAB15 as a plurality of serial digital audio signals.
1 is performed from the transmission / reception system B side shown in FIG. 1 to the transmission / reception system A side shown in FIG.

In the transmission / reception system A shown in FIG. 1, six systems of S digital digital video signals are used.
DI video signals DSVA1 to DSVA6 are serial /
The signals are supplied to the parallel (S / P) converters 11 to 16, respectively. Each of the SDI video signals DSVA1 to DSVA6 has a bit transmission rate of 270 Mbps.

The S / P converters 11 to 16 respectively convert the SDI video signals DSVA1 to DSVA6 into S / P
The conversion is performed to form six parallel video data DPVA1 to DPVA6 each of which is 10-bit 27-MHz 10-bit word string data. That is, S / P conversion is performed on the six SDI video signals DSVA1 to DSVA6 to form six parallel video data DPVA1 to DPVA6 that make the transmission rates substantially equal to each other. Then, the S / P converters 11 to 16
Video data DPVA1-D obtained from
The PVA 6 is supplied to the video / audio multiplexing unit 17.

Also, 15 AES / EBU audio signals DAA1 to DAA15, which are a plurality of serial digital audio signals, are supplied to the audio multiplexing unit 18. AES / EBU audio signal DAA1
Each of the DAAs 15 has been subjected to biphase mark modulation and has a sampling frequency of, for example, fs = 48 k
Hz and the bit transmission rate is 128 × 48/1000
= 6.144 Mbps.

In the audio multiplexing section 18, the AES
Multiplexed parallel audio data DCAA is formed based on / EBU audio signals DAA1 to DAA15.
The multiplex parallel audio data DCAA is 4 bits
The data is 27-MHz 4-bit word string data, and the transmission rate is made substantially equal to each of the parallel video data DPVA1 to DPVA6 supplied to the video / audio multiplexing unit 17. The multiplexed parallel audio data DC obtained from the audio multiplexing unit 18
The AA is supplied to the video / audio multiplexing unit 17.

In a specific example of the audio multiplexing unit 18, first, the AES / EBU audio signals DAA1 to DAAD
Each of the AAs 15 is converted from a configuration in which one block is formed by 192 frames to a configuration in which one block is formed by 225 frames, and the sampling frequency is changed to fs
= 48 kHz to fs' = 56.25 kHz apparently, and a process of inserting auxiliary data (AUG data) forming 33 frames into each block to perform AES / EBU audio signals DAA1 to DAA1.
5 for each bit transmission rate of 128 × 56.25 / 1
000 = 7.2 Mbps.

Next, AES / AUG / AUG / AUG / AGS / AUG / AES / AGS / AUG / AES / AUG / AES / AUG / AES / AUG /
Fifteen synthesized serial data based on each of the EBU audio signals DAA1 to DAA15 are
The data is converted to 60-bit / 32 fs 'parallel data by treating it as fs' parallel data and performing S / P conversion. Then, further, the 60 bits and 32f
Parallel / serial (P / S) for parallel data of s'
The data is converted to 4-bit / 480 fs 'parallel data to form multiplex parallel audio data DCAA which is 4-bit / 480 fs', that is, 4-bit / 27 MHz 4-bit word string data.

FIG. 3 shows such an audio multiplexing unit 18.
In one embodiment, the bit transmission rate is 6.144M.
AES / EBU audio signal DAA1 in bps
2 shows an example of a configuration for inserting AUG data forming 33 frames in each block and converting the bit transmission rate to 7.2 Mbps. In the configuration example shown in FIG. 3, the AES / EBU audio signal DAA
1 is supplied to the S / P converter 20, and is converted into 8 bits / 16f
s is converted into parallel data DPA1. The parallel data DPA1 is supplied to the FIFO memory unit 21.

In the FIFO memory section 21, the parallel data DPA1 is written according to a write clock QW having a frequency of 16 fs under the control of the write control signal QWE, and the written parallel data DPA1 is written.
Changes the frequency to 1 under the control of the read control signal QRE.
6 fs ′ according to a read clock QR,
It is transmitted as 8-bit 16 fs 'parallel data DPA1'. At this time, the parallel data DPA1 '
Parallel data DPA compared to parallel data DPA1
It is delayed by one 64 frames. That is, the beginning of each block in the 8-bit 16 fs 'parallel data DPA1' is delayed by 64 frames of the parallel data DPA1 compared to the beginning of each block in the 8-bit 16fs parallel data DPA1. You.

The 8-bit / 16 fs 'parallel data DPA1' sent from the FIFO memory unit 21 is
The data is supplied to the G data insertion unit 22. The AUG data insertion unit 22 is also supplied with AUG data DAUG converted into parallel data of 8 bits and 16 fs ′. The AUG data DAUG is equivalent to 33 frames in the parallel data DPA1 ', and has block synchronization pattern data, system number data, frame number data, subframe number data, and the like embedded therein.

The AUG data insertion unit 22 adds the AUG data D to the 33 frame portion at the end of each block in the parallel data DPA1 '.
The AUG is inserted, and the parallel data DPA1 ′ into which the AUG data DAUG is inserted is transmitted from the AUG data insertion unit 22 as 8-bit 16fs ′ combined parallel data DPAM1. 8-bit 16 fs' synthesized parallel data DPAM1 from the AUG data insertion unit 22
Is supplied to the P / S converter 23 to form synthesized serial data DAA1 ′ having a bit transmission rate of 128 × 56.25 / 1000 = 7.2 Mbps.

FIG. 4 shows the combined serial data DAA1 'obtained from the P / S converter 23. In the synthesized serial data DAA1 ′ shown in FIG.
The UG data DAUG is the frame 1 in each block.
AUG0 to AUG32 forming 92 to 224 are inserted.

FIG. 5 shows the timing relationship between the AES / EBU audio signal DAA1 and the combined serial data DAA1 '. In FIG. 5, AES / EB
In the U audio signal DAA1, sub-blocks 0, 1, and 2 each consisting of 64 frames form each block, and in the synthesized serial data DAA1 ', each sub-block consisting of 75 frames. Block 0, 1
And 2 form each block. Each block of the AES / EBU audio signal DAA1 is formed with 192 frames, while each block of the combined serial data DAA1 'is formed with 225 frames, and the beginning of each block of the combined serial data DAA1' is , AES / EBU audio signal DAA1 lags behind the beginning of each block by 64 frames in AES / EBU audio signal DAA1.

In one specific example of the above-mentioned audio multiplexing unit 18, each of the bit multiplexing rates is set to 6.144 Mbp.
AES / EBU audio signals DAA2 to DA
A15 is also subjected to the same processing as in the case of the AES / EBU audio signal DAA1, and AUG data is inserted into each of them as in the case of the combined serial data DAA1 ', and the bit transmission rate is set to 7.2 Mbps. The synthesized serial data DAA2 ′ to DAA
15 'are formed.

FIG. 6 shows a specific example of the audio multiplexing unit 18 based on the synthesized serial data DAA1 'to DAA15' obtained as described above.
A configuration example for obtaining multiplexed parallel audio data DCAA as 4-bit word string data of MHz is shown.
In the configuration example shown in FIG. 6, the combined serial data DAA1 ′ to DAA15 ′, each of which is assumed to have a bit transmission rate of 7.2 Mbps, are 15 bits × 12 bits.
8 fs 'parallel data DAA'
It is supplied to the P conversion unit 24. In the S / P converter 24, the 15-bit / 128 fs' parallel data DA
A / P conversion is performed on A ', resulting in a 60-bit / 32 fs'
Is converted to parallel data DPAA.

The parallel data DPAA obtained from the S / P converter 24 is supplied to a P / S converter 25. P /
In the S converter 25, the parallel data DPAA of 60 bits / 32 fs 'is subjected to P / S conversion to form parallel data of 4 bits / 480 fs', which is multiplexed parallel audio data DCAA of 4 bits / 27 MHz. Is sent as

In another specific example of the audio multiplexing section 18, the AES / EBU audio signals DAA1 to DAA
The whole of 15 is treated as parallel data of 15 bits / 128 fs. First, transmission rate conversion for converting into parallel data of 15 bits / 128 fs ′ is performed, and processing of inserting AUG data forming 33 frames into each block is performed. AES / EBU audio signal DA
Based on A1 to DAA15, 15 bits · 12 with AUG data forming 33 frames in each block
8 fs' parallel data is obtained.

Next, a 15-bit 128 fs' in which AUG data forming 33 frames is inserted in each block.
Is subjected to S / P conversion processing to convert the parallel data into 60-bit / 32 fs' parallel data. continue,
Further, the 60-bit / 32 fs' parallel data is subjected to P / S conversion processing to be converted into 4-bit / 480 fs' parallel data, and is converted into a 4-bit / 480 fs', that is, a 4-bit / 27 MHz 4-bit word string. The multiplexed parallel audio data DCAA to be data is formed.

FIG. 7 shows such an audio multiplexing unit 18.
In another specific example, a configuration example for obtaining multiplexed parallel audio data DCAA based on AES / EBU audio signals DAA1 to DAA15 is shown. In the configuration example shown in FIG. 7, the entirety of the AES / EBU audio signals DAA1 to DAA15 is 15 bits / 128 bits.
The data is treated as fs parallel data and supplied to the FIFO memory unit 26.

In the FIFO memory unit 26, AE which is handled as parallel data of 15 bits / 128 fs
The frequency of the S / EBU audio signals DAA1 to DAA15 is changed to 128f under the control of the write control signal QWE.
s and the written AES / EBU audio signals DAA1 to DAA
15 is read out according to a read clock QR having a frequency of 128 fs 'under the control of the read control signal QRE, and the 15-bit 128 fs' parallel data DP
Transmitted as A '. At that time, the parallel data DP
A 'is an AES / EBU audio signal DAA1-DAA treated as 15-bit / 128 fs parallel data.
Compared to AA15, the AES / EBU audio signals DAA1 to DAA15 are delayed by 64 frames. That is, the start of each block in the 15-bit 128 fs 'parallel data DPA' is 15 bits.
A treated as 128-bit parallel data
This is delayed by 64 frames in the AES / EBU audio signals DAA1 to DAA15 from the start of each block in the ES / EBU audio signals DAA1 to DAA15.

15 sent from the FIFO memory unit 26
The bit / 128 fs 'parallel data DPA' is A
It is supplied to the UG data insertion unit 27. The AUG data insertion unit 27 is also supplied with AUG data DAUG converted into parallel data of 15 bits and 128 fs ′. AUG
Data DAUG is 3 in parallel data DPA '.
It corresponds to three frames, and has embedded therein block synchronization pattern data, system number data, frame number data, subframe number data, and the like.

Then, the AUG data insertion unit 27 adds the AUG data DA to the 33 frame portion at the end of each block in the parallel data DPA '.
The parallel data DPA 'into which the UG is inserted and the AUG data DAUG is inserted is transmitted from the AUG data insertion unit 27 as 15-bit 128 fs' synthesized parallel data DPAM. 1 from the AUG data insertion unit 27
5-bit 128fs' synthetic parallel data DPAM
Is supplied to the S / P converter 28. S / P converter 28
, The S / P conversion is performed on the 15-bit 128 fs ′ synthesized parallel data DPAM to obtain a 60-bit
It is converted into 32 fs' parallel data DPAA.

The parallel data DPAA obtained from the S / P converter 28 is supplied to a P / S converter 29. P /
In the S conversion section 29, P / S conversion is performed on the parallel data DPAA of 60 bits / 32 fs 'to form parallel data of 4 bits / 480 fs', which is multiplexed parallel audio data DCAA of 4 bits / 27 MHz. Is sent as

The parallel video data DPVA1 to DPVA6, each of which is obtained from the S / P converters 11 to 16 and is 10 bits / 27 MHz parallel data, respectively, and the 10 bits / 27 MHz obtained from the audio multiplexing unit 18.
Video / audio multiplexing unit 1 to which multiplexed parallel audio data DCAA which is parallel data of
7, the parallel video data DPVA1 to DPVA
Under the assumption that the entire VA6 is treated as parallel data of 60 bits / 27 MHz, the parallel video data DPVA1
~ DPVA6 and multiple parallel audio data DCAA
And multiplexing processing, and 16 bits / 480 fs × 4 =
16-bit 108MHz composite parallel data DPX
Form A.

The composite parallel data DPXA obtained from the video / audio multiplexing unit 17 is supplied to an 8-bit / 10-bit conversion unit (8B / 10B conversion unit) 30. 8
The B / 10B conversion unit 30 performs an 8B / 10B conversion process on the composite parallel data DPXA. Such 8B /
In the 10B conversion process, the composite parallel data DPXA is divided into 8 bits by dividing the 16 bits forming each word into two 8-bit groups each having 8 bits. Each one,
The conversion is performed by sequentially converting the data into 10-bit data according to a conversion table prepared in advance. At this time, a 10-bit code that does not appear as long as it follows the conversion table is embedded in the sequentially obtained 10-bit data as a synchronization detection reference code.

Subsequently, in the 8B / 10B conversion unit 30, two 10-bit data sequentially obtained by the 8B / 10B conversion processing are superimposed two by two to form 20-bit word string data, It is derived as complex parallel data DPZA of 108 bits. The composite parallel data DPZA obtained from the 8B / 10B conversion unit 30 in this manner is supplied to a fiber channel transceiver (FC transceiver) 31.

The FC transceiver 31 outputs 1 for every 8 bits.
This is a transceiver for transmitting and receiving data in accordance with a fiber channel system, which converts parallel digital data formed through 8B / 10B conversion processing in which conversion to 0 bits is performed into serial data and transmits the serial data. And in the FC transceiver 31, 8B
The 20-bit / 108 MHz composite parallel data DPZA from the / 10B converter 30 is supplied to the P / S converter 32 and converted into composite serial data DSZA having a bit transmission rate of 2.16 Gbps. DSZA is transmitted.

On the other hand, in the transmission / reception system B shown in FIG. 2, the bit transmission rate transmitted by the FC transceiver 31 in the transmission / reception system A shown in FIG.
The composite serial data DSZA of ps is received by the FC transceiver 40 and supplied to the S / P converter 41 in the FC transceiver 40.

In the S / P converter 41, the composite serial data D having a bit transmission rate of 2.16 Gbps
The synchronization detection reference code portion in the SZA is detected, S / P conversion is performed based on the synchronization detection reference code portion detected in the composite serial data DSZA, and 20-bit / 108 MHz composite parallel data DPZA is reproduced. The composite parallel data DPZA obtained from the S / P converter 41 is a 10-bit / 8-bit converter (10B / 8
B conversion unit) 42.

The 10B / 8B converter 42 performs a 10B / 8B conversion process on the composite parallel data DPZA. The 10B / 8B conversion process detects a synchronization detection reference code in 10 bits forming each 20-bit word of the composite parallel data DPZA, and sets the composite parallel data DPZA based on the detected synchronization detection reference code.
Each of the 10 bits forming each 20-bit word of ZA is sequentially converted into 8-bit data according to a conversion table prepared in advance.

Subsequently, in the 10B / 8B conversion section 42, 8-bit data sequentially obtained by the 10B / 8B conversion processing is superimposed two by two to form 16-bit word string data. It is derived as complex parallel data DPXA of 108 bits. The composite parallel data DPXA obtained from the 10B / 8B conversion unit 42 in this way is supplied to the video / audio division unit 43.

In the video / audio division unit 43, the 16-bit / 108 MHz composite parallel data D
PXA is converted into 64-bit / 27 MHz parallel data, and six 10-bit / 27 MHz parallel video data DPVA1 to DPVA6 are converted from the 64-bit / 27 MHz parallel data into 60-bit / 27 MHz parallel data as a whole. At the same time, the 4-bit / 27 MHz multiplexed parallel audio data DCAA is divided. In the video / audio division unit 43, the total is 60 bits / 27 MH
6 10-bit data obtained as z parallel data
27 MHz parallel video data DPVA1 to DPV
A6 is supplied to P / S converters 44 to 49, respectively.
The 4-bit / 27 MHz multiplexed parallel audio data DCAA obtained by the video / audio division unit 43 is supplied to the audio division unit 50.

In the P / S converters 44 to 49, six 10-bit / 27 MHz parallel video data DP
P / S conversion is performed on each of VA1 to DPVA6, and six SDI video signals DSVA1 to DSVA6 each having a bit transmission rate of 270 Mbps are reproduced.

In the audio dividing section 50, 4-bit / 27 MHz multiplexed parallel audio data DCA
AES / EBU audio signal DAA of 15 systems from A
1 to DAA 15 are reproduced.

At this time, in one specific example of the audio dividing section 50, first, 4-bit 27 MHz, that is, 4-bit 480 fs' multiplexed parallel audio data D
The CAA is converted into parallel data of 60 bits / 32 fs', and the parallel data of 60 bits / 32 fs' is converted into parallel data of 15 bits / 128 fs' as a whole.
It is converted into 15 synthesized serial data of 2 Mbps.

Next, each has a bit transmission rate of 7.2M.
Each of the 15 synthesized serial data at bps is 8
After being converted into the combined parallel data of 16 bits / fs, the parallel data of 8 bits / 16 fs' and the AUG data of 16 bits / fs' are separated from the combined parallel data of 8 bits / 16 fs'. Then, 8 bits / 16 fs' parallel data separated into 8 bits
The transmission rate conversion is performed to convert the bits into 16 fs parallel data, and the 8-bit 16 fs parallel data is converted into serial data having a bit transmission rate of 6.144 Mbps. As a result, 15 AES / E systems
The BU audio signals DAA1 to DAA15 are reproduced.

FIG. 8 shows such an audio dividing unit 50.
In one specific example, a configuration example is shown for converting 4-bit / 480 fs' multiplexed parallel audio data DCAA into 15 pieces of synthesized serial data each having a bit transmission rate of 7.2 Mbps. In the configuration example shown in FIG. 8, the 4-bit / 480 fs' multiplexed parallel audio data DCAA is supplied to the S / P conversion unit 51, subjected to the S / P conversion processing, and subjected to the 60-bit / 32f
It is converted into parallel data DPAA of s ′. The 60-bit / 32 fs' parallel data DPAA obtained from the S / P converter 51 is supplied to the P / S converter 52,
After receiving the / S conversion process, each of them increases the bit transmission rate to 7.
15 synthesized serial data DAA at 2 Mbps
15 bits 12 formed by 1 'to DAA 15'
The data is converted into 8 fs 'parallel data DAA'.

FIG. 9 shows a specific example of the audio dividing section 50, which is obtained as described above and has a total of 15.
15 pieces of combined serial data DAA1 ′ to DAA15 ′ each forming a 128 fs ′ parallel data DAA ′, each having a bit transmission rate of 7.2 Mbps
From the combined serial data DAA1 ', AES /
4 shows a configuration example for reproducing an EBU audio signal DAA1. In the configuration example shown in FIG. 9, the combined serial data DA having a bit transmission rate of 7.2 Mbps
A1 ′ is supplied to the S / P conversion unit 53, and is subjected to S / P conversion processing to be converted into 8-bit 16fs ′ synthetic parallel data DPAM1. The combined parallel data DPAM1 obtained from the S / P converter 53 is supplied to the AUG data separator 54.

The AUG data separation unit 54 converts the 8-bit 16 fs 'parallel data DPA1' from the 8-bit 16fs 'parallel data DPA1'.
And 8-bit 16fs' AUG data DAUG are separated and transmitted. 8-bit 16 fs 'parallel data DPA1' obtained from the AUG data separation unit 54
Is supplied to the FIFO memory unit 55.

In the FIFO memory unit 55, the parallel data DPA1 'is written under the control of the write control signal QWE in accordance with the write clock QW having a frequency of 16 fs', and the written parallel data DPA1' is written.
1 ′ is read out under the control of the read control signal QRE in accordance with the read clock QR having a frequency of 16 fs, and sent out as 8-bit 16 fs parallel data DPA1. At this time, the start of each block in the 8-bit 16 fs parallel data DPA1 is 64 times larger than the start of each block in the 8-bit 16fs 'parallel data DPA1'.
It is assumed to be earlier by the frame.

The 8-bit / 16 fs parallel data DPA1 sent from the FIFO memory unit 55 is supplied to the P / S conversion unit 56. In the P / S converter 56,
The 8-bit / 16 fs parallel data DPA1 from the FIFO memory unit 55 is subjected to P / S conversion processing to be serialized, and the bit transmission rate is 6.144 Mbps.
AES / EBU audio signal DAA1 is reproduced.

In one specific example of the above-described audio dividing section 50, 15 pieces of synthesized serial data DAA1 'to DAA1 each having a bit transmission rate of 7.2 Mbps.
Synthesized serial data DAA2 'to DAA1 of 5'
Also for each of 5 ', the synthesized serial data DAA1'
Is performed, and each of the AES / EBU audio signals DAA2 to DAA15 is reproduced in the same manner as the AES / EBU audio signal DAA1.

In another specific example of the audio division unit 50, the 4-bit data from the video / audio division unit 43
27 MHz, that is, 15 bits 128 fs of the total of 15 pieces of synthesized serial data DAA 1 ′ to DAA 15 ′ each having a bit transmission rate of 7.2 Mbps obtained based on 4-bit 480 fs ′ multiplexed parallel audio data DCAA. Synthesized parallel data DA
Treat as A ', then 15 bits, 128fs'
Parallel data and 15-bit 128 fs' AUG
Separate from data. Then, the separated 15 bits
From the 128 fs' parallel data, 15 systems of AES / each having a bit transmission rate of 6.144 Mbps.
The EBU audio signals DAA1 to DAA15 are reproduced.

FIG. 10 shows such an audio dividing unit 5.
In another specific example of A.0, 4-bit / 480 fs ′ multiplexed parallel audio data DCAA to 15 systems of A
2 shows a configuration example for reproducing ES / EBU audio signals DAA1 to DAA15. In the configuration example shown in FIG. 10, 4-bit / 27 MHz, that is, 4-bit / 480 fs ′ multiplexed parallel audio data DCAA from the video / audio division unit 43 is supplied to the S / P conversion unit 57, After undergoing the S / P conversion processing, the data is converted into parallel data DPAA of 60 bits / 32 fs ′.
Parallel data DPAA obtained from S / P converter 57
Is supplied to the P / S conversion section 58 and subjected to the P / S conversion processing to obtain the 15-bit / 128 fs' parallel data DA.
Converted to A '.

The parallel data DAA ′ obtained from the P / S converter 58 is supplied to the AUG data separator 59. In the AUG data separation section 59, the parallel data DAA 'of 15 bits and 128 fs' is
5-bit 128 fs 'parallel data DPA' and 1
The 5-bit 128 fs' AUG data DAUG is separated and transmitted. 15-bit 128 fs' parallel data DP obtained from the AUG data separation unit 59
A 'is supplied to the FIFO memory unit 60.

In the FIFO memory unit 60, the parallel data DPA 'is written according to a write clock QW having a frequency of 128 fs' under the control of the write control signal QWE, and the written parallel data DPA' is written.
A ′ is read according to a read clock QR having a frequency of 128 fs under the control of the read control signal QRE to form 15-bit / 128 fs parallel data as a whole, each having a bit transmission rate of 6.144.
15-bit AE, which is serial data at Mbps
The S / EBU audio signals DAA1 to DAA15 are reproduced.

In the transmission / reception system B shown in FIG. 2, a serial digital video signal of a plurality of systems is used.
The SDI video signals DSVB1 to DSVB6 of the system
/ P converters 61-66. Each of the SDI video signals DSVB1 to DSVB6 has a bit transmission rate of 270 Mbps.

The S / P converters 61 to 66 convert the SDI video signals DSVB1 to DSVB6 into S / P
The conversion is performed to form six parallel video data DPVB1 to DPVB6 each of which is 10-bit / 27-MHz 10-bit word string data. That is, S / P conversion is performed on the six systems of SDI video signals DSVB1 to DSVB6 to form six parallel video data DPVB1 to DPVB6 that make the transmission rates substantially equal to each other. Then, the S / P converters 61 to 66
Video data DPVB1-DVB obtained from
The PVB 6 is supplied to the video / audio multiplexing unit 67.

Further, 15 AES / EBU audio signals DAB1 to DAB15, which are a plurality of serial digital audio signals, are supplied to the audio multiplexing section 68. AES / EBU audio signal DAB1
Each of the DABs 15 has been subjected to bi-phase mark modulation and has a sampling frequency of, for example, fs = 48 k
Hz and the bit transmission rate is 128 × 48/1000
= 6.144 Mbps.

In audio multiplexing section 68, AES
Multiplexed parallel audio data DCAB is formed based on / EBU audio signals DAB1 to DAB15.
The multiplexed parallel audio data DCAB is 4 bits
This is 4-bit word string data of 27 MHz, and the transmission rate is made substantially equal to each of the parallel video data DPVB1 to DPVB6 supplied to the video / audio multiplexing section 67. The multiplexed parallel audio data DC obtained from the audio multiplexing unit 68
AB is supplied to the video / audio multiplexing unit 67.

In a specific example of the audio multiplexing section 68, first, the AES / EBU audio signals DAB1-DAB
Each of AB15 is converted from a configuration in which one block is formed by 192 frames to a configuration in which one block is formed by 225 frames, and the sampling frequency is changed to fs
= 48 kHz to fs' = 56.25 kHz apparently, and a process of inserting AUG data forming 33 frames into each block is performed.
The bit transmission rate of each of the U audio signals DAB1 to DAB15 is set to 128 × 56.25 / 1000 = 7.2M.
The data is converted into synthesized serial data of bps.

Next, AES / EB in which the AUG data forming 33 frames are inserted in each block to set the bit transmission rate to 7.2 Mbps, respectively.
1 based on the U audio signals DAB1 to DAB15, respectively.
5 synthesized serial data is converted to 15 bit 128f
The data is converted to 60-bit / 32 fs 'parallel data by treating the data as s' parallel data and performing S / P conversion. Then, further, the 60 bits and 32f
P / S conversion is performed on the parallel data of s ′ to convert it into 4-bit / 480 fs ′ parallel data,
480 fs', that is, multiplexed parallel audio data DCAB which is 4-bit / 27 MHz 4-bit word string data is formed.

In one specific example of such an audio multiplexing section 68, each of them has a bit transmission rate of 6.144 Mb.
AES / EBU audio signal D of 15 systems with ps
Based on each of AB1 to DAB15, each has a bit transmission rate of 128 × 56.25 / 1000 = 7.2 Mb
An example of a configuration for obtaining the combined serial data in ps is the AES / EBU audio signal DA shown in FIG.
This is the same as the configuration example relating to A1.

In a specific example of the audio multiplexing section 68, the multiplexed parallel audio data D which is converted into 4-bit / 27-MHz 4-bit word string data based on the 15 synthesized serial data obtained as described above.
The configuration example for obtaining the CAB is the same as the configuration example relating to the 15-bit 128 fs 'parallel data DAA' shown in FIG.

In another specific example of audio multiplexing section 68, AES / EBU audio signals DAB1-DAB
The whole of 15 is treated as parallel data of 15 bits / 128 fs. First, transmission rate conversion for converting into parallel data of 15 bits / 128 fs ′ is performed, and processing of inserting AUG data forming 33 frames into each block is performed. AES / EBU audio signal DA
15 bits.12 in which AUG data forming 33 frames is inserted in each block based on B1 to DAB15
8 fs' parallel data is obtained.

Next, a 15-bit 128 fs' in which AUG data forming 33 frames is inserted in each block.
Is subjected to S / P conversion processing to convert the parallel data into 60-bit / 32 fs' parallel data. continue,
Further, the 60-bit / 32 fs' parallel data is subjected to P / S conversion processing to be converted into 4-bit / 480 fs' parallel data, and is converted into a 4-bit / 480 fs', that is, a 4-bit / 27 MHz 4-bit word string. The multiplexed parallel audio data DCAA to be data is formed.

In another specific example of such audio multiplexing section 68, AES / EBU audio signal DAB1
~ Multiple parallel audio data D based on DAB15
A configuration example for obtaining CAB is shown in FIG.
The configuration is the same as the configuration example relating to the EBU audio signals DAA1 to DAA15.

The parallel video data DPVB1 to DPVB6, each of which is obtained from the S / P converters 61 to 66, is 10-bit 27 MHz parallel data, and the 10-bit 27 MHz obtained from the audio multiplexing unit 68.
Video / audio multiplexing unit 6 to which multiplexed parallel audio data DCAB which is parallel data of
7, the parallel video data DPVB1 to DPVB1 to DPVB
Under the assumption that the entire VB6 is treated as parallel data of 60 bits / 27 MHz, the parallel video data DPVB1
~ DPVB6 and multiplexed parallel audio data DCAB
And multiplexing processing, and 16 bits / 480 fs × 4 =
16-bit 108MHz composite parallel data DPX
Form B.

The composite parallel data DPXB obtained from the video / audio multiplexing section 67 is supplied to an 8B / 10B conversion section 69. The 8B / 10B converter 69 performs an 8B / 10B conversion process on the composite parallel data DPXB. The 8B / 10B conversion process forms each word of the composite parallel data DPXB by using 16 bits.
By dividing the bits into two 8-bit groups of 8 bits each, 8-bit division is performed, and each of the divided 8-bits is sequentially converted into 10-bit data according to a conversion table prepared in advance. It is done by going. At this time, a 10-bit code that does not appear as long as it follows the conversion table is embedded in the sequentially obtained 10-bit data as a synchronization detection reference code.

Subsequently, in the 8B / 10B conversion section 69, 10-bit data sequentially obtained by the 8B / 10B conversion processing is superimposed two by two to form 20-bit word string data. It is derived as complex parallel data DPZB of 108 bits. The composite parallel data DPZB obtained from the 8B / 10B converter 69 in this way is supplied to the FC transceiver 40.

In the FC transceiver 40, 8B /
The 20-bit / 108 MHz composite parallel data DPZB from the 10B converter 69 is supplied to the P / S converter 70 and converted into composite serial data DSZB having a bit transmission rate of 2.16 Gbps. Is sent.

In the transmission / reception system A shown in FIG. 1, the bit transmission rate transmitted by the FC transceiver 40 in the transmission / reception system B shown in FIG.
The composite serial data DSZB of ps is received by the FC transceiver 31 and supplied to the S / P converter 71 in the FC transceiver 31.

In S / P conversion section 71, composite serial data D having a bit transmission rate of 2.16 Gbps
The synchronization detection reference code portion in the SZB is detected, and S / P conversion is performed based on the synchronization detection reference code portion detected in the composite serial data DSZB to reproduce 20-bit 108 MHz composite parallel data DPZB. The composite parallel data DPZB obtained from the S / P converter 71 is supplied to the 10B / 8B converter 72.

The 10B / 8B converter 71 performs a 10B / 8B conversion process on the composite parallel data DPZB. The 10B / 8B conversion process detects a synchronization detection reference code in 10 bits forming each 20-bit word of the composite parallel data DPZB, and sets the composite parallel data DPZB based on the detected synchronization detection reference code.
Each of 10 bits forming each 20-bit word of ZB is sequentially converted into 8-bit data according to a conversion table prepared in advance.

Subsequently, in the 10B / 8B conversion section 72, 8-bit data sequentially obtained by the 10B / 8B conversion processing are superimposed two by two to form 16-bit word string data, Derived as complex parallel data DPXB of 108 bits. The composite parallel data DPXB obtained from the 10B / 8B conversion unit 72 in this way is supplied to the video / audio division unit 73.

In the video / audio division unit 73, 16-bit / 108 MHz composite parallel data D
PXB is converted into 64-bit / 27 MHz parallel data, and six 10-bit / 27 MHz parallel video data DPVB1 to DPVB6 are converted into 60-bit / 27 MHz parallel data from the 64-bit / 27 MHz parallel data. At the same time, the 4-bit 27 MHz multiplexed parallel audio data DCAB is divided. In the video / audio division unit 73, the total is 60 bits / 27 MH
6 10-bit data obtained as z parallel data
27 MHz parallel video data DPVB1 to DPV
B6 is supplied to P / S converters 74 to 79, respectively.
The 4-bit / 27 MHz multiplexed parallel audio data DCAB obtained in the video / audio division unit 73 is supplied to the audio division unit 80.

In the P / S converters 74 to 79, six 10-bit / 27 MHz parallel video data DP
P / S conversion is applied to each of VB1 to DPVB6, and six SDI video signals DSVB1 to DSVB6 each having a bit transmission rate of 270 Mbps are reproduced.

In the audio dividing section 80, 4-bit / 27 MHz multiplexed parallel audio data DCA
AES / EBU audio signal DAB of 15 systems from B
1 to DAB 15 are reproduced.

At this time, in a specific example of the audio division unit 80, first, 4-bit / 27 MHz, that is, 4-bit / 480 fs ′ multiplexed parallel audio data D
The CAB is converted into parallel data of 60 bits / 32 fs', and the parallel data of 60 bits / 32 fs' is converted into parallel data of 15 bits / 128 fs' as a whole.
It is converted into 15 synthesized serial data of 2 Mbps.

Next, each of the bit transmission rates is set to 7.2M.
Each of the 15 synthesized serial data at bps is 8
After being converted into the combined parallel data of 16 bits / fs, the parallel data of 8 bits / 16 fs' and the AUG data of 16 bits / fs' are separated from the combined parallel data of 8 bits / 16 fs'. Then, 8 bits / 16 fs' parallel data separated into 8 bits
The transmission rate conversion is performed to convert the bits into 16 fs parallel data, and the 8-bit 16 fs parallel data is converted into serial data having a bit transmission rate of 6.144 Mbps. As a result, 15 AES / E systems
The BU audio signals DAB1 to DAB15 are reproduced.

In one specific example of such an audio dividing unit 80, the 4-bit / 480 fs' multiplexed parallel audio data DCAB is converted into a 15-bit / 1
An example of the configuration for converting into 28 pieces of parallel data, each of which is composed of 28 fs' parallel data and having a bit transmission rate of 7.2 Mbps, is shown in FIG. The same is assumed.

Also, in one specific example of the audio dividing section 80, 15 bits and 128 fs' parallel data as a whole obtained as described above are formed, each of which has a bit transmission rate of 7.2 Mbps. A configuration example for reproducing each of the AES / EBU audio signals DAB1 to DAB15 from each of the combined serial data of the composite serial data DAA1 ′ shown in FIG.
Is the same as the configuration example relating to.

In another specific example of the audio division unit 80, the 4-bit data from the video / audio division unit 73
27 MHz, that is, 15 bits / 128 fs ', each of which is obtained based on multiplexed parallel audio data DCAB of 4 bits / 480 fs' and has a bit transmission rate of 7.2 Mbps.
Of 15 bits 128 fs' parallel data and 15 bits 12 fs
8fs' AUG data is separated. Then, from the separated 15-bit / 128 fs' parallel data,
Each of which has a bit transmission rate of 6.144 Mbps 1
AES / EBU audio signals DAB1 to DA of 5 systems
Play B15.

In another specific example of such an audio dividing unit 80, 15 systems of AES / EB are obtained from 4-bit / 480 fs' multiplexed parallel audio data DCAB.
A configuration example for reproducing the U audio signals DAB1 to DAB15 is similar to the configuration example relating to the multiplexed parallel audio data DCAA shown in FIG.

FIGS. 11 and 12 show an example of a digital signal transmission method according to the invention described in any one of claims 1 to 3 and claims 8 to 14 of the present application. Claim 15, Claim 16, and Claim 2 in the claims of the present application, wherein
An example of the digital signal transmission device according to the invention described in any one of claims 0 to 25 is shown.

The examples shown in FIG. 11 and FIG. 12 show six systems of S digital signals as a plurality of systems of serial digital video signals.
DI video signals DSVC1 to DSVC6 and 30 systems of A as a plurality of serial digital audio signals
The multiplex transmission with the ES / EBU audio signals DAC1 to DAC30 is performed from the transmission / reception system C shown in FIG. 11 to the transmission / reception system D shown in FIG. SDI video signals DSVD1 to DSVD6 and 30 systems of AES / E as a plurality of serial digital audio signals
Multiplex transmission with the BU audio signals DAD1 to DAD30 is performed from the transmitting / receiving system D shown in FIG. 12 to the transmitting / receiving system C shown in FIG.

In the transmission / reception system C shown in FIG. 11, six SDI video signals DSVC1 to DSVC6, which are a plurality of serial digital video signals, are supplied to S / P converters 81 to 86, respectively. SDI video signal D
Each of SVC1 to DSVC6 has a bit transmission rate of 2
70 Mbps.

The S / P converters 81 to 86 respectively convert the SDI video signals DSVC1 to DSVC6 into S / P
The conversion is performed to form six parallel video data DPVC1 to DPVC6 each of which is 10-bit / 27-MHz 10-bit word string data. That is, S / P conversion is performed on the six systems of the SDI video signals DSVC1 to DSVC6 to form six parallel video data DPVC1 to DPVC6 that make the transmission rates substantially equal to each other. Then, the S / P converters 81 to 86
Video data DPVC1-D obtained from
The PVC 6 is supplied to the video / audio multiplexing unit 87.

AES / EBU audio signals DAC1 to DAC30 of 30 systems, which are serial digital audio signals of a plurality of systems, are supplied to the audio multiplexing unit 88. AES / EBU audio signal DAC1
Each of the DACs 30 has been subjected to biphase mark modulation and has a sampling frequency of, for example, fs = 48 k
Hz and the bit transmission rate is 128 × 48/1000
= 6.144 Mbps.

In the audio multiplexing section 88, FIG.
AES / EBU audio signal DA
The C1 to DAC 30 are supplied to the biphase mark demodulation unit 89. These AES / EBU audio signals D
Each of the AC1 to the DAC 30 is, for example, synchronized with respect to all of the blocks, frames, and subframes.

In the biphase mark demodulation section 89, AES / EBU audio signals DAC1 to DAC3
0, detection of preambles Z, X, and Y is performed as shown in FIG. 25, and a synchronization control signal is formed based on the detected preambles Z, X, and Y, Synchronous control is performed. Under such circumstances, in the bi-phase mark demodulation unit 89, the AES / EB on which the bi-phase mark modulation is performed is performed.
Bi-phase mark demodulation processing is performed on each of U audio signals DAC1 to DAC30, and demodulated AES / EBU audio signals DACD1 to DACD3 based on AES / EBU audio signals DAC1 to DAC30, respectively.
0 is formed. Each of the demodulated AES / EBU audio signals DACD1 to DACD30 has a sampling frequency of fs = 48 kHz and a bit transmission rate of AES / EBU audio signals DAC1 to DAC3.
64, corresponding to 1/2 of each bit transmission rate of 0
× 48/1000 = 3.072 Mbps.

In the audio multiplexing section 88, each of the AES signals obtained from the bi-phase mark demodulation section 89 has a bit transmission rate of 3.072 Mbps.
Multiplexed parallel audio data DCAC is formed based on / EBU audio signals DACD1 to DACD30. The multiplexed parallel audio data DCAC is 4-bit / 27 MHz 4-bit word string data and has a transmission rate substantially equal to each of the parallel video data DPVC1 to DPVC6 supplied to the video / audio multiplexing unit 87. Is done. Then, the multiplexed parallel audio data DCAC obtained from the audio multiplexing unit 88 is supplied to the video / audio multiplexing unit 87.

In a specific example of the audio multiplexing unit 88, first, the AES / EBU audio signals DACD1 to DACD1 are output.
Each of the DACDs 30 is converted from a configuration in which one block is formed by 192 frames to a configuration in which one block is formed by 225 frames, and changes the sampling frequency from fs = 48 kHz to fs' = 56.25 kHz apparently.
z, and a process of inserting AUG data forming 33 frames into each block is performed.
The bit transmission rate of each of the EBU audio signals DACD1 to DACD30 is 64 × 56.25 / 1000 =
It is converted to synthesized serial data of 3.6 Mbps.

Next, AES / AUG / AUG / AGS / AUG / AES / AUG / AES / AUG / AES / AUG / AGS / AUG / AES / AUG /
30 synthesized serial data based on each of the EBU audio signals DACD1 to DACD30 are converted into 30 bits.
The data is converted into 60-bit / 32 fs 'parallel data by treating it as 4 fs' parallel data and performing S / P conversion. Then, further, the 60 bits and 32
P / S conversion is performed on the fs' parallel data to convert it into 4-bit / 480 fs' parallel data, which is converted into 4-bit / 480 fs', that is, 4-bit / 27 MHz 4-bit word string data. Form data DCAC.

FIG. 14 shows such an audio multiplexing section 8.
8, the bit transmission rate is 3.072.
AES / EBU audio signal DACD with Mbps
FIG. 1 shows an example of a configuration for inserting AUG data forming 33 frames into each block and converting the bit transmission rate to one having a bit transmission rate of 3.6 Mbps. In the configuration example shown in FIG. 14, the AES / EBU audio signal D
ACD1 is supplied to the S / P conversion unit 90, and the 8-bit data
It is converted to 8 fs parallel data DPC1. The parallel data DPC1 is supplied to a FIFO memory unit 91.

In the FIFO memory unit 91, the parallel data DPC1 is written according to a write clock QW having a frequency of 8 fs under the control of the write control signal QWE, and the written parallel data DPC1 is
Frequency 8f under control by read control signal QRE
The data is read out in accordance with the read clock QR set as s ′, and is sent out as 8-bit / 8fs ′ parallel data DPC1 ′. At this time, the parallel data DPC1 'is 6 times smaller than the parallel data DPC1.
It is delayed by four frames. That is, 8 bits
The beginning of each block in the 8fs' parallel data DPC1 'is an 8-bit / 8fs parallel data DPC1'.
1 is delayed by 64 frames of the parallel data DPC1 from the start end of each block.

The 8-bit / 8fs ′ parallel data DPC1 ′ sent from the FIFO memory unit 91 is AUG
The data is supplied to the data insertion unit 92. AUG data insertion unit 9
2 is also supplied with AUG data DAUG converted into 8-bit / 8fs' parallel data. AUG data DA
The UG is equivalent to 33 frames in the parallel data DPC1 ', and has the block synchronization pattern data, system number data, frame number data, subframe number data, etc. embedded therein.

The AUG data insertion unit 92 adds the AUG data D to the 33 frame portion at the end of each block in the parallel data DPC1 '.
The parallel data DPC1 ′ into which the AUG is inserted and the AUG data DAUG is inserted is transmitted from the AUG data insertion unit 92 as 8-bit / 8fs ′ combined parallel data DPCM1. 8 from the AUG data insertion unit 92
The bit parallel data DPCM1 of 8fs' is
The bit transmission rate supplied to the P / S converter 93 is set to 6
Synthesized serial data DACD1 ′ with 4 × 56.25 / 1000 = 3.6 Mbps is formed.

The combined serial data DACD1 ′ obtained from the P / S converter 93 has a different bit transmission rate from the combined serial data DAA1 ′ shown in FIG.
It has a similar bit configuration.

The AES / EBU audio signal DA
The timing relationship between CD1 and the combined serial data DACD1 'is similar to the timing relationship between the AES / EBU audio signal DAA1 and the combined serial data DAA1' shown in FIG.

In one specific example of the above-described audio multiplexing unit 88, each of the bit rates is 3.072 Mbp.
AES / EBU audio signals DACD2 to DCD
The same processing as in the case of the AES / EBU audio signal DACD1 is performed on each of the ACDs 30, and each of the ACDs 30 is processed in the same manner as the synthesized serial data DACD1 '.
Data is inserted, and the bit transmission rate is set to 3.6 Mbp.
s, the synthesized serial data DACD
2 ′ to DACD 30 ′ are formed.

FIG. 15 shows a specific example of the audio multiplexing unit 88 in which multiplexed parallel data is converted into 4-bit / 27 MHz 4-bit word string data based on the synthesized serial data DACD1 ′ to DACD30 ′ obtained as described above. 4 shows a configuration example for obtaining audio data DCAC. In the configuration example shown in FIG. 15, 30 bits of synthesized serial data DACD1 ′ to DACD30 ′ each having a bit transmission rate of 3.6 Mbps.
The data is treated as parallel data DACD 'of 64 fs' bits and supplied to the S / P converter 94. In the S / P converter 94, the 30-bit 64fs 'parallel data DACD' is subjected to S / P conversion to obtain a 60-bit
The data is converted to 32 fs' parallel data DPAC.

The parallel data DPAC obtained from the S / P converter 94 is supplied to the P / S converter 95. P /
In the S converter 95, the parallel data DPAC of 60 bits / 32 fs ′ is subjected to P / S conversion to form parallel data of 4 bits / 480 fs ′. Is sent as

In another specific example of audio multiplexing section 88, AES / EBU audio signals DACD1-DACD
The entire CD 30 is treated as 30-bit / 64 fs parallel data. First, a transmission rate conversion for converting the data into 30-bit / 64 fs' parallel data is performed, and AUG data forming 33 frames is inserted into each block. AES / EBU audio signal DA
30 bits based on CD1 to DACD30, in which AUG data forming 33 frames is inserted in each block.
64 fs' parallel data is obtained.

Next, S / P conversion processing is performed on 30-bit / 64 fs 'parallel data in which AUG data forming 33 frames is inserted in each block to convert the data into 60-bit / 32 fs' parallel data. Subsequently, P / S conversion processing is performed on the 60-bit / 32 fs' parallel data to convert it into 4-bit / 480 fs' parallel data, and the 4-bit / 480 fs', that is, 4-bit / 27 MHz 4-bit data is converted. The multiplexed parallel audio data DCAC to be bit word string data is formed.

FIG. 16 shows such an audio multiplexing section 8.
8 shows a configuration example for obtaining multiplexed parallel audio data DCAC based on AES / EBU audio signals DACD1 to DACD30 in another specific example. FIG.
In the configuration example shown in FIG. 6, the entirety of the AES / EBU audio signals DACD1 to DACD30 is treated as parallel data of 30 bits / 64 fs, and
The data is supplied to the O memory unit 96.

In the FIFO memory unit 96, AES which is handled as 30-bit / 64 fs parallel data is used.
/ EBU audio signals DACD1-DACD30 are
The frequency is 64f under the control of the write control signal QWE.
s and the written AES / EBU audio signals DACD1 to DACD
The CD 30 is read according to a read clock QR having a frequency of 64 fs 'under the control of the read control signal QRE, and the 30-bit 64 fs' parallel data DP
Transmitted as C '. At that time, the parallel data DP
C ′ is an AES / EBU audio signal DACD1 to DACD treated as parallel data of 30 bits / 64fs.
Compared to the ACD 30, the AES / EBU audio signals DACD1 to DACD30 are delayed by 64 frames. That is, the start of each block in the 30-bit / 64 fs 'parallel data DPC' is:
AES / EBU audio signals DACD1-DACD3 handled as 30-bit / 64fs parallel data
AES / E compared to the beginning of each block at 0
The BU audio signals DACD1 to DACD30 are delayed by 64 frames.

30 transmitted from the FIFO memory unit 96
The bit / 64fs 'parallel data DPC' is AU
The data is supplied to the G data insertion unit 97. The AUG data insertion unit 97 is also supplied with AUG data DAUG converted into parallel data of 30 bits / 64 fs ′. The AUG data DAUG is equivalent to 33 frames in the parallel data DPC ', and has block synchronization pattern data, system number data, frame number data, subframe number data, etc. embedded therein.

In the AUG data insertion unit 97, the AUG data DA is added to the 33 frame portion at the end of each block in the parallel data DPC '.
The parallel data DPC 'in which the UG is inserted and the AUG data DAUG is inserted is converted into the AUG data insertion unit 9 as 30-bit / 64 fs' synthetic parallel data DPCM.
7 is sent. 30 from the AUG data insertion unit 97
The combined parallel data DPCM of 64 bits / bit is
It is supplied to the S / P converter 98. The S / P converter 98 performs S / P conversion on the 30-bit / 64 fs ′ synthesized parallel data DPCM to obtain a 60-bit / 32 fs
It is converted into parallel data DPAC of s ′.

The parallel data DPAC obtained from the S / P converter 98 is supplied to the P / S converter 99. P /
In the S conversion section 99, the parallel data DPAC of 60 bits / 32 fs 'is subjected to P / S conversion to form parallel data of 4 bits / 480 fs'. Is sent as

The parallel video data DPVC1 to DPVC6, each of which is obtained from the S / P converters 81 to 86 and is 10 bits / 27 MHz parallel data, and the 10 bits / 27 MHz obtained from the audio multiplexing unit 88, respectively.
Video / audio multiplexing unit 8 to which multiplexed parallel audio data DCAC, which is parallel data of
7, the parallel video data DPVC1-DPVC
Under the assumption that the entire VC6 is treated as parallel data of 60 bits / 27 MHz, the parallel video data DPVC1
~ DPVC6 and multiple parallel audio data DCAC
And multiplexing processing, and 16 bits / 480 fs × 4 =
16-bit 108MHz composite parallel data DPX
Form C.

The composite parallel data DPXC obtained from the video / audio multiplexing section 87 is supplied to the 8B / 10B conversion section 100. The 8B / 10B conversion unit 100 performs an 8B / 10B conversion process on the composite parallel data DPXC. Such an 8B / 10B conversion process is a process for forming each word of the composite parallel data DPXC.
By dividing 6 bits into two 8-bit groups each consisting of 8 bits, 8-bit division is performed, and each of the divided 8 bits is sequentially converted into 10-bit data according to a conversion table prepared in advance. It is done by doing. At this time, a 10-bit code that does not appear as long as it follows the conversion table is embedded in the sequentially obtained 10-bit data as a synchronization detection reference code.

Subsequently, in the 8B / 10B conversion section 100, the 10-bit data sequentially obtained by the 8B / 10B conversion processing is superimposed two by two to form 20-bit word string data. Derived as complex parallel data DPZC of 108 bits. The composite parallel data DPZC obtained from the 8B / 10B converter 100 in this way is supplied to the FC transceiver 101.

For the FC transceiver 101, 8B
20 bits, 108 MHz from the / 10B converter 100
Of the composite parallel data DPZC of the P / S converter 102
Is converted to composite serial data DSZC having a bit transmission rate of 2.16 Gbps, and the composite serial data DSZC is transmitted.

On the other hand, in the transmission / reception system D shown in FIG. 12, the bit transmission rate transmitted by the FC transceiver 101 in the transmission / reception system C shown in FIG.
The composite serial data DSZC of Gbps is received by the FC transceiver 110 and supplied to the S / P converter 111 in the FC transceiver 110.

The S / P converter 111 detects a synchronization detection reference code portion in the composite serial data DSZC having a bit transmission rate of 2.16 Gbps,
The S / P conversion is performed based on the synchronization detection reference code portion detected in the composite serial data DSZC, and the 20-bit / 108 MHz composite parallel data DPZC is reproduced. The composite parallel data DPZC obtained from the S / P converter 111 is supplied to the 10B / 8B converter 112.

The 10B / 8B conversion unit 112 performs a 10B / 8B conversion process on the composite parallel data DPZC. The 10B / 8B conversion process detects a synchronization detection reference code in 10 bits forming each 20-bit word of the composite parallel data DPZC, and uses the detected synchronization detection reference code as a reference to generate the composite parallel data DPZC.
Each of 10 bits forming each 20-bit word of ZC is sequentially converted into 8-bit data according to a conversion table prepared in advance.

Subsequently, the 10B / 8B conversion unit 112 superimposes two pieces of 8-bit data sequentially obtained by the 10B / 8B conversion processing, two by two, to form 16-bit word string data. Derived as complex parallel data DPXC of 108 bits. The composite parallel data DPXC obtained from the 10B / 8B conversion unit 112 in this way is supplied to the video / audio division unit 113.

In the video / audio division unit 113, the 16-bit / 108 MHz composite parallel data D
PXC is converted into 64-bit / 27 MHz parallel data, and from the 64-bit / 27 MHz parallel data, six 10-bit / 27 MHz parallel video data DPVC1 to DPVC6 are converted into 60-bit / 27 MHz parallel data as a whole. At the same time, the 4-bit 27 MHz multiplexed parallel audio data DCAC is divided. In the video / audio division unit 113, the total is 60 bits / 27M
Hz 10-bit 27 MHz parallel video data DPVC1 to DPVC obtained as parallel data
VC6 is supplied to P / S converters 114 to 119, respectively. The 4-bit / 27 MHz multiplexed parallel audio data DCAC obtained in the video / audio division unit 113 is supplied to the audio division unit 120.

In P / S conversion sections 114 to 119,
P / S conversion is performed on each of the six 10-bit 27 MHz parallel video data DPVC1 to DPVC6, and each of the parallel video data has a bit transmission rate of 270 Mbps.
The SDI video signals DSVC1 to DSVC6 of the system are reproduced.

[0130] In the audio dividing section 120, multiplexed parallel audio data DC of 4 bits / 27 MHz is provided.
AES / EBU audio signal DA of 30 systems from AC
CD1 to DACD30 are reproduced.

At this time, in a specific example of the audio dividing unit 120, first, 4 bits / 27 MHz, that is, 4 bits
The bit / 480 fs 'multiplexed parallel audio data DCAC is converted to 60-bit / 32 fs' parallel data, and the 60-bit / 32 fs 'parallel data is converted into 30-bit / 64 fs' parallel data as a whole. , Each having a bit transmission rate of 3.
It is converted into 30 synthesized serial data of 6 Mbps.

Next, each of the bit transmission rates is set to 3.6M.
Each of the 30 synthesized serial data at bps is 8
After converting to synthetic parallel data of bit 8fs',
From the 8-bit / 8fs' synthesized parallel data, 8
Bit 8fs' parallel data and 8-bit 8f
The AUG data of s ′ is separated. Subsequently, the separated 8-bit / 8fs ′ parallel data includes 8-bit / 8fs data.
The transmission rate is converted to fs parallel data, and the 8-bit / 8 fs parallel data is converted to serial data having a bit transmission rate of 3.072 Mbps. As a result, the 30 AES / EBU audio signals DACD1 to DACD30 are reproduced.

FIG. 17 shows such an audio dividing unit 1.
20 shows a specific example of a configuration for converting multiplex parallel audio data DCAC of 4 bits / 480 fs' into 30 pieces of combined serial data each having a bit transmission rate of 3.6 Mbps. In the configuration example shown in FIG. 17, 4-bit / 480 fs ′ multiplexed parallel audio data DCAC is
1 and subjected to S / P conversion processing,
The data is converted to 32 fs' parallel data DPAC. S
60 bits / 32 fs ′ obtained from / P conversion section 121
Is supplied to the P / S conversion unit 122, and is subjected to P / S conversion processing, and is formed by 30 pieces of combined serial data DACD1 ′ to DACD15 ′ each having a bit transmission rate of 3.6 Mbps. 30
It is converted into parallel data DACD 'of 64 bits.

FIG. 18 shows a specific example of the audio dividing unit 120, which forms parallel data DACD 'of 30 bits / 64 fs' as a whole obtained as described above, each of which has a bit transmission rate of 3.6 Mbps. 30 synthesized serial data DACD1 'to DAC
A configuration example for reproducing the AES / EBU audio signal DACD1 from the combined serial data DACD1 'of D30' is shown. In the configuration example shown in FIG. 18, synthetic serial data DACD1 ′ having a bit transmission rate of 3.6 Mbps is supplied to the S / P conversion unit 123, subjected to the S / P conversion processing, and 8fs'
Is converted to the combined parallel data DPCM1. S / P
Synthesized parallel data DPCM obtained from converter 123
1 is supplied to the AUG data separation unit 124.

In the AUG data separation section 124, 8
The 8-bit / 8fs 'parallel data DPC1' and the 8-bit / 8fs 'AUG data DAUG are separated from the bit-8fs' combined parallel data DPCM1 and transmitted. The 8-bit / 8fs ′ parallel data DPC1 ′ obtained from the AUG data separation unit 124 is
The data is supplied to the FIFO memory unit 125.

In the FIFO memory unit 125, the parallel data DPC1 'is written under the control of the write control signal QWE in accordance with a write clock QW having a frequency of 8fs', and the written parallel data DPC1' is written.
1 ′ is read according to a read clock QR having a frequency of 8 fs under the control of the read control signal QRE,
It is transmitted as 8-bit / 8fs parallel data DPC1. At this time, the parallel data D of 8 bits / 8 fs
The beginning of each block in PC1 is 8 bits / 8f
It is earlier by 64 frames of the parallel data DPC1 than the start of each block in the parallel data DPC1 'of s'.

8 sent from FIFO memory unit 125
The bit / 8 fs parallel data DPC1 is supplied to the P / S converter 126. In the P / S conversion unit 126, the 8-bit / 8fs parallel data DPC1 from the FIFO memory unit 125 is subjected to P / S conversion processing to be serialized, and the bit transmission rate is set to 3.072 Mb.
The AES / EBU audio signal DACD1 at ps is reproduced.

In one specific example of the above-described audio division unit 120, each of them has a bit transmission rate of 3.6 Mbps.
30 combined serial data DACD1 'to DA
Synthesized serial data DACD2 'of CD30'
Each of the DACDs 30 'is subjected to the same processing as in the case of the composite serial data DACD1', and AES / E
In the same manner as BU audio signal DACD1, AES /
Each of the EBU audio signals DACD2 to DACD30 is reproduced.

In another specific example of the audio division unit 120, the 4-bit / 27 MHz, that is, 4-bit / 480fs ′ multiplexed parallel audio data DCAC obtained from the video / audio division unit 113 is obtained. Sets the bit transmission rate to 3.6 Mbps3
0 synthesized serial data DACD1 'to DACD3
The entirety of 0 'is treated as 30-bit / 64fs' synthetic parallel data, and then 30-bit / 64fs 'parallel data and 30-bit / 64fs' AUG data are separated. Then, the separated 30 bits 64
fs' parallel data, 30 systems of AES / EBU each having a bit transmission rate of 3.072 Mbps
The audio signals DACD1 to DACD30 are reproduced.

FIG. 19 shows such an audio dividing unit 1.
In another specific example of the 20th embodiment, 30 systems of AES / EBU audio signals DACD1 to DACD3 from the 4-bit / 480 fs' multiplexed parallel audio data DCAC.
5 shows a configuration example for reproducing 0. In the configuration example shown in FIG. 19, the 4-bit / 27 MHz from the video / audio division unit 113, that is, 4-bit / 480f
The s' multiplexed parallel audio data DCAC is S /
Supplied to the P conversion unit 130, subjected to the S / P conversion processing,
It is converted to 60-bit 32 fs' parallel data DPAC. The parallel data DPAC obtained from the S / P conversion unit 130 is supplied to the P / S conversion unit 131,
After undergoing the S conversion process, the data is converted into 30-bit / 64 fs' parallel data DPCM.

The parallel data DPCM obtained from the P / S converter 131 is converted into an AUG data separator 132.
Supplied to In the AUG data separation unit 132,
From 30-bit / 64 fs' parallel data DPCM, to 30-bit / 64 fs' parallel data DPC '
And AUG data DAUG of 30 bits / 64 fs' are transmitted separately. 30-bit 64 fs' parallel data DP obtained from the AUG data separation unit 132
C ′ is supplied to the FIFO memory unit 133.

In the FIFO memory unit 133, the parallel data DPC 'is written according to a write clock QW having a frequency of 64 fs' under the control of the write control signal QWE, and the written parallel data DP is written.
C ′ is read in accordance with a read clock QR having a frequency of 64 fs under the control of the read control signal QRE to form 30-bit / 64 fs parallel data as a whole, each having a bit transmission rate of 3.072M.
30 bits of AES, which is serial data at bps
/ EBU audio signals DACD1 to DACD30 are obtained.

In the audio dividing unit 120, each is serial data having a bit transmission rate of 3.072 Mbps obtained as described above.
30 AES / EBU audio signals DACD1-
The DACD 30 is supplied to the bi-phase mark modulator 134 as shown in FIG. The bi-phase mark modulation section 134 performs bi-phase mark modulation on each of the AES / EBU audio signals DACD1 to DACD30, and outputs the AES / EBU audio signal DAC
AES / EBU audio signals DAC1 to DA that are biphase mark modulated based on D1 to DACD30, respectively.
Form C30. Such AES / EBU audio signals DAC1 to DAC30 modulated with the biphase mark modulation
Each have a sampling frequency of fs = 48 kHz and a bit transmission rate of 128 × 48/1000 = 6.14, which corresponds to twice the bit transmission rate of each of the AES / EBU audio signals DACD1 to DACD30.
4 Mbps.

FIG. 21 shows still another specific example of the audio multiplexing unit 88 in the transmission / reception system C shown in FIG. 11, in which AES / EBU audio signals DACD1 to DACD are used.
Multiplexed parallel audio data DCAC based on D30
An example of a configuration for obtaining the above will be described. In the configuration example shown in FIG. 21, the AES / EBU audio signals DACD1 to DACD1
DACD 30 is an AES / EBU audio signal DAC
D1 to DACD15 and AES / EBU audio signal D
It is divided into ACD16 to DACD30, and AES / EB
U audio signals DACD1 to DACD15 are treated as parallel data of 15 bits / 64fs, and
AES / E is supplied to the FO memory unit 134 and
When the BU audio signals DACD16 to DACD30 are 1
It is treated as 5-bit 64fs parallel data,
The data is supplied to the FIFO memory unit 135.

In the FIFO memory unit 134, 15
AE treated as parallel data of 64 bits / bit
S / EBU audio signals DACD1 to DACD15
Changes the frequency to 6 under the control of the write control signal QWE.
AES / EBU audio signals DACD <b> 1 to DACD <b> 1 written in accordance with a write clock QW of 4 fs.
The DACD 15 is read out under the control of the read control signal QRE in accordance with a read clock QR having a frequency of 64 fs' and sent out as 15-bit 64 fs' parallel data DPC1 '. At this time, the parallel data DPC1 'is an AES / EBU audio signal DACD treated as parallel data of 15 bits / 64 fs.
The AES / EBU audio signals DACD1 to DACD15 are delayed by 64 frames as compared with the AES / EBU15. That is, 15 bits 64f
The beginning of each block in the s 'parallel data DPC1' is AES / EBU audio signals DACD1 to DACD1-D treated as 15-bit 64fs parallel data.
Compared to the beginning of each block in ACD15,
ES / EBU audio signals DACD1-DACD15
Is delayed by 64 frames.

1 sent from FIFO memory unit 134
The 5-bit 64fs 'parallel data DPC1' is
The data is supplied to the AUG data insertion unit 136. The AUG data insertion unit 136 is also supplied with AUG data DAUG converted into parallel data of 15 bits / 64 fs ′. A
The UG data DAUG is equivalent to 33 frames in the parallel data DPC1 ', and has block synchronization pattern data, system number data, frame number data, subframe number data, etc. embedded therein.

In the AUG data insertion unit 136, the AUG data DAUG is inserted into the 33 frame portion at the end of each block in the parallel data DPC1 ', and the parallel data DPC1' into which the AUG data DAUG is inserted is converted into the parallel data DPC1 '. 15 bits 64f
The AUG data insertion unit 136 sends out the composite parallel data DPCM1 of s ′. AUG data insertion unit 1
The 15-bit / 64 fs ′ synthesized parallel data DPCM1 from 36 is supplied to the S / P converter 137. S
In the / P conversion unit 137, 15 bits · 64fs ′
Is subjected to S / P conversion on the combined parallel data DPCM1 of 30 bits / 32 fs' parallel data DPAC.
Converted to 1.

The parallel data DPAC1 obtained from the S / P converter 137 is supplied to the P / S converter 138. In the P / S converter 138, 30 bits / 32 bits
The P / S conversion is performed on the fs 'parallel data DPAC1 to form 2-bit / 480 fs' parallel data, which is transmitted as 2-bit / 27 MHz multiplexed parallel audio data DCAC1.

On the other hand, in the FIFO memory section 135, AES / EBU audio signals DACD16 to DACD16 to DA treated as parallel data of 15 bits / 64fs.
The CD 30 is written according to the write clock QW having a frequency of 64 fs under the control of the write control signal QWE, and the written AES / EBU audio signal DA is written.
The read clock Q having a frequency of 64 fs' is controlled under the control of the read control signal QRE.
It is read according to R and sent out as parallel data DPC2 'of 15 bits / 64fs'. At this time, the parallel data DPC2 'is different from the AES / EBU audio signals DACD16 to DACD30 which are treated as 15-bit / 64fs parallel data.
The EBU audio signals DACD16 to DACD30 are delayed by 64 frames. That is, 15
The start of each block in the parallel data DPC2 'of 64 bits / bit is compared with the start of each block in the AES / EBU audio signals DACD16 to DACD30 treated as parallel data of 15 bits / 64fs. DACD
It is assumed to be delayed by 64 frames from 16 to DACD30.

1 sent from FIFO memory unit 135
The 5-bit 64fs 'parallel data DPC2'
The data is supplied to the AUG data insertion unit 140. The AUG data insertion unit 140 is also supplied with AUG data DAUG converted into parallel data of 15 bits / 64 fs ′. A
The UG data DAUG is equivalent to 33 frames in the parallel data DPC2 ', and has block synchronization pattern data, system number data, frame number data, subframe number data, and the like embedded therein.

In the AUG data insertion unit 140, the AUG data DAUG is inserted into the 33 frame portion at the end of each block in the parallel data DPC2 ', and the parallel data DPC2' into which the AUG data DAUG is inserted is converted into the parallel data DPC2 '. 15 bits 64f
The AUG data insertion unit 140 sends out the composite parallel data DPCM2 of s ′. AUG data insertion unit 1
The 15-bit / 64 fs ′ synthesized parallel data DPCM2 from 40 is supplied to the S / P converter 141. S
In the / P conversion section 141, 15 bits · 64 fs ′
The S / P conversion is performed on the composite parallel data DPCM2 of 30 bits / 32 fs' parallel data DPAC.
Converted to 2.

The parallel data DPAC2 obtained from the S / P converter 141 is supplied to the P / S converter 142. In the P / S converter 142, 30 bits / 32 bits
The P / S conversion is performed on the fs 'parallel data DPAC2 to form 2-bit / 480 fs' parallel data, which is transmitted as 2-bit / 27 MHz multiplexed parallel audio data DCAC2.

In this manner, the 2-bit / 27 MHz multiplexed parallel audio data DCAC1 obtained from the P / S converter 138 and the 2-bit / 27MHz multiplexed parallel audio data DCAC2 obtained from the P / S converter 142 are The entire data is treated as 4-bit / 27 MHz parallel data, and is 4-bit / 27 MHz multiplexed parallel audio data DCAC.

FIG. 22 shows another example of the audio dividing section 120 in the transmission / reception system D shown in FIG. 12, in which 30 systems of AES / EBU from the 4-bit / 480 fs' multiplexed parallel audio data DCAC.
4 shows a configuration example for reproducing audio signals DACD1 to DACD30. In the configuration example shown in FIG. 22, the 4-bit
27 MHz, that is, 4-bit / 480 fs' multiplexed parallel audio data DCAC is converted to 2-bit / 480 fs
s 'multiplexed parallel audio data DCAC1 and 2-bit 480 fs' multiplexed parallel audio data D
CAC2, and 2-bit / 480 fs ′ multiplexed parallel audio data DCAC1 is converted by S / P converter 1
In addition, the 2-bit / 480 fs ′ multiplexed parallel audio data DCAC2 is supplied to the S / P converter 151.

In S / P conversion section 150, 2-bit / 480 fs' multiplexed parallel audio data DCA
C1 undergoes S / P conversion processing, and is 30 bits / 32f
It is converted into parallel data DPAC1 of s ′. S / P
Parallel data DPAC1 obtained from conversion section 150
Is supplied to the P / S conversion unit 152, and is subjected to P / S conversion processing to be converted into 15-bit 64 fs ′ synthesized parallel data DPCM1.

The combined parallel data DPCM1 obtained from the P / S converter 152 is supplied to the AUG data separator 153. In the AUG data separation unit 153, the synthesized parallel data D of 15 bits / 64 fs'
From the PCM1, the 15-bit 64fs' parallel data DPC1 'and the 15-bit 64fs' AUG data DAUG are separated and transmitted. The 15-bit / 64 fs ′ parallel data DPC1 ′ obtained from the AUG data separation unit 153 is supplied to the FIFO memory unit 155.

In the FIFO memory unit 155, the parallel data DPC1 'is converted into a write clock QW having a frequency of 64 fs' under the control of the write control signal QWE.
Parallel data DP written and written according to
C1 'is read out under the control of the read control signal QRE in accordance with a read clock QR having a frequency of 64 fs, forming 15-bit / 64 fs parallel data as a whole, each having a bit transmission rate of 3.072M.
15 bits of AES, which is serial data with bps
/ EBU audio signals DACD1 to DACD15 are obtained.

In the S / P converter 151, 2
The 480 fs ′ multiplexed parallel audio data DCAC2 is subjected to S / P conversion processing,
It is converted to 2fs' parallel data DPAC2. S
Data DPAC obtained from / P conversion section 151
2 is supplied to a P / S conversion unit 157, and is subjected to P / S conversion processing to be converted into 15-bit 64 fs ′ synthesized parallel data DPCM2.

The parallel data DPCM2 obtained from the P / S conversion section 157 is
9. In the AUG data separation unit 159, the combined parallel data DP of 15 bits / 64 fs' is used.
From the CM2, the 15-bit 64fs' parallel data DPC2 'and the 15-bit 64fs' AUG data D
The AUG is transmitted separately. The 15-bit / 64 fs ′ parallel data DPC2 ′ obtained from the AUG data separation unit 159 is supplied to the FIFO memory unit 160.

In the FIFO memory unit 160, the parallel data DPC2 'is converted into a write clock QW having a frequency of 64 fs' under the control of the write control signal QWE.
Parallel data DP written and written according to
C2 'is read out under the control of the read control signal QRE in accordance with the read clock QR having a frequency of 64 fs, forming 15-bit / 64 fs parallel data as a whole, each having a bit transmission rate of 3.072M.
15 bits of AES, which is serial data with bps
/ EBU audio signals DACD16 to DACD30 are obtained.

In this way, the FIFO memory unit 155
And 160, each of which has a bit transmission rate of 3.072.
30 AEs that are serial data at Mbps
The S / EBU audio signals DACD1 to DACD30 are obtained.

In the transmission / reception system D shown in FIG. 12, a serial digital video signal 6
System SDI video signals DSVD1 to DSVD6
/ P conversion sections 171 to 176. Each of the SDI video signals DSVD1 to DSVD6 has a bit transmission rate of 270 Mbps.

In S / P converters 171 to 176,
Each of the SDI video signals DSVD1 to DSVD6 has S / D
P conversion is performed, and each is 10 bits / 27 MHz 10 bits.
Six parallel video data DPVD1 to DPVD6, which are bit word string data, are formed. That is, the S / P signals are applied to the six SDI video signals DSVD1 to DSVD6.
The six parallel video data DPVD1 to DPVD6 which are converted to make the transmission rates substantially equal to each other
Is formed. Then, the S / P conversion units 171 to 171
176, the parallel video data DPVD respectively obtained from
1 to DPVD6 are supplied to the video / audio multiplexing unit 177.

AES / EBU audio signals DAD1 to DAD30 of 30 systems, which are serial digital audio signals of a plurality of systems, are supplied to audio multiplexing section 178.
Supplied to AES / EBU audio signal DAD1
To DAD30 are subjected to bi-phase mark modulation, and the sampling frequency is set to, for example, fs = 48.
kHz and the bit transmission rate is 128 × 48/100
It is assumed that 0 = 6.144 Mbps.

In audio multiplexing section 178, AE
The S / EBU audio signals DAD1 to DAD30 shown in FIG. 13 are based on the assumption that the S / EBU audio signals DAD1 to DAD30 are synchronized with each other for all blocks, frames, and subframes.
It is supplied to a biphase mark demodulation unit similar to the biphase mark demodulation unit 89 relating to C30.

In such a bi-phase mark demodulation unit, AES / EBU audio signals DAD1 to DAD3
0, detection of preambles Z, X, and Y is performed as shown in FIG. 25, and a synchronization control signal is formed based on the detected preambles Z, X, and Y, Synchronous control is performed. Under such circumstances, in the bi-phase mark demodulation unit, the AES / EBU to which the bi-phase mark modulation is applied is used.
A bi-phase mark demodulation process is performed on each of the audio signals DAD1 to DAD30, and demodulated A based on the AES / EBU audio signals DAD1 to DAD30, respectively.
ES / EBU audio signals DADD1 to DADD30
To form Each of the demodulated AES / EBU audio signals DADD1 to DADD30 has a sampling frequency of fs = 48 kHz and a bit transmission rate of AES / EBU audio signals DAD1 to DAD3.
64, corresponding to 1/2 of each bit transmission rate of 0
× 48/1000 = 3.072 Mbps.

In the audio multiplexing section 178, each of the AES / E signals obtained from the bi-phase mark demodulating section has a bit transmission rate of 3.072 Mbps.
Multiplexed parallel audio data DCAD is formed based on the BU audio signals DADD1 to DADD30.
Multiple parallel audio data DCAD is 4 bits
This is 4-bit word string data of 27 MHz, and the transmission rate is made substantially equal to each of the parallel video data DPVD1 to DPVD6 supplied to the video / audio multiplexing unit 177. Then, the multiplexed parallel audio data DCAD obtained from the audio multiplexing unit 178 is supplied to the video / audio multiplexing unit 177.

In a specific example of the audio multiplexing section 178, first, the AES / EBU audio signal DADD1
ＤDADD30 is converted from a configuration in which one block is formed by 192 frames to a configuration in which one block is formed by 225 frames, and the sampling frequency is changed from fs = 48 kHz to fs ′ = 56.25 k in appearance.
Hz, and performs a process of inserting AUG data forming 33 frames into each block.
/ EBU audio signals DADD1 to DADD30 each have a bit transmission rate of 64 × 56.25 / 1000 =
It is converted to synthesized serial data of 3.6 Mbps.

Next, AES / AUG / AUG / AUG / AGS / AUG / AES / AUG / AES / AUG / AES / AUG / AES / AUG / AES
30 synthesized serial data based on each of the EBU audio signals DADD1 to DADD30 are converted into 30 bits.
The data is converted into 60-bit / 32 fs 'parallel data by treating it as 4 fs' parallel data and performing S / P conversion. Then, further, the 60 bits and 32
P / S conversion is performed on the fs' parallel data to convert it into 4-bit / 480 fs' parallel data, which is converted into 4-bit / 480 fs', that is, 4-bit / 27 MHz 4-bit word string data. The data DCAD is formed.

In a specific example of such an audio multiplexing unit 178, each of the audio multiplexing units 178 has a bit transmission rate of 3.072M.
The bit transmission rate is 64 × 56.25 / 1000 = 3.6 Mbp based on each of the 30 AES / EBU audio signals DADD1 to DADD30 at 30 bps.
The configuration example for obtaining each of the thirty synthesized serial data s is the same as the configuration example relating to the AES / EBU audio signal DACD1 shown in FIG.

In one specific example of the audio multiplexing section 178, 30 pieces of synthesized serial data each having a bit transmission rate of 3.6 Mbps obtained as described above are treated as 30-bit 64 fs' parallel data. The configuration example for obtaining the multiplexed parallel audio data DCAD as 4-bit / 27 MHz 4-bit word string data based thereon is the same as the configuration example relating to the combined parallel data DACD 'shown in FIG. You.

In another specific example of audio multiplexing section 178, AES / EBU audio signals DADD1-DADD
The entire ADD 30 is treated as 30-bit / 64 fs parallel data, and first, a transmission rate conversion for converting the data into 30-bit / 64 fs' parallel data is performed.
AES / EBU audio signal D is processed by inserting AUG data forming 33 frames into each block.
Based on ADD1 to DADD30, parallel data of 30 bits / 64 fs ′ in which AUG data forming 33 frames is inserted in each block is obtained.

Next, S / P conversion processing is performed on 30-bit / 64 fs 'parallel data in which AUG data forming 33 frames is inserted in each block to convert the data into 60-bit / 32 fs' parallel data. Subsequently, P / S conversion processing is performed on the 60-bit / 32 fs' parallel data to convert it into 4-bit / 480 fs' parallel data, and the 4-bit / 480 fs', that is, 4-bit / 27 MHz 4-bit data is converted. The multiplexed parallel audio data DCAD is formed as bit word string data.

In another specific example of such audio multiplexing section 178, AES / EBU audio signal DAD
An example of a configuration for obtaining the multiplexed parallel audio data DCAD based on D1 to DADD30 is described in AES / EBU audio signals DACD1 to DACD3 shown in FIG.
This is the same as the configuration example relating to 0.

Parallel video data DPVD1 to DPVD6, each of which is obtained from the S / P converters 171 to 176 and is 10-bit / 27 MHz parallel data,
10 bits / 27 obtained from audio multiplexing section 178
In the video / audio multiplexing unit 177 supplied with the multiplexed parallel audio data DCAD which is parallel data of MHz, the parallel video data DPVD
1 to DPVD6 are handled as parallel data of 60 bits / 27 MHz, and the parallel video data D
A multiplexing process is performed on the PVD1 to DPVD6 and the multiplexed parallel audio data DCAD to obtain a 16-bit / 480f
The complex parallel data DPXD of s × 4 = 16 bits / 108 MHz is formed.

The composite parallel data DPXD obtained from the video / audio multiplexing section 177 is supplied to an 8B / 10B conversion section 179. The 8B / 10B conversion unit 179 performs an 8B / 10B conversion process on the composite parallel data DPXD. In the 8B / 10B conversion process, the complex parallel data DPXD is divided into 8 bits by dividing 16 bits forming each word into two 8-bit groups each having 8 bits. The conversion is performed by sequentially converting each of the 8-bit data into 10-bit data according to a conversion table prepared in advance. At this time, a 10-bit code that does not appear as long as it follows the conversion table is embedded in the sequentially obtained 10-bit data as a synchronization detection reference code.

Subsequently, in the 8B / 10B conversion section 179, 20-bit word string data is formed by superimposing two pieces of 10-bit data sequentially obtained by the 8B / 10B conversion processing on each other. Derived as complex parallel data DPZD of 108 bits. The composite parallel data DPZD obtained from the 8B / 10B converter 179 in this manner is supplied to the FC transceiver 110.

In the FC transceiver 110, 8B
20 bits from the / 10B converter 179, 108 MHz
Of the composite parallel data DPZD of the P / S converter 180
Is converted to composite serial data DSZD having a bit transmission rate of 2.16 Gbps, and the composite serial data DSZD is transmitted.

In the transmission / reception system C shown in FIG. 11, the bit transmission rate transmitted by the FC transceiver 110 in the transmission / reception system D shown in FIG.
6 Gbps composite serial data DSZD is used for FC
The signal is received by the transceiver 101 and supplied to the S / P converter 181 in the FC transceiver 101.

The S / P converter 181 detects a synchronization detection reference code portion in the composite serial data DSZD having a bit transmission rate of 2.16 Gbps,
The S / P conversion is performed based on the synchronization detection reference code portion detected in the composite serial data DSZD to reproduce the 20-bit 108 MHz composite parallel data DPZD. The composite parallel data DPZD obtained from the S / P converter 181 is supplied to the 10B / 8B converter 182.

The 10B / 8B converter 182 performs a 10B / 8B conversion process on the composite parallel data DPZD. The 10B / 8B conversion process detects a synchronization detection reference code in 10 bits forming each 20-bit word of the composite parallel data DPZD, and uses the detected synchronization detection reference code as a reference to generate the composite parallel data DPZD.
Each of the 10 bits forming each 20-bit word of the ZD is sequentially converted into 8-bit data according to a conversion table prepared in advance.

Subsequently, in the 10B / 8B converter 182, 8-bit data sequentially obtained by the 10B / 8B conversion processing is superimposed two by two to form 16-bit word string data. Derived as complex parallel data DPXD of 108 bits. The composite parallel data DPXD obtained from the 10B / 8B conversion unit 182 in this way is supplied to the video / audio division unit 183.

In the video / audio dividing section 183, 16-bit / 108 MHz composite parallel data D
PXD is converted into 64-bit / 27 MHz parallel data, and from the 64-bit / 27 MHz parallel data, six 10-bit / 27 MHz parallel video data DPVD1 to DPVD6 are converted into 60-bit / 27 MHz parallel data as a whole. At the same time, the multiplexed parallel audio data DCAD of 4 bits / 27 MHz is divided. In the video / audio division unit 183, the total is 60 bits / 27M
10-bit 27-MHz parallel video data DPVD1 to DPV obtained as Hz parallel data
VD6 is supplied to P / S converters 184 to 189, respectively. The 4-bit / 27 MHz multiplexed parallel audio data DCAD obtained in the video / audio division unit 183 is supplied to the audio division unit 190.

In P / S converters 184 to 189,
P / S conversion is performed on each of the six 10-bit 27 MHz parallel video data DPVD1 to DPVD6, and each of the parallel video data has a bit transmission rate of 270 Mbps.
The SDI video signals DSVD1 to DSVD6 of the system are reproduced.

In the audio division section 190, 4-bit / 27 MHz multiplexed parallel audio data DC
AES / EBU audio signal DA of 30 systems from AD
DD1 to DADD30 are reproduced.

At this time, in one specific example of the audio division unit 190, first, 4 bits / 27 MHz, that is, 4 bits
The bit / 480 fs 'multiplexed parallel audio data DCAD is converted to 60-bit / 32 fs' parallel data, and the 60-bit / 32 fs 'parallel data is converted into 30-bit / 64 fs' parallel data as a whole. , Each having a bit transmission rate of 3.
It is converted into 30 synthesized serial data of 6 Mbps.

Next, each of the bit transmission rates is set to 3.6M.
Each of the 30 synthesized serial data at bps is 8
After converting to synthetic parallel data of bit 8fs',
From the 8-bit / 8fs' synthesized parallel data, 8
Bit 8fs' parallel data and 8-bit 8f
The AUG data of s ′ is separated. Subsequently, the separated 8-bit / 8fs ′ parallel data includes 8-bit / 8fs data.
The transmission rate is converted to fs parallel data, and the 8-bit / 8 fs parallel data is converted to serial data having a bit transmission rate of 3.072 Mbps. Thereby, the AES / EBU audio signals DADD1 to DADD30 of 30 systems are reproduced.

In one specific example of such an audio dividing unit 190, the 4-bit / 480 fs' multiplexed parallel audio data DCAD is converted into a 30-bit
A configuration example for forming 64 fs' parallel data and converting each to 30 synthesized serial data with a bit transmission rate of 3.6 Mbps is shown in FIG. 17 with a configuration example involving multiplexed parallel audio data DCAC. The same is assumed.

In one specific example of the audio separating section 190, a total of 30 audio signals obtained as described above are obtained.
A configuration example for reproducing AES / EBU audio signals DADD1 to DADD30 from each of 30 synthesized serial data having a bit transmission rate of 3.6 Mbps, forming parallel data of 64 bits per bit, is shown in FIG. 18. Synthesized serial data DACD shown in FIG.
This is the same as the configuration example relating to 1 ′.

In another specific example of the audio division unit 190, the 4-bit / 27 MHz, that is, 4-bit / 480fs' multiplexed parallel audio data DCAD obtained from the video / audio division unit 183 is obtained. Sets the bit transmission rate to 3.6 Mbps3
The entirety of zero synthesized serial data is 30 bits 64f
Treated as synthetic parallel data of s', then 30
Bit 64fs' parallel data and 30 bit 6
4fs' AUG data is separated. Subsequently, from the separated parallel data of 30 bits / 64 fs ′, each of the 30 bits has a bit transmission rate of 3.072 Mbps.
AES / EBU audio signals DADD1 to DA
Play DD30.

In another specific example of such audio division section 190, 30 systems of AES / E from 4-bit / 480 fs' multiplexed parallel audio data DCAD.
The configuration example for reproducing the BU audio signals DADD1 to DADD30 is similar to the configuration example relating to the multiplexed parallel audio data DCAC shown in FIG.

In the audio division section 190, each is serial data having a bit transmission rate of 3.072 Mbps, obtained as described above.
30 AES / EBU audio signals DADD1
The DADD 30 is supplied to a biphase mark modulation unit similar to the biphase mark modulation unit 127 related to the AES / EBU audio signals DADC1 to DACD30 shown in FIG. In such a bi-phase mark modulation unit, the AES / EBU audio signals DADD1 to DADD1
Apply bi-phase mark modulation to each of DADD30,
AES / EBU audio signals DADD1 to DADD3
AES / Biphase mark modulated AES /
EBU audio signals DAD1 to DAD30 are formed. AES / EB modulated by such bi-phase mark modulation
The U audio signals DAD1 to DAD30 each have a sampling frequency of fs = 48 kHz and a bit transmission rate of AES / EBU audio signals DADD1 to DADD30.
128 × 48/1000 = 6.144 Mbps, which is twice the bit transmission rate of each of the ADDs 30.

In still another specific example of audio multiplexing section 178 in transmission / reception system D shown in FIG.
A configuration example for obtaining the multiplexed parallel audio data DCAD based on the / EBU audio signals DADD1 to DADD30 is similar to the configuration example relating to the AES / EBU audio signals DACD1 to DACD30 shown in FIG.

In such a configuration example, AES / EBU
The audio signals DADD1 to DADD30 are AES /
EBU audio signals DADD1 to DADD15 and AE
S / EBU audio signals DADD16 to DADD30
AES / EBU audio signal DADD
1 to DADD15 are treated as parallel data of 15 bits / 64 fs, and are multiplexed parallel audio data of 2 bits / 27 MHz, and AES / EB.
The U audio signals DADD16 to DADD30 are 15
Bits are treated as 64 fs parallel data and 2
Bit 27 MHz multiplexed parallel audio data. Then, the AES / EBU audio signal DADD
1 to DADD15, 2 bits / 27 MHz multiplexed parallel audio data, and 2 bits / bits based on AES / EBU audio signals DADD16 to DADD30.
27 MHz multiplexed parallel audio data is treated as 4-bit / 27 MHz parallel data as a whole, and becomes 4-bit / 27 MHz multiplexed parallel audio data DCAD.

Further, in still another specific example of the audio division unit 190 in the transmission / reception system C shown in FIG. 11, 30 systems of AES / EBU audio signals DADD1 to DADD30 are converted from 4-bit / 480 fs' multiplexed parallel audio data DCAD. The configuration example for reproduction is the same as the configuration example relating to the 2-bit / 480 fs' multiplexed parallel audio data DCAC1 and DCAC2 shown in FIG.

In such a configuration example, 4 bits / 27 MHz from the video / audio division unit 183, that is,
The 4-bit / 480 fs 'multiplexed parallel audio data DCAD is divided into two 2-bit / 480 fs' multiplexed parallel audio data and two 2-bit
The 15 AES / EBU audio signals DADD1 to DADD15 are reproduced based on one of the 480 fs ′ multiplexed parallel audio data, and 2
15 systems of AES / EB based on the other of the two 2-bit / 480 fs' multiplexed parallel audio data
The U audio signals DADD16 to DADD30 are reproduced.

The examples shown in FIGS. 1 and 2 as described above,
In each of the examples shown in FIGS. 11 and 12, conversion of six SDI video signals into a plurality of parallel video data, fifteen or thirty AES /
For example, an integrated circuit device for digital signal processing, etc., for forming multiplexed parallel audio data based on an EBU audio signal, multiplexing a plurality of parallel video data and multiplexed parallel audio data, and forming and transmitting composite serial data. With means that can be prepared relatively easily by using the method, it is possible to carry out efficiently and at a reduced cost. In addition, the transmitted composite serial data can reliably reproduce the original six SDI video signals and the fifteen or thirty AES / EBU audio signals on the receiving side.

The standard for multiplexing 56 AES / EBU audio signals is MADI (Mult).
Also known as ichannel Audio Digital Interface). Therefore, for example, in the examples shown in FIGS. 1 and 2 described above, the audio multiplexing units 18 and 68 and the audio dividing units 50 and 80 can be configured as a unit that handles signals obtained in accordance with MADI. In such a case, the configuration can be further simplified.

[0199]

As is apparent from the above description, the digital signal transmission method according to any one of the first to fourteenth aspects of the present invention, or the digital signal transmission method according to the present invention. Claim 1 in the scope
According to the digital signal transmission apparatus of any one of the fifth to twenty-fifth aspects, a plurality of serial digital video signals are converted into a plurality of parallel video data having transmission rates substantially equal to each other. At the same time, multiplexed parallel audio data based on a plurality of serial digital audio signals and having a transmission rate substantially equal to each of the plurality of parallel video data is formed, and the plurality of parallel video data and the multiplexed parallel audio data are combined. Multiplex transmission is performed by transmitting the serial data.

Under these circumstances, each of the plurality of serial digital video signals can be, for example, an SDI video signal, and each of the plurality of serial digital audio signals can be, for example, an AES / EBU audio signal. It can be a signal. And in that case,
Conversion of multiple serial digital video signals into multiple parallel video data, formation of multiple parallel audio data based on multiple serial digital audio signals, multiplexing and decoding of multiple parallel video data and multiple parallel audio data The formation and transmission of serial data, for example, can be performed efficiently and at low cost by means that can be relatively easily prepared using existing digital signal processing integrated circuit elements and the like. it can. In addition, the composite serial data to be transmitted can reliably reproduce the original plurality of serial digital video signals and the plurality of serial digital audio signals on the receiving side.

Accordingly, multiplex transmission of a plurality of serial digital video signals, each of which is, for example, an SDI video signal, and a plurality of serial digital audio signals, each of which is, for example, an AES / EBU audio signal, is performed. It can be performed efficiently by means that can be prepared relatively easily, cost can be reduced, and the original plurality of serial digital video signals and the plurality of serial digital audio signals can be reliably received on the receiving side. Will be able to be played back.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a digital signal transmission method according to an embodiment of the present invention; FIG. 1 is a diagram illustrating a digital signal transmission method according to an embodiment of the present invention; FIG. 22 is a block connection diagram showing a part of an example of a digital signal transmission device according to the invention described in any one of claims 21 to 21.

FIG. 2 is a block diagram showing an embodiment of a digital signal transmission method according to the present invention; FIG. 22 is a block connection diagram showing a part of an example of a digital signal transmission device according to the invention described in any one of claims 21 to 21.

FIG. 3 is a block connection diagram for explaining a specific example of an audio multiplexing unit in the examples shown in FIGS. 1 and 2;

FIG. 4 is a data bit configuration diagram used for describing an operation of the audio multiplexing unit in the examples shown in FIGS. 1 and 2;

FIG. 5 is a diagram illustrating a data bit configuration used for describing an operation of the audio multiplexing unit in the examples illustrated in FIGS. 1 and 2;

FIG. 6 is a block connection diagram for explaining a specific example of an audio multiplexing unit in the examples shown in FIGS. 1 and 2;

FIG. 7 is a block connection diagram used for explaining another specific example of the audio multiplexing unit in the examples shown in FIGS. 1 and 2;

FIG. 8 is a block connection diagram for explaining a specific example of an audio dividing unit in the examples shown in FIGS. 1 and 2;

FIG. 9 is a block connection diagram for explaining a specific example of an audio division unit in the examples shown in FIGS. 1 and 2;

FIG. 10 is a block connection diagram used for describing another specific example of the audio division unit in the example shown in FIGS. 1 and 2;

FIG. 11 is a diagram showing an example of a digital signal transmission method according to the invention according to any one of claims 1 to 3 and claims 8 to 14 in the claims of the present application. FIG. 26 is a block connection diagram showing a part of an example of a digital signal transmission device according to the invention described in any one of claims 15, 16 and 20 to 25 in the claims of the present invention.

FIG. 12 is a diagram showing an example of a digital signal transmission method according to the invention according to any one of claims 1 to 3 and claims 8 to 14 in the claims of the present application. FIG. 26 is a block connection diagram showing a part of an example of a digital signal transmission device according to the invention described in any one of claims 15, 16 and 20 to 25 in the claims of the present invention.

FIG. 13 is a block connection diagram for explaining an audio multiplexing unit in the examples shown in FIGS. 11 and 12;

FIG. 14 is a block connection diagram for explaining a specific example of an audio multiplexing unit in the examples shown in FIGS. 11 and 12;

FIG. 15 is a block connection diagram for explaining a specific example of an audio multiplexing unit in the examples shown in FIGS. 11 and 12;

FIG. 16 is a block connection diagram for explaining another specific example of the audio multiplexing unit in the examples shown in FIGS. 11 and 12;

FIG. 17 is a block connection diagram used for describing a specific example of an audio division unit in the examples shown in FIGS. 11 and 12;

FIG. 18 is a block connection diagram used for describing a specific example of an audio division unit in the examples shown in FIGS. 11 and 12;

FIG. 19 is a block connection diagram used for describing another specific example of the audio division unit in the examples shown in FIGS. 11 and 12.

FIG. 20 is a block connection diagram for explaining an audio dividing unit in the example shown in FIGS. 11 and 12;

FIG. 21 is a block connection diagram for explaining still another specific example of the audio multiplexing unit in the examples shown in FIGS. 11 and 12;

FIG. 22 is a block connection diagram for explaining still another specific example of the audio dividing unit in the examples shown in FIGS. 11 and 12;

FIG. 23 is a chart showing a data format for forming a digital video signal.

FIG. 24 is a chart showing a data format of a digital audio signal.

FIG. 25 is a chart showing a data format of a digital audio signal.

[Explanation of symbols]

11 to 16, 20, 24, 28, 41, 51, 53, 5
7, 61 to 66, 71, 81 to 86, 90, 94, 9
8, 111, 121, 123, 130, 137, 14
1,150,151,171-176,181 ... S
./P conversion unit, 17, 67, 87, 177... Video / audio multiplexing unit, 18, 68, 88, 178,.
・ Audio multiplexing unit, 21, 26, 55, 60, 9
1,96,125,133,134,135,155,
160... FIFO memory section, 22, 27, 92,
97, 136, 140 ... AUG data insertion unit, 2
3, 25, 29, 32, 44 to 49, 52, 56, 5
8,70,74-79,93,95,99,102,1
14 to 119, 122, 126, 131, 138, 14
2,152,157,180,184-189 ... P
/ S converter, 30, 100, 179 ... 8B / 10
B conversion unit, 31, 40, 101, 110 ... FC transceiver, 42, 69, 72, 112, 182 ...
・ 10B / 8B converter, 43, 73, 113, 183
... Video / audio division unit, 50, 80, 12
0, 190... Audio dividing section, 54, 59, 1
24, 132, 153, 159: AUG data separation unit, 89: Biphase mark demodulation unit, 127
... Biphase mark modulator

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 7/081 H04N 7/08 101 7/24 7/13 Z // H04L 25/49 F-term (reference) 5C059 LA02 PP16 RB01 RB10 RC02 RC11 RC32 SS13 SS30 UA24 UA32 UA38 5C063 AB07 AC05 CA34 DA05 DA13 EB49 5D045 DA20 5K028 AA06 EE03 KK03 KK12 NN02 SS06 SS16 SS26 5K029 AA18 DD02 GG03 HH21

Claims (25)

[Claims] A plurality of serial digital video signals are subjected to serial / parallel conversion to form a plurality of parallel video data having transmission rates substantially equal to each other, based on the plurality of serial digital audio signals. ,
Forming multiplexed parallel audio data having a transmission rate substantially equal to each of the plurality of parallel video data, and performing multiplexing processing on the plurality of parallel video data and the multiplexed parallel audio data to form composite parallel data A digital signal transmission method for performing parallel / serial conversion on the composite parallel data to form composite serial data, and transmitting the composite serial data. 2. The digital signal transmission method according to claim 1, wherein an 8-bit / 10-bit conversion process is performed on the composite parallel data before performing the parallel / serial conversion on the composite parallel data. 3. The digital signal transmission method according to claim 2, wherein, when performing 8-bit / 10-bit conversion processing on the composite parallel data, synchronization detection reference code data is embedded. 4. A plurality of serial digital audio signals are subjected to serial / parallel conversion to obtain a plurality of parallel audio data, and the plurality of parallel audio data are subjected to a multiplexing process. 4. The digital signal transmission method according to claim 1, wherein multiplexed parallel audio data based on the digital audio signal is formed. 5. The multiplex parallel audio data based on the plurality of serial digital audio signals is formed by treating the entirety of the serial digital audio signals as parallel audio data. The digital signal transmission method according to claim 2 or 3. 6. The transmission rate conversion and auxiliary data insertion for said plurality of serial digital audio signals in forming multiplex parallel audio data based on the plurality of serial digital audio signals. The digital signal transmission method according to claim 5. 7. The digital signal transmission method according to claim 6, wherein the auxiliary data includes synchronization pattern data when the auxiliary data is inserted. 8. The method according to claim 1, wherein each of the serial digital video signals of a plurality of systems follows a format of a serial digital interface (SDI) standardized as SMPTE259M. 2. A digital signal transmission method according to claim 1. 9. A system according to claim 1, wherein each of a plurality of serial digital audio signals has been subjected to bi-phase mark modulation in accordance with a serial digital audio format standardized as AES / EBU. The digital signal transmission method according to any one of claims 1 to 8. 10. When forming multiplexed parallel audio data based on a plurality of serial digital audio signals, a bi-phase mark demodulation process is performed on each of the plurality of serial digital audio signals to form a plurality of demodulated serial digital audio signals. 10. The digital signal transmission method according to claim 9, wherein 11. A serial / parallel converter for each of a plurality of demodulated serial digital audio signals to obtain a plurality of parallel audio data, and a multiplexing process for the plurality of parallel audio data to obtain a plurality of serial digital The digital signal transmission method according to claim 10, wherein multiplexed parallel audio data based on the audio signal is formed. 12. The digital audio system according to claim 10, wherein a plurality of demodulated serial digital audio signals are handled as parallel audio data as a whole to form multiplex parallel audio data based on a plurality of serial digital audio signals. Signal transmission method. 13. The transmission rate conversion and auxiliary data insertion for said plurality of demodulated serial digital audio signals when forming multiplexed parallel audio data based on the plurality of demodulated serial digital audio signals. The digital signal transmission method according to claim 12. 14. The digital signal transmission method according to claim 13, wherein the auxiliary data includes synchronization pattern data when the auxiliary data is inserted. 15. A serial / parallel converter for performing serial / parallel conversion on each of a plurality of systems of serial digital video signals to form a plurality of parallel video data having transmission rates substantially equal to each other; An audio multiplexing unit that forms multiplexed parallel audio data based on a serial digital audio signal and that has a transmission rate substantially equal to each of the plurality of parallel video data; and the plurality of parallel video data and the multiplexed parallel audio data. A video / audio multiplexing unit that performs multiplexing processing to form composite parallel data; and a parallel / serial conversion that performs parallel / serial conversion on the composite parallel data to form composite serial data and transmits the composite serial data. And a Digital signal transmission device is. 16. An 8-bit / 10-bit conversion process is performed on composite parallel data formed by a video / audio multiplexing unit, and the composite parallel data subjected to the 8-bit / 10-bit conversion process is directed to a parallel / serial conversion unit. 16. The digital signal transmission device according to claim 15, further comprising an 8-bit / 10-bit conversion unit for transmitting the digital signal. 17. An audio multiplexing unit performs serial / parallel conversion on each of a plurality of serial digital audio signals to obtain a plurality of parallel audio data.
17. The digital signal transmission device according to claim 15, wherein a multiplexing process is performed on the plurality of parallel audio data to form multiplexed parallel audio data based on the plurality of serial digital audio signals. 18. An audio multiplexing unit which forms multiplex parallel audio data based on the plurality of serial digital audio signals by treating the entirety of the plurality of serial digital audio signals as parallel audio data. The digital signal transmission device according to claim 15. 19. The digital signal transmission apparatus according to claim 17, wherein said audio multiplexing section performs transmission rate conversion and auxiliary data insertion for serial digital audio signals of a plurality of systems. 20. The system according to claim 15, wherein each of the plurality of serial digital video signals conforms to a serial digital interface (SDI) format standardized as SMPTE259M.
The digital signal transmission device according to any one of claims 1 to 19. 21. Each of a plurality of serial digital audio signals is subjected to bi-phase mark modulation according to a serial digital audio format standardized as AES / EBU. The digital signal transmission device according to any one of claims 15 to 20. 22. The digital signal according to claim 21, wherein the audio multiplexing section performs bi-phase mark demodulation processing on each of the serial digital audio signals of a plurality of systems to obtain a plurality of demodulated serial digital audio signals. Transmission equipment. 23. An audio multiplexing unit performs serial / parallel conversion on each of a plurality of demodulated serial digital audio signals to obtain a plurality of parallel audio data, and performs a multiplexing process on the plurality of parallel audio data. 23. The digital signal transmission apparatus according to claim 22, wherein multiplex parallel audio data is formed based on a plurality of serial digital audio signals. 24. An audio multiplexing unit which forms multiplex parallel audio data based on a plurality of serial digital audio signals by treating the whole of a plurality of demodulated serial digital audio signals as parallel audio data. Item 23. The digital signal transmission device according to item 22. 25. The digital signal transmission apparatus according to claim 23, wherein said audio multiplexing section performs transmission rate conversion and auxiliary data insertion for a plurality of demodulated serial digital audio signals.