JP2002176133A - Flat semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flat semiconductor device whose thickness of constituent members can be stably adjusted without generating the dislocation of the constituent members. SOLUTION: Three-layer solder plates 6, 7 which operate as thickness adjusting plates are arranged in the upper part and the lower part of a plurality of semiconductor chips 1. Thermal buffer plates 2, 3 and the plurality of semiconductor chips 1 are fixed and bonded via the solder plates 6, 7, and they are sandwiched and held between a pressure contact plate 4 as a collector cathode plate and a pressure contact plate 5 as an emitter electrode plate. When the solder plates 6, 7 are melted and solidified while being pressurized, the plurality of semiconductor chips 1 and the plates 2, 3 are fixed and bonded, the whole thickness of the semiconductor chips 1, the solder plates 6, 7 and the plates 2, 3 is set to a uniform height, and an equal pressurization force is applied to the plurality of semiconductor chips 1 which are arranged between the plates 4, 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat semiconductor device such as a flat insulated gate bipolar transistor having a structure in which a plurality of semiconductor chips are pressed together.

[0002]

2. Description of the Related Art FIG. 3 is a sectional view of a main part of a conventional flat type semiconductor device. A flat semiconductor device that uses a plurality of semiconductor chips 61 (for example, an IGBT chip and a freewheel diode chip) in a press-contact state, such as an insulated gate bipolar transistor (hereinafter, referred to as an IGBT) having a flat structure, is used. , Two opposed pressure contact electrode plates 66, 6
7, a semiconductor chip 61 and a structure in which thermal buffer plates 62 and 63 are stacked on both upper and lower surfaces of the semiconductor chip 61 are sandwiched therebetween, which is disclosed in JP-A-8-88240.

The heat buffer plates 62 and 63 superposed on both surfaces of the semiconductor chip 61 have a thickness of 1 to 3 mm with good heat conduction.
Heat generated by the semiconductor chip 61
There is a function to radiate from both upper and lower surfaces of the semiconductor chip 61,
So-called double-sided cooling is enabled. Japanese Unexamined Patent Publication No. Hei 8
In the case of -88240, if the semiconductor chip 61 and the thermal buffer plates 62 and 63 are uneven in thickness or pressurized,
Variations occur in the pressure applied. Then, the semiconductor chip 61, the heat buffer plates 61 and 63, the press-contact electrode plate 66,
It is difficult to obtain 67 good electrical contacts. In order to solve this, the pressure contact electrode plates 66 and 67 and the heat buffer plate 6
Thickness correction plates 64 and 65 made of a soft metal sheet of Ag foil are interposed between 2 and 63 to ensure good electrical contact between the semiconductor chip 61, the thermal buffer plates 62 and 63, and the press-contact electrode plates 66 and 67. are doing.

[0004]

However, these techniques have problems. Semiconductor chip 61, thermal buffer plates 62, 6
3 is assembled between the press contact electrode plates 66 and 67 in a state separated from each other, and therefore, there is a possibility that a displacement occurs in a state other than the pressurized state. To prevent this, Japanese Patent Application Laid-Open No. 8-88240 discloses a semiconductor chip 61 and a heat buffer plate 6.
2, 63 are housed in the positioning frame 68 and held. In this case, displacement is unlikely to occur, but is not sufficient as a measure for preventing displacement because the semiconductor chip 61 and the thermal buffer plates 62 and 63 are not tightly fixed.

In order to correct the variation in the thickness of the constituent members such as the semiconductor chip 61, if the pressure is applied once, the Ag foils of the thickness correction plates 64 and 65 are reduced, and then the pressure is applied again, this positional deviation may occur. If so, it is difficult to adjust the thickness after re-pressing. To solve these inconveniences, Japanese Patent Application Laid-Open
There is a structure (FIG. 4) disclosed in Japanese Patent Publication No. -026421. In this flat type semiconductor device, the semiconductor chip 61 and the lower thermal buffer plate 62 are fixed with solder 69 so that the solder 69 performs positioning and thickness adjustment.

However, the solder 69 disclosed in Japanese Unexamined Patent Publication No. Hei 7-026421 uses lead (Pb 90.0 to 98.0).
Wt%) and tin (Sn 10.0 to 2.0 wt%), so if joined at a temperature higher than the solidus temperature, the solder 69 will be compressed too much, making it difficult to adjust the thickness. At a temperature lower than the solidus temperature, the thickness can be easily adjusted, but the bondability is deteriorated. Therefore, in this method, it is difficult to accurately adjust the thickness while securing the bonding strength between the semiconductor chip 61 and the thermal buffer plate 62.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to assemble components such as a semiconductor chip and a heat buffer plate by sandwiching them between press-contact electrodes. It is another object of the present invention to provide a flat type semiconductor device capable of stably adjusting the thickness of a constituent member without causing displacement of a built-in constituent member.

[0008]

In order to achieve the above-mentioned object, a plurality of semiconductor chips arranged on the same plane are provided.
For each of the semiconductor chips, a heat buffer plate provided on both main surfaces thereof, two press-contacting electrode plates sandwiching these, and interposed between the semiconductor chip and the heat buffer plate to fix them together. A flat semiconductor device having a solder for thickness adjustment, wherein the solder has a plurality of solder plates having different solidus temperatures.

It is preferable that the solder has a structure in which a solder plate having a high solidus temperature is sandwiched by a solder plate having a low solidus temperature. Further, it is preferable that the solder has a three-layer structure in which a first solder plate and a second solder plate sandwich a third solder plate having a higher solidus temperature than the first and second solder plates. The first solder plate and the second solder plate may be composed of 90.0% by weight of tin (Sn) and 10.0% by weight of silver (Ag) to 98.0% by weight of tin (Sn).
% By weight and 2.0% by weight of silver (Ag).

Further, the first solder plate and the second solder plate may include:
It is effective if the content is in the range of 95.0% by weight of tin (Sn) and 5.0% by weight of silver (Ag) to 98.0% by weight of tin (Sn) and 2.0% by weight of silver (Ag). Further, the third solder plate is
From 90.0% by weight of tin (Sn) and 10% by weight of antimony (Sb), 98.0% by weight of tin (Sn) and
b) It is preferably in the range of 2.0% by weight.

Further, the third solder plate is made of tin (Sn) 9
It is effective to be in the range of 0.0% by weight and 10% by weight of antimony (Sb) to 95.0% by weight of tin (Sn) and 5.0% by weight of antimony (Sb). Also, a plurality of semiconductor chips arranged on the same plane, and for each of the semiconductor chips,
A heat buffer plate provided on at least one main surface thereof,
In the method of manufacturing a flat semiconductor device joined by solder interposed between the semiconductor chip and the thermal buffer, a plurality of solder plates having different solidus temperatures from the semiconductor chip and a thermal buffer are provided on the same plane. A step of melting a solder having a low solidus temperature at a predetermined first temperature while applying pressure from above and below, and a step of applying a pressure higher than the first temperature while pressing vertically. By adjusting the individual thickness of the solder plate having a lower solidus temperature than the solidus temperature and a higher solidus temperature than the solidus temperature at the second temperature, the solder chip and the solder plate and the thermal buffer plate were combined. The manufacturing method includes a step of adjusting the thickness.

A plurality of semiconductor chips arranged on the same plane, a thermal buffer plate provided for each of the semiconductor chips so as to be superimposed on both main surfaces thereof, and two press-contacting electrode plates sandwiching these; In a method of manufacturing a flat semiconductor device having a thickness adjusting solder interposed between the semiconductor chip and the heat buffer plate and fixing the both, the first solder having a low solidus temperature is provided on the semiconductor chip. A third solder plate having a high solidus temperature on the first solder plate, a second solder plate having a low solidus temperature on the third solder plate, and the thermal buffer plate on the second solder plate. Sequentially laminating each of the first, second, and third solder plates; raising the three-layer solder plate to the low solidus temperature; The semiconductor chip and the three-layer solder plate and the three-layer solder plate are heated while being pressurized with a pressing force to a high solidus temperature. Fine the thermal buffer plate to adjust the total thickness of the combined, and the process to align each semiconductor chip, the 3
Cooling the layer solder plate and fixing the semiconductor chip and the thermal buffer plate.

[0013]

FIG. 1 is a structural view of a flat type semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) is a sectional view of an essential part, and FIG. 1 (b) is a sectional view of FIG. FIG. IG
On the upper and lower sides of a semiconductor chip 1 such as a BT chip or a freewheel diode chip, three layers of solder plates 6 and 7 each serving as a thickness adjusting plate are arranged.
The heat buffer plates 2 and 3 and the semiconductor chip 1 are fixed via the intermediary 7 and sandwiched between the press contact electrode plate 4 as the collector electrode plate and the press contact electrode plate 5 as the emitter electrode plate.

The three-layer solder plates 6 and 7 are melted and solidified while applying pressure, so that the semiconductor chip 1 and the thermal buffer plates 2 and 3 are fixed, and at the same time, the thickness of the semiconductor chip 1 and the thermal buffer plates 2 and 3 is increased. If there is a variation in the thickness, the thickness is adjusted so that the semiconductor chip 1 and the three-layer solder plates 6 and 7 and the thermal buffer plates 2 and 3 have the same overall thickness. A uniform pressure is applied to the plurality of semiconductor chips 1.

The three-layer solder plates 6 and 7 include first solder plates 6 a and 7 a having a low solidus temperature in contact with the semiconductor chip 1, and
Second solder plate 6 having a low solidus temperature in contact with thermal buffer plates 2 and 3
b, 7b, first solder plates 6a, 6b and second solder plate 7a,
7b, the third solder plates 6c and 7 having a high solidus temperature
c. The temperature of the three-layer solder plates 6 and 7 is increased while pressurizing them via the pressure-contact electrode plates 4 and 5 to increase the temperature of the semiconductor chip 1.
And the three-layer solder plates 6 and 7 and the thermal buffer plates 2 and 3 are combined. Is fixed.

The first solder plates 6a, 7a and the second solder plates 6b, 7b are composed of 96.5% by weight of tin (Sn) and silver (A).
g) 3.5% by weight and thickness of about 0.05 mm;
The solder plates 6c and 7c are 91.5% by weight of tin (Sn), 8.5% by weight of antimony (Sb), and about 0.1 mm in thickness. The first solder plates 6a, 7a and the second solder plate 6b,
In FIG. 7b, when the amount of silver (Ag) increases with respect to the amount of tin (Sn), the bonding strength of the solder increases. The joining strength is reduced. On the other hand, if it decreases too much, the bonding strength of the solder will decrease. Therefore, the first solder plates 6a, 7a and the second solder plates 6b, 7b are made of tin (Sn) 9
From 0.0% by weight and 10.0% by weight of silver (Ag) to tin (S
n) It is good to be in the range of 98.0% by weight and 2.0% by weight of silver (Ag). More preferably, tin (Sn) is 95.0% by weight and silver (Ag) is 5.0% by weight to tin (Sn) 98.0%.
% By weight and 2.0% by weight of silver (Ag).

In the third solder plates 6c and 7c, when the amount of antimony (Sb) is increased with respect to the amount of tin (Sn), the solidus temperature rises, and the first and second solder plates are increased. 6
The solidus temperatures of a, 6b, 7a, and 7b are preferably different from each other, but if they are excessively increased, they become hard and brittle. on the other hand,
If the temperature decreases too much, the solidus temperature decreases, and the solidus temperature of the first and second solder plates 6a, 6b, 7a, and 7b becomes indistinguishable. Therefore, the third solder plates 6c and 7c are made of tin (Sn).
The range is preferably 90.0% by weight and 10% by weight of antimony (Sb) to 98.0% by weight of tin (Sn) and 2.0% by weight of antimony (Sb). Further, preferably, tin (S
n) 90.0% by weight and 10% by weight of antimony (Sb) to 95.0% by weight of tin (Sn) and 5% by weight of antimony (Sb).
It is good to be in the range of 0% by weight.

As described above, the three-layer solder plates 6 and 7 are replaced with tin and silver-based first and second solder plates 6a and 6 having a low solidus temperature.
b, 7a, and 7a, and tin and antimony-based third solder plates 6c and 7c having a high solidus temperature, and first, tin and silver-based first and second solder plates 6a having a low solidus temperature. , 6b, 7a, 7
a, the semiconductor chip 1 and the third solder plates 6c and 7c and the thermal buffer plates 2 and 3 and the third solder plates 6c and 7c are joined, and then the temperature is increased to melt the third solder plates 6c and 7c. By solidifying, the overall thicknesses of the semiconductor chip 1, the three-layer solder plates 6, 7 and the thermal buffer plates 2, 3 can be made uniform. With the uniform thickness, a uniform pressing force can be applied to all the semiconductor chips 1 housed in a package (not shown). The third solder plates 6c and 7c have a central function of adjusting the thickness.

In the above description, the heat buffer plate 3 and the semiconductor chip 1 arranged above are also fixed by the three-layer solder plate 7,
Here, a thickness adjusting plate made of Ag or the like may be used without being fixed. Also, lead (P) is added to the three-layer solder plates 6 and 7.
Since b) is not included, the problem of environmental pollution does not occur.

2A to 2C show a method of manufacturing the flat semiconductor device of FIG. 1. FIGS. 2A to 2C are cross-sectional views of a main part manufacturing process shown in the order of processes. In FIG. 2A, a thermal buffer plate 2 is disposed on a lower pressure contact electrode plate 4, a second solder plate 6a having a low solidus temperature is disposed on the thermal buffer plate 2, and a second solder plate is provided. A third solder plate 6c having a high solidus temperature is disposed on the second solder plate 6a, and a first solder plate 6c having a low solidus temperature is provided on the third solder plate 6c.
The solder plate 6b is arranged, and the semiconductor chip 1 is arranged on the first solder plate 6b. The first and second solder plates 6a and 6b are 96.5% by weight of tin (Sn) and 3.5% by weight of silver (Ag) and have a thickness of about 0.05 mm, and the third solder plate 6c is formed of tin (Sn).
n) 91.5% by weight, 8.5% by weight of antimony (Sb) and about 0.1 mm in thickness.

In FIG. 1B, a first solder plate 7a is disposed on the semiconductor chip 1, and a third solder plate 7a is provided on the first solder plate 7a.
A solder plate 7c is disposed, a second solder plate 7b is disposed on the third solder plate 7c, a thermal buffer plate 3 is disposed on the second solder plate 7b, and an upper pressure contact electrode plate 5 is disposed thereon. Deploy. In FIG. 3C, a pressing force of 5 to 10 N is applied to each semiconductor chip from the upper and lower press contact electrode plates 4 and 5 to reach 225.
° C, and the first and second solder plates 6a, 6b, 7a, 7b
And the third solder plates 6c, 7c and the semiconductor chip 1,
The third solder plates 6c and 7c are fixed to the heat buffer plates 2 and 3, respectively. Then, the pressing force is increased to 20 to 40N, the heating temperature is set to 234 ° C, and then the cooling is performed while applying the pressure as it is. Then, the entire thickness of the semiconductor chip 1, the three-layer solder plates 6, 7 and the thermal buffer plates 2, 3 is made uniform for each semiconductor chip. The entire thickness adjustment is performed at a third temperature higher than the solidus temperature.
The solder plates 6c and 7c are the same as their solidus temperatures or
It is desirable to adjust the pressure at a temperature lower by a few degrees.

It is preferable to apply pressure at the time of heating at 225 ° C. and at the time of cooling. The first and second solder plates 6a, 6b, 7a, 7b fix the semiconductor chip 1 to the thermal buffer plates 2, 3, and the thickness is adjusted by the third solder plates 6c, 7c to melt the solder. Temperature can be selected widely, and productivity is improved. Further, by fixing the semiconductor chip 1 and the thermal buffer plates 2 and 3, a positioning frame for fixing the positions of the semiconductor chip 1 and the thermal buffer plates 2 and 3 becomes unnecessary, and the manufacturing cost can be reduced.

[0023]

According to the present invention, by using a three-layer solder plate which serves to adjust the thickness between a semiconductor chip and a heat buffer plate which are sandwiched between press-contact electrode plates and constitute a flat semiconductor device, The thickness variation of the semiconductor chip and the thermal buffer plate can be easily adjusted, and the semiconductor chip and the thermal buffer plate can be fixed. Due to this fixation, the semiconductor chip and the heat buffer plate are integrated, so that even when pressure is removed, the semiconductor chip and the heat buffer plate do not separate from each other and cause a position shift, thereby stabilizing the thickness adjustment. You can let me. Furthermore, even if there is a strong shock due to the semiconductor chip and the thermal buffer plate being fixed,
The displacement between the semiconductor chip and the heat buffer plate can be prevented. Further, a positioning frame for fixing the positions of the semiconductor chip and the heat buffer plate is not required, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIGS. 1A and 1B are configuration diagrams of a flat type semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a sectional view of a main part, and FIG.

FIGS. 2A to 2C are cross-sectional views of a main part manufacturing process shown in the order of processes, showing a method of manufacturing the flat semiconductor device according to the first embodiment;

FIG. 3 is a sectional view of a main part of a conventional flat semiconductor device.

FIG. 4 is a sectional view of a main part of another conventional flat semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2, 3 Thermal buffer plate 4, 5 Pressure contact electrode plate 6, 7 Three-layer solder plate 6a, 7a First solder plate 6b, 7b Second solder plate 6c, 7c Third solder plate

Claims (9)

[Claims] 1. A plurality of semiconductor chips arranged on the same plane, a heat buffer plate provided for each of the semiconductor chips so as to be overlapped on both main surfaces thereof, and two press-contact electrode plates sandwiching these.
A flat semiconductor device having a thickness adjusting solder that is interposed between the semiconductor chip and the thermal buffer plate and fixes the two, wherein the solder has a plurality of solder plates having different solidus temperatures. A flat semiconductor device characterized by having: 2. The method according to claim 1, wherein the solder is a solder plate having a high solidus temperature.
2. The flat semiconductor device according to claim 1, wherein the flat semiconductor device has a structure sandwiched between solder plates having a low solidus temperature. 3. A structure in which the solder comprises three layers, and a first solder plate and a second solder plate sandwich a third solder plate having a higher solidus temperature than the first and second solder plates. 3. The flat semiconductor device according to claim 2, wherein: 4. The method according to claim 1, wherein the first solder plate and the second solder plate are composed of 90.0% by weight of tin (Sn) and 10.0% by weight of silver (Ag) to 98.0% by weight of tin (Sn) and 3. The flat semiconductor device according to claim 2, wherein Ag is in a range of 2.0% by weight. 5. The method according to claim 1, wherein the first solder plate and the second solder plate are composed of 95.0% by weight of tin (Sn) and 5.0% by weight of silver (Ag) to 98.0% by weight of tin (Sn) and 4. The flat semiconductor device according to claim 3, wherein Ag is in a range of 2.0% by weight. 6. The method according to claim 1, wherein the second solder plate comprises tin (Sn) 90.0% by weight and antimony (Sb) 10% by weight and tin (Sn) 9
3. The flat semiconductor device according to claim 2, wherein the content is in a range of 8.0% by weight and 2.0% by weight of antimony (Sb). 7. The method according to claim 7, wherein the second solder plate comprises tin (Sn) 90.0% by weight and antimony (Sb) 10% by weight and tin (Sn) 9
3. The flat semiconductor device according to claim 2, wherein the content is in a range of 5.0% by weight and 5.0% by weight of antimony (Sb). 8. A plurality of semiconductor chips arranged on the same plane, a heat buffer plate provided for each of the semiconductor chips so as to overlap at least one main surface thereof, the semiconductor chip and the heat buffer plate. In a method of manufacturing a flat type semiconductor device joined by solder interposed therebetween, a step of arranging a plurality of semiconductor chips, a plurality of solder plates having different solidus temperatures and a thermal buffer plate on the same plane. Melting a solder having a low solidus temperature at a predetermined first temperature while applying pressure from above and below, and setting the solidification to a predetermined second temperature higher than the first temperature while applying upward and downward pressure. By adjusting the individual thickness of the solder plate having a higher solidus wire solid phase solder than the phase line temperature, it is possible to include a step of adjusting the thickness of the solder chip and the solder plate and the thermal buffer plate together. Manufacture of flat type semiconductor devices Method. 9. A plurality of semiconductor chips arranged on the same plane, a heat buffer plate provided for each of the semiconductor chips so as to be superposed on both main surfaces thereof, and two press-contacting electrode plates sandwiching them.
In a method of manufacturing a flat semiconductor device having a thickness adjusting solder interposed between the semiconductor chip and the heat buffer plate and fixing the both, the first solder having a low solidus temperature is provided on the semiconductor chip. A third solder plate having a high solidus temperature on the first solder plate, a second solder plate having a low solidus temperature on the third solder plate, and the thermal buffer plate on the second solder plate. Sequentially laminating each of the first, second, and third solder plates; raising the three-layer solder plate to the low solidus temperature; Raising the temperature to a high solidus temperature while pressing with a pressing force, adjusting the overall thickness of the semiconductor chip and the three-layer solder plate and the thermal buffer plate together, and aligning the semiconductor chips with each other; Cooling the three-layer solder plate and fixing the semiconductor chip and the thermal buffer plate. Method of manufacturing a flat type semiconductor device according to claim and.