JP2002176084A - Equipment and method for inspecting semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an equipment and a method for inspecting a semiconductor with high accuracy and efficiency. SOLUTION: The substrate stage 28 of an EB inspection equipment 1 is sequentially applied with a plurality of DC voltages having different voltage levels from a variable DC power supply 42. The same area of a semiconductor substrate S is scanned with a charge beam 32 for each DC voltage being applied to a substrate and a signal having an intensity dependent on the surface potential of a semiconductor substrate S is acquired through a secondary electron detector 44. Intensity difference between different DC voltages applied to the substrate is then calculated for the signals thus acquired and a decision is made that a part corresponding to a signal having a large intensity difference is acceptable and a part corresponding to a signal having a small intensity difference is rejectable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate inspection apparatus and a semiconductor substrate inspection method, and more particularly, to an inspection method for inspecting electrical conduction failure generated in a contact hole or a via hole of a wiring formed on a surface of a semiconductor substrate. It is.

[0002]

2. Description of the Related Art Conventionally, an image comparison inspection method has been used for a defect inspection for a contact hole or a via hole of a wiring formed during the manufacture of a semiconductor integrated circuit device. In this method, a potential contrast image of a surface of a wiring existing on a specific chip in a wafer plane is obtained, and a potential contrast image of a region where wirings having the same layout are formed in cells or dies adjacent to each other is obtained. This is a method of comparing the two with each other and detecting a defect having a different contrast (gradation value of a pixel) as a defect. Such an inspection method is described in, for example, Japanese Society for the Promotion of Science
LSI Testing Symposium / 1998 "Development of Wafer Process Failure Analysis Method Using Potential Contrast Image P160-165". Generally, such a defect inspection method is called a cell-to-cell image comparison inspection method or a die-to-die image comparison inspection method, and uses an electron beam represented by a product of KLA-Tncor. The used defect inspection apparatus also uses this method. The cell-to-cell image comparison inspection method is used, for example, when inspecting a die A1 having a repetitive wiring such as a memory device as shown in FIG. In the example shown in the figure, for example, the cells C1 and C2 are compared with each other, and the cell C2 is detected as a defective portion. Also, the die-to-die image comparison inspection method is, for example, shown in FIG.
As shown in FIG. 2, it is used to inspect dies B1 and B2 having no repetitive wiring such as a logic device. In the example shown in the figure, is compared with the potential contrast image G _B1 and G _B2, is P3 in the potential contrast image G _B2 is detected as a defective portion.

[0003]

However, in the above-described defect inspection method, the movement from the position coordinates of a certain cell or die to the position coordinates of an adjacent cell or die of the same layout requires the semiconductor substrate to be moved in the defect inspection apparatus. This is performed by mechanically operating the holding substrate stage. Therefore, when comparing two or more inspection images,
Since a difference in signal strength between images to be compared occurs due to a positional shift, vibration, focus shift, charging state, and the like of the substrate stage, a false defect is detected. As a result, accuracy and efficiency of the inspection are reduced. Had the drawback that

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor substrate inspection apparatus and a semiconductor substrate inspection method which are excellent in inspection accuracy and inspection efficiency.

[0005]

The present invention solves the above problems by the following means.

That is, according to the present invention, a plurality of DC voltages having different voltage values are sequentially applied to a semiconductor substrate to be inspected to sequentially form inspection conditions having different DC voltages applied to the substrate. Scanning the same region of the semiconductor substrate with a charged beam for each inspection condition, secondary charged particles or reflected charged particles generated from the surface of the semiconductor substrate by scanning of the charged beam or the secondary charged particles and the Detecting the reflected charged particles and obtaining a signal having an intensity dependent on the surface potential of the semiconductor substrate for each of the inspection conditions; and a defect in the semiconductor substrate based on a difference in the intensity of the signal between the inspection conditions. Detecting the semiconductor substrate.

According to the method of inspecting a semiconductor substrate according to the present invention, a plurality of DC voltages are sequentially applied to the semiconductor substrate to form inspection conditions having different DC voltages applied to the substrate. Obtain a signal having an intensity dependent on the surface potential, and detect a defect in the semiconductor substrate based on the difference in the intensity of the signal between the inspection conditions, without moving the substrate stage holding the semiconductor substrate Thus, a defect of the semiconductor substrate can be detected. As a result, it is possible to eliminate the influence of noise due to the positional shift, vibration, focus shift, charging state, and the like of the substrate stage. As a result, it is possible to realize a board inspection excellent in both accuracy and efficiency.

[0008] The step of detecting the defect includes the step of forming a potential contrast image, which is an image having a contrast distribution corresponding to the surface potential distribution of the semiconductor substrate, based on the signal, for each of the inspection conditions. Calculating a tone value of a pixel forming a contrast image as the intensity of the signal. Thereby, the intensity difference between the signals can be calculated quantitatively, so that the inspection accuracy can be improved.

The step of detecting a defect may include a step of determining that a defect exists in the semiconductor substrate when a difference in the signal intensity between different inspection conditions is equal to or less than a predetermined threshold value. . Thus, the presence or absence of a defect can be detected with high efficiency. The above threshold is
It can be set individually based on process conditions and design specifications.

[0010] The step of detecting the defect includes the step of creating a histogram of the frequency of appearance of the signal intensity at the same location between the inspection conditions based on the potential contrast image; The frequency of occurrence of the signal intensity of the same portion obtained between the inspection conditions when the inspection condition is satisfied is plotted in the histogram as a defect determination level, and among the histogram regions divided by the defect determination level, the signal intensity is A step of specifying a larger area as a defect determination area, and when there is the signal strength included in the defect determination area,
Determining that the semiconductor substrate has a defect.

Preferably, the step of detecting the defect includes a step of outputting position coordinates of a region on the surface of the semiconductor substrate corresponding to the signal intensity included in the defect determination region as defect location information. Thereby, a defective portion can be easily specified.

In the step of detecting the defect, the information of the wiring resistance value in the surface region of the semiconductor substrate corresponding to the signal intensity is output based on a relationship between the signal strength and the wiring resistance value prepared in advance. It is even better to include the step of performing As a result, the degree of the defect can be determined, so that it is easy to take measures to remedy the defect in the subsequent manufacturing process according to the required specifications.

Further, according to the present invention, a charged beam emitting means for generating a charged beam and irradiating the semiconductor substrate to be inspected with the charged beam, a beam deflection scanning means for deflecting and scanning the charged beam, Detects secondary charged particles or reflected charged particles generated from the semiconductor substrate by irradiation of a charged beam, or the secondary charged particles and the reflected charged particles, and outputs a signal having an intensity depending on a surface potential of the semiconductor substrate. Secondary charged particle detecting means, and controlling the inspection conditions so that a plurality of DC voltages having different voltage values are sequentially applied to the semiconductor substrate, and wherein the charged beam is the same as that of the semiconductor substrate for each of the inspection conditions. Control means for controlling the beam deflection scanning means so as to scan the area, and from the secondary charged particle detection means for each of the inspection conditions. And processing the signal output,
There is provided a semiconductor substrate inspection apparatus comprising: a determination unit that calculates the intensity of the signal and outputs information on a defect in the semiconductor substrate based on a difference in the intensity of the signal between the inspection conditions.

According to the semiconductor substrate inspection apparatus of the present invention, the inspection apparatus includes the control means and the determination means, acquires a signal having an intensity dependent on the surface potential of the semiconductor substrate for each of the inspection conditions, and Since information on the defect in the semiconductor substrate is output based on the difference in the signal intensity between the conditions, the defect in the semiconductor substrate can be detected without moving the substrate stage holding the semiconductor substrate. As a result, it is possible to eliminate the influence of noise due to the positional shift, vibration, focus shift, charging state, and the like of the substrate stage. As a result, it is possible to realize a board inspection excellent in both accuracy and efficiency.

Further, the determining means forms a potential contrast image, which is an image having a contrast distribution corresponding to a surface potential distribution of the semiconductor substrate, based on the signal, for each of the inspection conditions, and forms the potential contrast image. It is preferable to calculate the tone value of the constituent pixels as the intensity of the signal.

In the semiconductor substrate inspection apparatus, the determining means may determine that the semiconductor substrate has a defect when a difference between the signal intensities between the different inspection conditions is equal to or less than a predetermined threshold value. Is desirable.

Further, the determination means creates a histogram of the frequency of appearance of the signal intensity at the same location between the inspection conditions based on the potential contrast image, and when the semiconductor substrate satisfies the minimum required specification, The frequency of occurrence of the signal intensity of the same portion obtained between the inspection conditions is plotted in the histogram as a defect determination level as a defect determination level. It is preferable that the semiconductor substrate is specified as a determination area, and when the signal strength included in the defect determination area is present, it is determined that a defect exists in the semiconductor substrate.

[0018] It is preferable that the determination means outputs information on position coordinates of a region on the semiconductor substrate surface corresponding to the signal intensity included in the defect determination region as information on the defect.

[0019] Further, based on a relationship between the signal strength and the wiring resistance value, the determining means may use information on the wiring resistance value in the surface region of the semiconductor substrate corresponding to the signal strength as information on the defect. It is more preferable to output.

In the above-described semiconductor substrate inspection method or semiconductor substrate inspection apparatus according to the present invention, the plurality of DC voltages include positive and negative voltages.

In a preferred embodiment of the present invention, the plurality of DC voltages are two DC voltages having the same absolute value and different polarities, and the voltage is used to determine an arbitrary point in a two-dimensional histogram. A plurality of straight lines or circular arcs having a predetermined angle with respect to each other as reference points, and the defect determination area is an area divided by the plurality of straight lines or curves and having a higher signal strength. It is. Alternatively, a circle having a predetermined radius around the reference point may be drawn in the two-dimensional histogram, and the inside of the circle may be used as a defect determination area.

The above-mentioned defect includes a defect that causes a poor electrical conduction in the wiring of the semiconductor substrate.

Further, the defect includes a defective formation of a contact hole or a via hole in the semiconductor substrate.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the basic principle of a semiconductor substrate inspection method according to the present invention will be described.

When the surface of the semiconductor substrate is irradiated with a charged beam, secondary charged particles, reflected charged particles and backscattered charged particles (hereinafter referred to as secondary charged particles) are generated and emitted from the substrate surface. The energy amount at the time of emission of these secondary charged particles and the like depends on the potential of the substrate surface when the acceleration voltage and beam current of the charged beam are the same. Further, the surface potential of the substrate greatly depends on the material and structure of the substrate surface in addition to the voltage applied to the substrate. For example, if a contact hole or via hole for wiring is formed in an insulating film formed on a silicon substrate and a negative voltage is applied to the substrate,
If these wiring contacts / via holes are formed satisfactorily, the emission energy of secondary charged particles and the like increases. When a positive voltage of the opposite polarity is applied to the same silicon substrate, if these holes are formed well, the emission energy of secondary charged particles and the like will be small. On the other hand, if the wiring contact / via hole is not formed well and an insulating layer is formed between the conductor filling the hole and the silicon substrate due to some process problem, for example, Even when a voltage is applied to the substrate, the emission energy of secondary charged particles and the like does not change much. This will be described more specifically with reference to FIGS.

The schematic cross-sectional views shown in FIGS. 1A and 2A show that, after an insulating film 92 is formed on a P-type silicon substrate 90, a contact hole is formed in the insulating film 92. This is an example of a portion in which a metal material is embedded in a hole to form a wiring portion 94 (hereinafter, referred to as a non-defective portion Sa). In the example shown in both figures, the contact hole is formed well,
The wiring portion 94 is in direct contact with and electrically connected to the silicon substrate 90. Its resistance was 10Ω or less.

FIG. 1A shows an example in which a direct current voltage DC = -20 V is applied to the P-type silicon substrate 90 and the electron beam 32 is scanned around the non-defective part Sa. As shown in the figure, secondary electrons, reflected electrons, and backscattered electrons (hereinafter, referred to as secondary electrons) 34 enter the secondary electron detector 44 with a large emission energy from the surface of the substrate.

FIG. 1B shows a potential contrast image _GP-20 obtained from the signal output from the secondary electron detector 44 shown in FIG. 1A. In the figure, a portion I indicated by a circle
m94 is an image corresponding to the wiring section 94, and has an extremely high luminance according to the magnitude of the signal intensity.
The measured signal intensity was 203 gradations.

FIG. 2 (a) shows an example in which the electron beam 32 is scanned at a non-defective part Sa similar to that shown in FIG. 1 (a) while changing the substrate applied voltage to DC = + 20V. As shown in the figure, secondary electrons and the like generated on the surface of the wiring portion 94 flow to GND via the silicon substrate 90 and the variable DC power supply 42, so that the emission energy of the secondary electrons and the like is extremely small.

FIG. 2B shows a potential contrast image _{GP + 20} obtained from the signal output from the secondary electron detector 44 shown in FIG. 2A. In the figure, an image portion Im94 indicated by a circle is an image having extremely low luminance according to the magnitude of the signal intensity. When the signal strength is measured, it is 15
It was gradation.

In the schematic cross-sectional views shown in FIGS. 3A and 4A, after an insulating film 92 is formed on a P-type silicon substrate 90, a contact hole is formed in the insulating film 92. This is an example of a place where a contact hole is not formed well and a metal material is buried on the insulating film 96 to become the wiring part 95 (hereinafter referred to as a defective place Sd). In the example shown in FIGS.
, And was electrically insulated from its resistance value was 10 ⁴ Ω or more.

FIG. 3A shows an example in which a DC voltage DC = -20 V is applied to the P-type silicon substrate 90 and the electron beam 32 is scanned around the defective portion Sd. FIG. 3 (b)
Shows a potential contrast image _Gd-20 obtained from the signal output from the secondary electron detector 44 shown in FIG. In the figure, a portion Im95 indicated by a circle is an image corresponding to the wiring portion 95, and has an intermediate luminance according to the magnitude of the signal intensity. The measured signal intensity was 123 tones.

FIG. 4A shows an example in which the electron beam 32 is scanned with respect to the same defective portion Sd as in FIG. 3A by changing the substrate applied voltage to DC = + 20 V. FIG.
4B shows a potential contrast image G obtained from the signal output from the secondary electron detector 44 shown in FIG.
Indicates _{d + 20} . In the figure, an image portion Im95 indicated by a circle
Is an image having an intermediate luminance almost in the same manner as the image in FIG. 3B. When the signal strength is measured, it is 1
There were 41 tones.

Therefore, from the above, regarding the wiring portion at the same coordinate position of the same die, if the wiring portion 94 of the non-defective part Sa, two potential contrasts obtained by inverting the DC voltage applied to the substrate in the positive and negative directions are obtained. Images _GP-20 , G
The difference in signal strength between _{P + 20} is 188 (203-15)
It can be seen that the gradation is very large. The other hand, the wiring portion 95 of the defective portion Sd in the same coordinate position of the same die, the two which were obtained by a substrate applied DC voltage is positive and negative reversal between the potential contrast image _{G d-20, G d +} 2 0 It can be seen that the difference in signal strength is as small as 18 (141-123) gradations.

FIG. 5 shows that the DC voltage (V) applied to the substrate is -20.
7 is a graph showing a relationship between a DC voltage applied to a substrate (V) and a signal intensity (gradation value) of a potential contrast image on a wiring surface when the voltage is changed from V to +20 V. As shown in the figure, the difference between the signal intensity when the substrate applied DC voltage is negative and the signal intensity when the substrate applied DC voltage is positive is very large at 188 gradations for non-defective parts, whereas for the defective parts, It can be seen that the gradation is very small at 18 gradations.

According to the present invention, a plurality of voltages having different voltage values are sequentially applied to a substrate to be inspected by utilizing such a difference in signal strength, and a gradation of a signal obtained for each substrate applied voltage is obtained. By comparing the values with each other, it is possible to detect a defective product without mechanically operating the substrate stage.

Hereinafter, some embodiments of the present invention will be described with reference to the drawings.

FIG. 6 is a block diagram showing an embodiment of the board inspection apparatus according to the present invention. The substrate inspection apparatus 1 of the present embodiment includes an electron beam column 10, a variable DC power supply 42, a secondary electron detector 44, a signal processing device 46,
It includes a deflector controller 48, a control computer 52, a display device (CRT) 54, and a memory 56.

The electron beam column 10 includes an electron gun 12 and
Condenser lens 14 and Wien-fil
ter) 16, an objective lens 18, a beam scanning deflector 22, a column stage 24, an electrode 26, and a substrate stage 28. On the substrate stage 28, a semiconductor substrate S on which wiring including a non-defective part Sa shown in FIGS. 1 and 2 and a defective part Sd shown in FIGS. 3 and 4 is formed is held upside down.

The electron beam 32 emitted from the electron gun 12
Are focused by the condenser lens 14 and enter the Wien filter 16. The Wien filter 16 causes the incident electron beam 32 to travel straight without being deflected and to enter the objective lens 18. The objective lens 18 focuses the electron beam 32 so as to form an image on the surface of the substrate S. The focused electron beam 32 is deflected and scanned on the semiconductor substrate S by the beam scanning deflector 22 that receives a control signal from the polarizer controller 48. A positive / negative DC voltage is applied to the semiconductor substrate S from the variable DC power supply 42 via the substrate stage 28.

By scanning with the electron beam 32, secondary electrons 34 are emitted from the surface of the wiring formed on the semiconductor substrate S. The emitted secondary electrons and the like 34 are deflected by the Wien filter 16 after passing through the objective lens 18 while being accelerated by the electric field formed between the semiconductor substrate S and the objective lens 18, and are deflected by the secondary electron detector 44. Be drawn in. The secondary electron detector 44 detects the detected secondary electrons 34 and the like.
The signal processing device 46 converts the received signal into an image signal and outputs the signal to the control computer 52.
To supply. The control computer 52 includes the signal processing device 4
The processing described below is performed on the image signal received from 6, and a potential contrast image representing the state of the wiring surface of the semiconductor substrate S is displayed by the display device (CRT) 54.

The memory 56 includes a program describing an inspection recipe for executing the inspection method described below, and a data table (hereinafter referred to as a wiring resistance data table) representing the relationship between the signal strength of the potential contrast image and the wiring resistance. ) Is stored.

The control computer 52 constitutes control means and determination means in the present embodiment, controls the entire apparatus, reads a program of an inspection recipe from the memory 56, and executes each inspection procedure based on the program.

The operation of the board inspection apparatus 1 shown in FIG. 6 will be described as an embodiment of the board inspection method according to the present invention with reference to the drawings. In the following, for the sake of simplicity, DC = −20 V, DC = −2
A case where two DC voltages of 0 V are sequentially applied to the semiconductor substrate S will be described.

FIG. 7 is a flowchart showing the main operation of the board inspection apparatus 1. As shown in the figure, first, a semiconductor substrate S having a wiring to be inspected is placed on a substrate stage 28.
(Step S1). Here, it is assumed that the wiring to be inspected includes the non-defective part Sa (see FIGS. 1 and 2) and the defective part Sd (see FIGS. 3 and 4).

Next, the control computer 52 has the memory 5
6 is read, and the following processing is executed in accordance with the program.

That is, first, the substrate applied DC voltage DC = −2
A potential contrast image G1 of the wiring surface is obtained at 0 V (step S2).

FIG. 8 is a flowchart specifically showing the procedure of step S2. Control computer 52
Supplies a control signal to the variable DC power supply 42 and sets its DC voltage value to DC = -20V (step S21),
DC voltage DC to the semiconductor substrate S via the substrate stage 28
= -20V is applied (step S22). Next, under these inspection conditions, the electron gun 12, the control lenses 14, 18
Then, the beam scanning deflector 22 is operated to scan the surface of the substrate including the wiring portion to be inspected with the electron beam 32 (step S23). Next, secondary electrons and the like 34 generated and emitted from the surface of the substrate S are detected by the secondary electron detector 44, and a signal representing the detection result is supplied to the signal processing device 46. The signal processing device 46 converts the signal received from the secondary electron detector 44 into an image signal and supplies it to the control computer 52. The control computer 52 supplies the received image signal to the display device (CRT) 54, and the potential contrast image G1 is displayed (Step S24). The potential contrast image G1 includes the above-described image _{GP-20 of the non-} defective part Sa (see FIG. 1B) and the image _Gd-20 of the defective part Sd (see FIG. 3B). The control computer 52 binarizes the received image signal to calculate a gradation value, and stores the gradation value in the memory 56 in association with the coordinate value of the scanning area.

Returning to FIG. 7, when the DC voltage applied to the substrate is DC = +
Change to 20V, potential contrast image G2 on wiring surface
Is obtained (step S3). FIG. 9 illustrates this step S.
9 is a flowchart specifically showing a procedure 3; As shown in the figure, a control signal is supplied from the control computer 52 to the variable DC power supply 42, the setting is changed to DC = + 20 V (step S31), and the DC voltage is applied to the semiconductor substrate S via the substrate stage 28. = + 20 V is applied (step S32). Further, under these inspection conditions, the electron gun 1
2. Operate the control lenses 14 and 18 and the beam scanning deflector 22 to scan the surface of the substrate including the wiring portion to be inspected with the electron beam 32 (step S33). Further, secondary electrons or the like generated and emitted from the surface of the substrate S 34
Is detected by the secondary electron detector 44 and the potential contrast image G2 is obtained by signal processing by the signal processing device 46 (step S34). The potential contrast image G2 includes the above-described image _{GP + 20} of the non-defective part Sa (FIG. 2).
(B) and the image G _{d + 20} of the defective portion Sd (FIG. 4)
(B)). The control computer 52 binarizes the received image signal to calculate a gradation value, and stores the gradation value in the memory 56 in association with the coordinate value of the scanning area.

Returning to FIG. 7, the control computer 52 fetches the gradation value and coordinate value data obtained in steps S2 and S3 from the memory 56 and controls the signal intensity at the same location in the two potential contrast images G1 and G2. A two-dimensional histogram in which the histogram of the appearance frequency is expressed in a secondary space is created (step S4). FIG. 10 shows a specific example of the two-dimensional histogram obtained in this manner.

The two-dimensional histogram shown in FIG. 10 shows the gradation value 0 of the signal obtained at the substrate applied DC voltage DC = −20 V.
２５255 on the horizontal axis, DC voltage applied to the substrate DC = + 20 V
With the gradation values 0 to 255 of the signal obtained in the vertical axis as the vertical axis, the signal intensity of the potential contrast image G1 is located for each coordinate from the gray scale values of the horizontal axis of the two-dimensional histogram, and the position is perpendicular to the two-dimensional histogram. Draw a straight line. Further, the signal intensity of the potential contrast image G2 is located for each coordinate from the gradation value on the vertical axis of the two-dimensional histogram, and a straight line is drawn horizontally in the two-dimensional histogram from the position. Potential contrast images G1, G2
Are plotted as signal intensities for each coordinate. For non-defective parts, the applied DC voltage DC = −2
Since there is a large difference in signal strength between 0 V and DC = + 20 V, the distribution is concentrated and distributed in the upper right portion of the drawing (non-defective part group 82). On the other hand, for defective products, the difference in signal intensity between the DC voltage applied to the substrate DC = −20 V and DC = + 20 V is small, so that the defective products are concentrated and distributed from the center of FIG. (Defective part group 84).
In the potential contrast images G1 and G2, the gradation value of the region corresponding to the region of the insulating film 92 becomes 120 under any of the inspection conditions of the substrate applied DC voltage DC = −20V and DC = + 20V. And the difference is small,
It is concentrated and distributed in the area 86 in the upper left part of the drawing.

Returning to FIG. 7, a defect determination area serving as a reference for defect determination is set and input to the control computer 52 by input means (not shown) (step S5). The defect determination areas are individually set based on process conditions, design specifications, and the like. In the present embodiment, as shown in FIG.
The gradation value 120 at == − 20 V and the gradation value 120 at DC = + 20 V are designated as reference points, and straight lines 11 and 12 (defect determination levels) forming arbitrary angles with respect to each other are drawn from these reference points. Among the areas divided by l1 and l2, the area with the higher signal strength is set as the defect determination area. The defect determination level is a straight line in the present embodiment, but is not limited to this, and may be, for example, an arc-shaped curve. Alternatively, a circle having a predetermined radius around the above-described reference point may be drawn in the two-dimensional histogram, and the inside of the circle may be set as a defect determination area.

Next, as shown in FIG. 7, the control computer 52 determines the signal strength in the defect determination area as the defective portion group 84 based on the input threshold value, and further, the position coordinates of each defective portion. Are extracted from the memory 56, and the respective signal intensities are calculated (step S6).

Further, the control computer 52 outputs data of the wiring resistance value of each defective portion together with its position coordinates from the signal strength at each defective portion by collating with the wiring resistance data table stored in the memory 56 ( Step S7).

According to the present embodiment, two DC voltages having different polarities are sequentially applied to the semiconductor substrate, and signal intensities are calculated for two potential contrast images respectively obtained in the same region on the substrate surface. The presence / absence of a defect is determined based on the information, and if there is a defect, information on the position of the defect is output together with the degree of the defect. Therefore, a defect in the same wiring of the same die can be detected without moving the substrate stage. As a result, displacement of the substrate stage, vibration,
It is possible to eliminate the influence of noise due to focus shift, charging state, and the like. As a result, it is possible to realize a board inspection excellent in both accuracy and efficiency.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and can be applied with various modifications without departing from the scope of the invention. In the above embodiment, DC = −20 V and DC = + 20 V
Although the case where various types of DC voltages are applied to the substrate has been described, as is clear from the graph of FIG. 5, a large number of potential contrast images are obtained from the same region of the substrate by changing the substrate applied DC voltage value over a predetermined range. By doing so, of course, the accuracy of the inspection can be further improved.
Further, in the above-described embodiment, the case where the substrate on which the wiring layer is already formed is to be inspected, but for example, the contact hole or the via hole before the metal material is embedded is to be inspected, and the presence or absence of the defect and the position·
The degree can also be checked.

[0057]

As described in detail above, the present invention has the following effects.

That is, according to the present invention, a plurality of DC voltages are sequentially applied to the semiconductor substrate to sequentially form inspection conditions having different DC voltages applied to the substrate, and the surface potential of the semiconductor substrate is changed for each of these inspection conditions. A signal having a dependent intensity is obtained, and a defect in the semiconductor substrate is detected based on a difference in the signal intensity between the inspection conditions, so that the semiconductor stage is not moved without moving the substrate stage holding the semiconductor substrate. Defects in the substrate can be detected.
This eliminates the influence of noise due to the positional shift, vibration, focus shift, charging state, and the like of the substrate stage, thereby realizing a substrate inspection excellent in both accuracy and efficiency.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating the principle of a substrate inspection method according to the present invention.

FIG. 2 is a schematic diagram illustrating the principle of a substrate inspection method according to the present invention.

FIG. 3 is a schematic diagram illustrating the principle of the substrate inspection method according to the present invention.

FIG. 4 is a schematic diagram illustrating the principle of the substrate inspection method according to the present invention.

FIG. 5 is a graph showing a relationship between a substrate applied DC voltage (V) and a signal intensity (gradation value) of a potential contrast image on a wiring surface.

FIG. 6 is a block diagram showing one embodiment of a board inspection apparatus according to the present invention.

FIG. 7 is a flowchart showing a main flow of an embodiment of the board inspection method according to the present invention.

FIG. 8 is a flow chart shown in FIG.
9 is a flowchart specifically showing a procedure for acquiring a potential contrast image of a wiring surface at 0 V.

FIG. 9 is a flow chart of FIG. 7, in which the substrate applied voltage DC = + 2;
9 is a flowchart specifically showing a procedure for acquiring a potential contrast image of a wiring surface at 0 V.

FIG. 10 is a schematic diagram showing an example of a two-dimensional histogram obtained from two potential contrast images according to the flow shown in FIG. 7;

FIG. 11 is a schematic diagram illustrating a semiconductor substrate inspection method using a cell-to-cell image comparison inspection method according to a conventional technique.

FIG. 12 is a schematic diagram illustrating a semiconductor substrate inspection method using a conventional die-to-die image comparison inspection system.

[Explanation of symbols]

 Reference Signs List 1 substrate inspection apparatus 10 electron beam column 12 electron gun 14 condenser lens 16 Wien filter 18 objective lens 22 beam scanning deflector 24 column stage 26 electrode 28 substrate stage 32 electron beam 34 secondary electron, reflected electron and backscattered electron 42 variable DC power supply 44 Secondary electron detector 46 Signal processing device 48 Deflector controller 52 Control computer 54 Display device (CRT) 56 Memory S Semiconductor substrate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G01R 31/302 G01R 31/28 L 4M106 F-term (Reference) 2F067 AA45 AA54 AA62 BB01 BB04 CC17 EE03 HH06 JJ05 KK04 KK08 LL16 QQ02 RR04 RR24 RR30 RR36 RR42 SS02 SS13 2G001 AA03 BA07 BA14 BA15 CA03 EA04 FA06 GA01 GA06 GA09 HA01 HA13 JA02 JA03 JA11 JA13 KA03 LA11 MA05 2G011 AA01 AC03 AE01 AE03 2G014 AA02 A01 A02 A01 A02 A01 A02 CA38 DB05 DB12 DB30 DJ01 DJ11

Claims (18)

[Claims] A step of sequentially applying a plurality of DC voltages having different voltage values to a semiconductor substrate to be inspected to sequentially form inspection conditions having different DC voltages applied to the substrate; and a charged beam for each of the inspection conditions. Scanning the same region of the semiconductor substrate, and detecting the secondary charged particles or reflected charged particles or the secondary charged particles and the reflected charged particles generated from the surface of the semiconductor substrate by scanning the charged beam, Acquiring a signal having an intensity that depends on the surface potential of the semiconductor substrate for each of the inspection conditions; anddetecting a defect in the semiconductor substrate based on a difference in the intensity of the signal between the inspection conditions. Semiconductor substrate inspection method provided. 2. The method according to claim 1, further comprising: acquiring a potential contrast image having a contrast distribution corresponding to a surface potential distribution of the semiconductor substrate based on the signal for each of the inspection conditions. 2. The semiconductor substrate inspection method according to claim 1, further comprising: calculating a tone value of a pixel forming the potential contrast image as the intensity of the signal. 3. The step of detecting a defect includes a step of determining that a defect exists in the semiconductor substrate when a difference in signal intensity between different inspection conditions is equal to or less than a predetermined threshold value. The semiconductor substrate inspection method according to claim 1 or 2, wherein: 4. The method according to claim 1, wherein the step of detecting the defect includes the step of creating a histogram of the frequency of occurrence of the signal intensity of the same portion between the inspection conditions based on the potential contrast image; The frequency of occurrence of the signal intensity at the same location obtained between the inspection conditions is plotted in the histogram as a defect determination level when the inspection condition is satisfied. A step of specifying a larger area as a defect determination area; and a step of determining that a defect exists in the semiconductor substrate when the signal intensity included in the defect determination area is present. 3. The semiconductor substrate inspection method according to 1 or 2. 5. The method according to claim 1, wherein the step of detecting the defect includes a step of outputting position coordinates of a region on the surface of the semiconductor substrate corresponding to the signal strength included in the defect determination region as information of a defect portion. The method for inspecting a semiconductor substrate according to claim 4. 6. The semiconductor device according to claim 1, wherein the step of detecting the defect includes the step of: detecting a defect on the surface area of the semiconductor substrate corresponding to the signal intensity included in the defect determination area based on a relationship between the signal intensity and a wiring resistance value prepared in advance. 6. The method according to claim 5, further comprising the step of outputting information on a wiring resistance value in the step (c). 7. The semiconductor substrate inspection method according to claim 1, wherein the plurality of DC voltages include a positive polarity voltage and a negative polarity voltage. 8. The semiconductor substrate inspection method according to claim 1, wherein the defect includes a defect that causes an electrical conduction failure in wiring of the semiconductor substrate. 9. The semiconductor substrate inspection method according to claim 1, wherein the defect includes a defective formation of a contact hole or a via hole in the semiconductor substrate. 10. A charged beam generating means for generating a charged beam and irradiating the semiconductor substrate to be inspected with the charged beam, a beam deflection scanning means for deflecting and scanning the charged beam, and irradiating the charged beam with the charged beam. Secondary charged particle or reflected charged particle generated from a semiconductor substrate, or secondary charged particle detection means for detecting the secondary charged particle and the reflected charged particle and outputting a signal having an intensity dependent on a surface potential of the semiconductor substrate And controlling inspection conditions so that a plurality of DC voltages having different voltage values are sequentially applied to the semiconductor substrate, and the charged beam is scanned over the same region of the semiconductor substrate for each of the different inspection conditions. Means for controlling the beam deflection scanning means as described above, and output from the secondary charged particle detection means for each of the inspection conditions. Processing the signal to calculate the strength of the signal;
A determining means for outputting information on a defect in the semiconductor substrate based on a difference in signal strength between the inspection conditions. 11. The determining means according to the signal,
Forming a potential contrast image, which is an image having a contrast distribution according to the surface potential distribution of the semiconductor substrate, for each of the inspection conditions, and calculating a tone value of a pixel forming the potential contrast image as an intensity of the signal. The semiconductor substrate inspection apparatus according to claim 10, wherein: 12. The semiconductor device according to claim 11, wherein said determining means determines that a defect exists in said semiconductor substrate when a difference in signal intensity between different inspection conditions is equal to or less than a predetermined threshold value. Item 12. The semiconductor substrate inspection device according to item 10 or 11. 13. The determination means creates a histogram of the frequency of appearance for the signal intensity at the same location between the inspection conditions based on the potential contrast image, and when the semiconductor substrate satisfies a minimum required specification, The appearance frequency with respect to the signal strength of the same portion obtained between the inspection conditions is plotted as a defect determination level in the histogram, and among the areas of the histogram divided by the defect determination level, a region having a higher signal strength is determined as a defect. 12. The semiconductor substrate inspection apparatus according to claim 10, wherein the semiconductor substrate is determined as a determination area, and when there is the signal strength included in the defect determination area, it is determined that a defect exists in the semiconductor substrate. 14. The semiconductor device according to claim 13, wherein said determining means outputs information on position coordinates of a region on said semiconductor substrate surface corresponding to said signal intensity included in said defect determining region as information on said defect. 4. The semiconductor substrate inspection apparatus according to claim 1. 15. The information processing apparatus according to claim 1, wherein the determining unit determines information on a wiring resistance value in a surface region of the semiconductor substrate corresponding to the signal intensity as information on the defect based on a relationship between the signal intensity and the wiring resistance value. 15. The semiconductor substrate inspection apparatus according to claim 14, wherein the output is performed. 16. The system according to claim 10, wherein said plurality of DC voltages include a positive polarity voltage and a negative polarity voltage.
The semiconductor substrate inspection apparatus according to any one of the above. 17. The semiconductor substrate inspection apparatus according to claim 10, wherein the defect includes a defect that causes an electrical continuity failure in wiring of the semiconductor substrate. 18. The semiconductor substrate inspection apparatus according to claim 10, wherein said defect includes a defective formation of a contact hole or a via hole in said semiconductor substrate.