JP2002175693A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory that operates normally even when voltage being higher than power source voltage for normal operation is applied without preventing high speed operation at normal operation time. SOLUTION: High voltage/low voltage of power source voltage is detected by a power source detecting circuit and a second delay circuit 2 or a third delay circuit 3 of which the delay time is different from each other is switched by a switching circuit 4 in accordance with the above detection signal. Thereby, since a sense amplifier is driven with timing in accordance with each power source voltage, potential difference of a pair of bit lines required for normal operation of the sense amplifier can be secured. Hence, malfunction of the sense amplifier can be prevented. Also, even in power source voltage for normal operation, since a delay time is not required to be lengthened longer than required, operation can be performed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
(Static RAM) etc.
In particular, it relates to control of the operation timing of the sense amplifier.

[0002]

2. Description of the Related Art A semiconductor memory device is required to guarantee operation not only at a power supply voltage during normal use but also at a power supply voltage during a voltage acceleration test. The power supply voltage during the voltage acceleration test is set to a voltage higher than the power supply voltage during normal use.

FIG. 12 shows a configuration of a generally used semiconductor memory. As shown in FIG. 12, the semiconductor memory device includes a memory cell array 21, a row decoder 2
2. Column decoder 23, address buffer 24, clock circuit 25, sense amplifier 26, and output buffer 27
Etc. A plurality of word lines WL and bit line pairs BL and / BL are arranged in the memory cell array 21, and memory cells MC are connected to these word lines WL and bit line pairs BL and / BL.

In the above configuration, when data in a memory cell is read, address signals A0, A1,... Are supplied to a row decoder 22 via an address buffer 24, and the row decoder 22 responds to the cell to be accessed in accordance with the address signal. Select the word line. Similarly, the bit line pair BL, / BL is selected by the column decoder 23,
Data of the memory cell is read through the bit line pair. The potential difference of the data read to the bit line pair is amplified by the sense amplifier 26 and output via the output buffer 27. In the above operation, the clock circuit 25 controls each operation timing such as activation of a word line and driving of a sense amplifier.

Generally, in order for a sense amplifier to operate stably, it is necessary that the potential difference between a pair of bit lines is equal to or greater than a certain value.

FIG. 13A shows an operation timing from activation of a word line to start of operation of a sense amplifier when a power supply voltage is a voltage V11 in a normal operation. As shown in FIG. 13A, by appropriately setting the time T12 at which the sense amplifier enable signal SAEN rises from the time T11 at which the word line WL is activated, the potential difference between the bit line pair is predetermined at the time T12. The value is set to V12. Thus, the potential difference between the pair of bit lines can be reliably amplified in the sense amplifier 26.

FIG. 14 shows an example of the clock circuit 25. This clock circuit includes a plurality of inverter circuits and a NAND circuit.

[0008]

The clock circuit 25 generates the sense amplifier enable signal SAEN using a delay circuit including a plurality of inverter circuits. Generally, in this type of delay circuit, the delay time becomes shorter as the power supply voltage becomes higher. On the other hand, the potential difference between the bit line pair is
It does not depend much on the power supply voltage, and there is no large difference in how the potential difference opens even if the power supply voltage increases.

FIG. 13B shows the operation timing when the power supply voltage is the high voltage V13 as in the voltage acceleration test. As shown in FIG. 13B, the time from the time T13 when the word line WL is activated to the time T14 when the sense amplifier enable signal SAEN rises is shorter than that at the time of the voltage V11 in the normal operation for the above reason. Has become. For this reason, at time T14, the potential difference between the bit line pair becomes only V14 smaller than V12,
The potential difference required for the stable operation of the sense amplifier cannot be obtained. Therefore, the sense amplifier malfunctions.

As described above, since the clock circuit 25 and the sense amplifier 26 have opposing power supply voltage dependencies, a malfunction occurs when the power supply voltage increases. For this reason, even if the device operates normally in the power supply voltage range during normal operation, it may not operate normally in the high voltage range during the voltage acceleration test. In this case, the semiconductor chip is treated as a defective product, which causes a decrease in yield.

Therefore, conventionally, the number of delay stages of the inverter circuit is increased, and the delay time of the delay circuit at the power supply voltage during the normal operation is increased in advance to allow a margin. By doing so, even when the delay time becomes short at a high power supply voltage, it is possible to secure a potential difference between the bit line pair that does not cause the sense amplifier to malfunction. Therefore, the malfunction of the sense amplifier at the time of the high power supply voltage can be avoided.

However, according to the above method,
Although the enable signal SAEN can be output at a faster timing, the output timing of the enable signal SAEN is delayed in order to guarantee operation at a high power supply voltage. Therefore, the output timing of the enable signal SAEN is delayed more than necessary at the power supply voltage during the normal operation, which hinders the semiconductor chip from operating at high speed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to apply a voltage higher than a power supply voltage in a normal operation without hindering a high-speed operation in a normal operation. It is an object of the present invention to provide a semiconductor memory device that operates normally even in the event of a problem.

[0014]

In order to solve the above-mentioned problems, a semiconductor memory device of the present invention outputs a first detection signal when a power supply voltage is a first voltage, and outputs a first detection signal when the power supply voltage is the first voltage. When the second voltage is higher than the voltage, a power supply detection circuit that outputs a second detection signal, a first delay circuit that delays a clock signal, and a second delay circuit that is connected to an output terminal of the first delay circuit And a third circuit connected to the output terminal of the first delay circuit and having a longer delay time than the second delay circuit.
And when the first detection signal is supplied from the power detection circuit, the output signal of the second delay circuit is selected, and the second detection signal is supplied from the power detection circuit. And a switching circuit for selecting an output signal of the third delay circuit.

The semiconductor memory device of the present invention outputs a first detection signal when the power supply voltage is the first voltage, and outputs the second detection signal when the power supply voltage is the second voltage higher than the first voltage. A power detection circuit for outputting a detection signal, a first delay circuit for delaying a clock signal, and a series circuit in which a plurality of inverter circuits are connected in series, the series circuit having a first delay time having a first delay time A first output terminal from which a signal is output, and a second output terminal having a second delay time longer than the first delay time.
A second delay circuit having a second output terminal to which the signal of (a) is output, and, when a first detection signal is supplied from the power supply detection circuit, an output signal of the first output terminal is selected. ,
A switching circuit that selects an output signal of the second output terminal when the second detection signal is supplied from the power supply detection circuit.

Further, the semiconductor device is characterized by further comprising a sense amplifier which is activated in response to an output signal of the switching circuit and detects a potential of a bit line.

The semiconductor memory device of the present invention outputs a first detection signal when the power supply voltage is the first voltage, and outputs the second detection signal when the power supply voltage is the second voltage higher than the first voltage. A power detection circuit for outputting a detection signal, a first delay circuit for delaying a clock signal, and a series circuit in which a plurality of inverter circuits are connected in series, the series circuit having a first delay time having a first delay time A first output terminal from which a signal is output, and a second output terminal having a second delay time longer than the first delay time.
A second output terminal for outputting a third signal having a third delay time longer than the second delay time, and a third output terminal for outputting a third signal having a third delay time having a third delay time longer than the second delay time. The third
A delay circuit having a fourth output terminal from which a fourth signal having a fourth delay time longer than the delay time is output, and a first detection signal being supplied from the power supply detection circuit. When the output signal of the first output terminal is selected and the second detection signal is supplied from the power supply detection circuit,
A first switching circuit for selecting an output signal from the second output terminal and outputting the selected signal as a first control signal; and a third output circuit when the first detection signal is supplied from the power supply detection circuit. Selecting the output signal of the fourth output terminal, and selecting the output signal of the fourth output terminal as the second control signal when the second detection signal is supplied from the power supply detection circuit. And a switching circuit.

The semiconductor memory device of the present invention outputs a first detection signal when the power supply voltage is the first voltage, and outputs the second detection signal when the power supply voltage is the second voltage higher than the first voltage. A power supply detection circuit that outputs a detection signal, a first delay circuit that delays a clock signal, and a series circuit in which a plurality of inverter circuits and a NAND circuit are connected in series, the series circuit has a first delay time The first signal from which the first signal is output
A second delay circuit having a second output terminal from which a second signal having a second delay time longer than the first delay time is output, and a first output terminal from the power supply detection circuit. When the detection signal is supplied, the output signal of the first output terminal is selected. When the second detection signal is supplied from the power supply detection circuit, the output signal of the second output terminal is selected. A switching circuit for switching between the first and second switching circuits, a first output terminal that is supplied with an output signal of the switching circuit, and that outputs a first signal having a first delay time in accordance with the output signal;
A second output terminal for outputting a second signal having a second delay time longer than the second delay time, and a third output terminal for outputting a third signal having a third delay time longer than the second delay time. A third delay circuit having a fourth output terminal that outputs a fourth signal having a fourth delay time longer than the third delay time, and a third delay circuit that outputs a fourth signal having a fourth delay time longer than the third delay time. A first output terminal connected to the first and second output terminals for generating a first control signal;
And a second logic circuit connected to the third and fourth output terminals of the third delay circuit and generating a second control signal delayed from the first control signal. It is characterized by the following.

Further, the semiconductor memory device of the present invention is provided with a sense amplifier for detecting a potential of a bit line, a transistor for connecting the bit line to the sense amplifier in response to the first control signal, and the sense amplifier. And a second transistor for activating the sense amplifier in response to the second control signal.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a clock circuit of a semiconductor memory device according to the present invention. As shown in FIG. 1, in the first delay circuit 1, the clock signal CLK is supplied to the NAND circuit N1 via one input terminal of the NAND circuit ND1 and, for example, five serially connected inverter circuits.
D1 is connected to the other input terminal. The output terminal of the NAND circuit ND1 is connected to the input terminal of the inverter circuit IV1.

The output terminal of the inverter circuit IV1 is connected to the second
Is connected to the input terminal of the delay circuit 2. The second delay circuit 2 is formed by, for example, two inverter circuits. The output terminal of the inverter circuit IV1 is further connected to the input terminal of the third delay circuit 3. The third delay circuit 3 is formed by, for example, six inverter circuits.

The second delay circuit 2 and the third delay circuit 3
Are connected to the switching circuit 4. The switching circuit 4 switches the output signals of the second delay circuit 2 and the third delay circuit 3 in accordance with a signal supplied from a power supply detection circuit 11 described later to the connection node 5. The switching circuit 4 includes an inverter circuit IV2, transistors QP1 to QP4, and transistors QN1 to QN4. That is, in the switching circuit 4, the power supply node 6 to which the power supply VDD is supplied is connected to the P-channel MOS transistors QP1, QP2, the N-channel MOS transistor Q connected in series.
It is connected to the ground potential VSS via N1 and QN2. Further, these transistors QP1, QP2, QN
1, P-channel MOS connected in series in parallel with QN2
Transistors QP3 and QP4 and N-channel MOS transistors QN3 and QN4 are connected.

The connection node 5 is connected to an inverter circuit IV
2 input terminals. This inverter circuit IV
2 is connected to the gate of the transistor QP1 and the gate of the transistor QN1. Connection node 5 is connected to the gate of transistor QP2 and the gate of transistor QN3. The output terminal of the second delay circuit 2 is connected to the gate of the transistor QP3 and the transistor QN.
2 gates. The output terminal of the third delay circuit 3 is connected to the gate of the transistor QP4 and the gate of the transistor QN4. The connection node between transistors QP1 and QP2 is connected to the connection node between transistors QP3 and QP4. A connection node N1 between transistors QP2 and QN1 is
It is connected to the connection node between P4 and QN3.

The connection node N1 is connected to an inverter circuit IV.
3 is connected to the input terminal. This inverter circuit IV
The sense amplifier enable signal SAEN is output from the output terminal 3 and is input to a sense amplifier described later.

FIG. 2 shows an example of the power supply detection circuit 11. In the power supply detection circuit 11, a P-channel MOS transistor QP5 and a resistor R are connected in series between the power supply node 12 and the ground. The gate of the transistor QP5 is connected to a connection node N2 between the transistor QP5 and the resistor R. The connection node N2 is connected to the switching circuit 4 via inverter circuits IV4 and IV5 connected in series.
Is connected to the connection node 5. This power supply detection circuit 11 is based on the size of the transistor QP5 and the resistance of the resistor R.
The potential of the connection node N2 is set.

That is, when a normal power supply voltage is supplied to the power supply node 12, the potential of the connection node N2 is set to the low level, and the output terminal of the inverter circuit IV5 is set to the ground voltage VSS (low level). . When the high power supply voltage is supplied to the power supply node 12, the potential of the connection node N2 is set to the high level, and the power supply voltage VDD (high level) is output from the output terminal of the inverter circuit IV5. This output signal is input to the connection node 5 of the switching circuit 4, and the second delay circuit 2 and the third delay circuit 3 are switched according to the level.

The operation of the clock circuit in the above configuration will be described with reference to FIGS. FIG. 3 shows a voltage waveform of each part in FIG. 1, and the same parts as those in FIG. 1 are denoted by the same reference numerals.

When the clock signal CLK is supplied, the first
The clock signal CLK is supplied to one input terminal of the NAND circuit ND1 of the delay circuit 1, and the signal CLK (the waveform shown in FIG. 4A) through five inverter circuits is supplied to the other input terminal. . Therefore, the waveform at the output terminal of the NAND circuit ND1 is as shown in FIG. The output signal (c) of the inverter circuit IV1 is as shown in FIG. This signal (c) is delayed by the second delay circuit 2 and becomes as shown in FIG.
And the result is as shown in FIG.

When the power supply voltage is normally used, the output level of the power supply detection circuit 11 is low, and a low level is input to the connection node 5 of the switching circuit 4. Therefore, the transistors QP2 and QN1 are on, and the transistors QP1 and QN3 are off.

Therefore, when the signal (d) is at a low level, the transistor QP3 is turned on, and the connection node N1 is at a high level via the transistors QP3 and QP2.
Therefore, a low level is output from the output terminal of the inverter circuit IV3. When the signal (d) is at a high level, the transistor QN2 is turned on, and the connection node N1 is at a low level via the transistors QN1 and QN2.
Therefore, a high level is output from the output terminal of the inverter circuit IV3. That is, when the connection node 5 is at the low level, the second delay circuit 2 is selected, the output of the second delay circuit 2 is delayed via the two transistors of the switching circuit 4, and the output of the signal (f) is changed. A sense amplifier enable signal SAEN is output. During the above operation, the transistor QP4 and the transistor QN4 are turned on, but since the transistors QP1 and QN3 are turned off, no current path is formed. Therefore, the third delay circuit 3 is not selected.

On the other hand, when the power supply voltage is higher than the normally used power supply voltage as in the voltage acceleration test, the output level of the power supply detection circuit 11 is set to the high level, and the high level is input to the connection node 5 of the switching circuit 4. ing. Therefore, the transistors QP1 and QN3 are turned on, and the transistors QP2 and QN1 are turned off. When the clock signal CLK is supplied in this state, the signal (c) generated in the same manner as described above is applied to the second delay circuit 2 and the third delay circuit 3
4 (d) and (e). When the output signal (e) of the third delay circuit 3 is at low level, the transistor QP4 turns on, and the connection node N1 goes to high level via the transistors QP1 and QP4. Therefore, a low level is output from the output terminal of the inverter circuit IV3. When the output signal (e) of the third delay circuit 3 is at a high level, the transistor QN4 is turned on, and the connection node N1 is at a low level via the transistors QN3 and QN4. Therefore, the inverter circuit I
A high level is output from the output terminal of V3. That is,
When the connection node 5 is at the high level, the third delay circuit 3 is selected, and the output signal (e) of the third delay circuit 3 is delayed via the two transistors of the switching circuit 4 to generate the signal (g). ) Is output. During the above operation, the transistor QP
3. The transistor QN2 is turned on, but the transistor QN2 is turned on.
Since P2 and QN1 are off, no current path is formed. Therefore, the second delay circuit 2 is not selected.

FIG. 4 shows an example of the sense amplifier.
The sense amplifier 13 includes P-channel MOS transistors QP6 to QP9 and an N-channel MOS transistor QN
5 to QN7 and an inverter circuit IV6. The sense amplifier enable signal SAEN is supplied to the gates of the transistors QP6, QP7, QN7.
This sense amplifier 13 has a sense amplifier enable signal S
When AEN goes low, the bit line pair B is activated.
It amplifies the L and / BL signals and outputs a signal to the data line DQ via the inverter circuit IV6.

FIGS. 5A and 5B show operation timings when the clock circuit according to the present invention is used. FIG. 5A shows the operation timing at the power supply voltage V1 in the normal operation, and FIG. 5B shows the operation timing at the high power supply voltage V3.

As shown in FIG. 5A, the word line WL is activated at the time T1, and the clock signal CLK delayed by the second delay circuit 2 is used as the sense amplifier enable signal SAEN at the time T2.
3 is input. Therefore, bit line pair BL, / BL
Is V2 at time T2. Therefore, a potential difference required for normal operation of the sense amplifier can be secured.

As shown in FIG. 5B, the time T3
, The word line WL is activated, and the third delay circuit 3
Is input to the sense amplifier 13 as the sense amplifier enable signal SAEN at time T4. Therefore, the sense amplifier 1 lags behind the power supply voltage during normal operation shown in FIG.
3 is driven. Therefore, the potential difference between the bit line pair is equal to the time T.
4, the potential becomes V4, and a potential difference required for normal operation of the sense amplifier can be secured.

According to the first embodiment, the switching circuit 4 switches between the second delay circuit 2 and the third delay circuit 3 according to the power supply voltage, thereby switching the delay time of the clock signal CLK. I have. By doing so, the time from when the word line is activated to when the sense amplifier is driven can be changed according to the power supply voltage. Therefore, even at a high power supply voltage, a potential difference between the bit line pair necessary for the normal operation of the sense amplifier can be secured. Therefore, a malfunction of the semiconductor chip can be avoided at the time of the voltage acceleration test, so that a decrease in yield can be prevented.

In addition, even at the power supply voltage during normal operation, it is not necessary to make the time from activation of the word line to driving of the sense amplifier unnecessarily long. Therefore, the drive timing of the sense amplifier can be advanced within a range where a potential difference required for normal operation of the sense amplifier can be secured at the power supply voltage during normal operation. Therefore, the operation of the semiconductor chip can be speeded up.

(Second Embodiment) FIG. 6 shows a second embodiment of the clock circuit according to the present invention. As shown in FIG. 6, in the second embodiment, delay circuits DC1, DC2, and DC3 each including four inverter circuits are connected in series to a first delay circuit 1 via an inverter circuit IV1. I have. Since the configuration of the switching circuit 4 is the same as that of FIG. 1, a detailed circuit is omitted, and only an input node is shown. That is, the output terminal of the delay circuit DC1 is connected to the first input node 7. This first input node 7 is
Are connected to the gates of the transistors QP3 and QN2 shown in FIG. The output terminal of the delay circuit DC2 is connected to the second input node 8. The second input node 8 is shown in FIG.
Are connected to the gates of the transistors QP4 and QN4 shown in FIG. The output node 9 is connected to the connection node N1 shown in FIG.

In the second embodiment, a second delay circuit 2 having a normal delay time is constituted by the delay circuit DC1, and a second delay circuit having a longer delay time than the second delay circuit 2 is constituted by the delay circuits DC1 and DC2. 3 of the delay circuit 3.

With the above configuration, the delay circuit D
By changing the outlet of C2, the delay time of the third delay circuit 3 can be adjusted. That is, for example, the delay time can be adjusted by connecting the output terminal of the delay circuit DC3 or the connection node between the inverter circuits and the second input node 8.

According to the second embodiment, the same effects as in the first embodiment can be obtained.

Further, the number of inverter circuits forming the third delay circuit 3 can be appropriately changed. Therefore, for example, when an operation failure of the sense amplifier occurs in the operation test, the mask pattern is changed and the delay circuit DC
By connecting the output terminal of DC2 or DC3 to the second input node 8, the delay time can be adjusted. Therefore, it is possible to avoid a malfunction of the semiconductor chip and prevent a decrease in yield.

(Third Embodiment) FIG. 7 shows a third embodiment of the clock circuit according to the present invention. 7, the same parts as those in FIG. 1 are denoted by the same reference numerals.

In the third embodiment, two switching circuits 4a, 4a
b, four delay circuits DC4, DC5, DC6, DC
7 and two sense amplifier enable signals SA
EN1 and SAEN2 are generated. That is, as shown in FIG. 7, the clock signal CLK is input to the delay circuit DC4 constituted by the inverter circuits IV41, IV42, IV43, IV44 via the inverter circuit IV1 connected in series to the first delay circuit 1. ing. The output terminal of the delay circuit DC4 is connected to the input terminal of a delay circuit DC5 composed of inverter circuits IV51, IV52, IV53 and IV54 connected in series. The output terminal of the delay circuit DC5 is connected to the input terminal of a delay circuit DC6 composed of serially connected inverter circuits IV61, IV62, IV63 and IV64. The output terminal of the delay circuit DC6 is connected to the input terminal of a delay circuit DC7 including inverter circuits IV71, IV72, IV73, and IV74 connected in series. The output terminal of the delay circuit DC4 is connected to the first input node 7a of the switching circuit 4a. The output terminal of the delay circuit DC5 is connected to the second input node 8a of the switching circuit 4a. Further, the output node 9a of the switching circuit 4a is connected to the input terminal of the inverter circuit IV3a, and the sense amplifier enable signal SAEN1 is output from the output terminal of the inverter circuit IV3a.

The connection node between the inverter circuits IV62 and IV63 forming the delay circuit DC6 is connected to the switching circuit 4
b is connected to the first input node 7b. Also, inverter circuits IV72 and IV7 forming delay circuit DC7
3 is connected to the second input node 8 of the switching circuit 4b.
b. Further, the output node 9b of the switching circuit 4b is connected to the input terminal of the inverter circuit IV3b,
The sense amplifier enable signal SAEN2 is output from the output terminal of the inverter circuit IV3b. The output signal of the detection circuit is supplied to the switching circuits 4a, 4a
b.

In the switching circuits 4a and 4b, the connection node 5, the first input nodes 7a and 7b, the second input nodes 8a and 8b, and the output nodes 9a and 9b
Is the same as in the first and second embodiments.

FIG. 8 shows an example of the sense amplifier 13a applied to the third embodiment. This sense amplifier 1
3a shows that the sense amplifier enable signal is SAEN1, SEN
It has the same configuration as the sense amplifier 13 shown in FIG. 3 except that it is divided into two systems of AEN2, and the same parts are denoted by the same reference numerals. The sense amplifier enable signal SAEN1 output from the inverter circuit IV3a connected to the switching circuit 4a is supplied to the gates of the transistors QP6 and QP7, and the sense amplifier enable signal output from the inverter circuit IV3b connected to the switching circuit 4b. S
AEN2 is supplied to the gate of transistor QN7.

Regarding the operation of the clock circuit having the above configuration,
This will be described with reference to FIG. FIG. 9 shows voltage waveforms at various parts in FIG.

When the power supply voltage is normally used, the output level of the power supply detection circuit 11 is at a low level.
A low level is input to the connection nodes 5a and 4b. Therefore, the switching circuits 4a and 4b select the first input nodes 7a and 7b, respectively. When the clock signal CLK is supplied in this state, the output signal of the first delay circuit 1 shown in FIG. 7 has the waveform shown in FIG. The output signal of the first delay circuit 1 is supplied to an inverter circuit IV1,
The signal is supplied to the first input node 7a of the switching circuit 4a via the delay circuit DC4. Therefore, a signal delayed for a predetermined time is output through the output terminal 9a of the switching circuit 4a and the inverter circuit IV3a as shown in FIG. 9 (h).

On the other hand, the first input node 7 of the switching circuit 4b
b, an inverter circuit IV1, a delay circuit DC4, DC
5, and an inverter circuit IV constituting the delay circuit DC6
61, the signal delayed by IV62 is input. Therefore, as shown in FIG. 9 (i), the signal (i) delayed from the signal (h) is output via the output terminal 9b of the switching circuit 4b and the inverter circuit IV3b.

The signals (h) and (i) are input to the sense amplifier 13a as sense amplifier enable signals SAEN1 and SAEN2, respectively. Therefore, the sense amplifier 13a first turns on the transistors QP6 and QP7 in response to the sense amplifier enable signal SAEN1,
Connected to bit line pair BL, / BL. Thereafter, the transistor QN7 outputs the sense amplifier enable signal SAEN2.
And the sense amplifier 13a is activated to amplify the potential difference between the pair of bit lines BL and / BL.

When a high power supply voltage is supplied to the power supply detection circuit 11 during the voltage acceleration test, the output signal of the power supply detection circuit 11 is at a high level. For this reason,
The switching circuits 4a and 4b select the second input nodes 8a and 8b, respectively. When the clock signal CLK is supplied in this state, the output signal of the first delay circuit 1 shown in FIG.
The waveform is as shown in FIG. The output signal of the first delay circuit 1 is an inverter circuit IV1, delay circuits DC4, D
It is supplied to the second input node 8a of the switching circuit 4a via C5. For this reason, as shown in FIG. 9J via the output terminal 9a of the switching circuit 4a and the inverter circuit IV3a,
A signal delayed by a predetermined time is output.

On the other hand, the first input node 7 of the switching circuit 4b
b, an inverter circuit IV1, a delay circuit DC4, DC
5, a signal delayed by DC6 and inverter circuits IV71 and IV72 constituting the delay circuit DC7 is input. Therefore, a signal (k) delayed from the signal (j) is output through the output terminal 9b of the switching circuit 4b and the inverter circuit IV3b as shown in FIG. 9 (k).

The signals (j) and (k) are input to the sense amplifier 13a as sense amplifier enable signals SAEN1 and SAEN2, respectively.
Is driven, and a signal is output to the data line DQ.

According to the third embodiment, a plurality of switching circuits 4
a and 4b, and a sense amplifier enable signal SAEN having a different delay time due to the switching circuits 4a and 4b.
1. SAEN2 is generated. Therefore, the control timing of the sense amplifier can be finely adjusted according to the sense amplifier enable signals SAEN1 and SAEN2. Therefore, the sense amplifier can be activated after the potential of the bit line is established, and the potential of the bit line can be detected more reliably than in the first embodiment.

The same effect as in the second embodiment can be obtained by appropriately changing the outlet of the delay circuit.

(Fourth Embodiment) FIG. 10 shows a fourth embodiment of the clock circuit according to the present invention. 10, the same parts as those in FIG. 1 are denoted by the same reference numerals.

In the third embodiment, two switching circuits are used.
Generated two sense amplifier enable signals. On the other hand, the fourth embodiment generates a sense amplifier enable signal using one switching circuit and a plurality of delay circuits. That is, as shown in FIG.
Is supplied to the delay circuit DC8 via the delay circuit 1 of FIG. This delay circuit DC8 is configured by inverter circuit circuits IV81, IV82, IV83, IV84 connected in series. The output terminal of the delay circuit DC8 is connected to the switching circuit 4
Is connected to the first input node 7 of

Further, the output terminal of the delay circuit DC8 and the output terminal of the first delay circuit 1 are connected to the input terminal of the delay circuit DC9. The delay circuit DC9 includes a NAND circuit ND91 and inverter circuits IV92, IV93, IV connected in series to an output terminal of the NAND circuit ND91.
94. An output terminal of the delay circuit DC8 and an output terminal of the first delay circuit 1 are connected to an input terminal of the NAND circuit ND91. This delay circuit DC
The output terminal 9 is connected to the first input node 8 of the switching circuit 4.

The output terminal of the delay circuit DC9 and the output terminal of the first delay circuit 1 are connected to the delay circuit DC10.
Is connected to the input terminal of The delay circuit DC10 includes a NAND circuit ND101 and inverter circuits IV102 and IV connected in series to an output terminal of the NAND circuit ND101.
103 and IV 104. An output terminal of the delay circuit DC9 and an output terminal of the first delay circuit 1 are connected to an input terminal of the NAND circuit ND101.

Further, the output terminal of the delay circuit DC10
And an output terminal of the first delay circuit 1 is a delay circuit DC1
1 input terminal. The delay circuit DC11 includes a NAND circuit ND111 and inverter circuits IV112 and I2 connected in series to an output terminal of the NAND circuit ND111.
V113 and IV114. An output terminal of the delay circuit DC10 and an output terminal of the first delay circuit 1 are connected to an input terminal of the NAND circuit ND111.

On the other hand, the output terminal 9 of the switching circuit 4 is connected to the input terminal of the delay circuit DC12 via the inverter circuit IV3. The delay circuit DC12 includes inverter circuits IV121, IV122, IV123,
IV124.

The output terminal of the delay circuit DC12 and the output terminal of the inverter circuit IV3 are connected to the input terminal of the delay circuit DC13. The delay circuit DC13 includes a NAND circuit ND131 and inverter circuits IV132 and IV13 connected in series to an output terminal of the NAND circuit ND131.
3, IV134. The delay circuit D
The output terminal of C12 and the output terminal of the inverter circuit IV3 are connected to the input terminal of the NAND circuit ND131.

The connection node between the inverter circuits IV122 and IV123 forming the delay circuit DC12 and the inverter circuits IV133 and IV133 forming the delay circuit DC13
The connection node of V134 is connected to the input terminal of the NAND circuit ND2, and the output terminal of the NAND circuit ND2 is connected to the inverter circuit IV7. This inverter circuit IV
7 from the sense amplifier enable signal SAEN1
Is output.

The output terminal of the delay circuit DC13 and the output terminal of the inverter circuit IV3 are connected to the delay circuit DC14.
Is connected to the input terminal of The delay circuit DC14 includes a NAND circuit ND141 and inverter circuits IV142 and IV connected in series to an output terminal of the NAND circuit ND141.
143, IV144. An output terminal of the delay circuit DC13 and an output terminal of the inverter circuit IV3 are connected to an input terminal of the NAND circuit ND141.

Further, the output terminal of the delay circuit DC14 and the output terminal of the inverter circuit IV3 are connected to the delay circuit DC1.
5 is connected to the input terminal. The delay circuit DC15 includes a NAND circuit ND151 and inverter circuits IV152 and I52 connected in series to an output terminal of the NAND circuit ND151.
V153 and IV154. The output terminal of the delay circuit DC13 and the inverter circuit IV3
Is connected to the input terminal of the NAND circuit ND151.

The output terminal of the delay circuit DC13 and the connection node between the NAND circuit ND151 and the inverter circuit IV152 constituting the delay circuit DC15 are connected to the input terminal of the NAND circuit ND3, and the output terminal of the NAND circuit ND3 is connected to the inverter circuit. IV8 is connected. A sense amplifier enable signal SAEN2 is output from the output terminal of the inverter circuit IV8.

Regarding the operation of the clock circuit having the above configuration,
This will be described with reference to FIG. FIG. 11 shows voltage waveforms at various points in FIG.

When the power supply voltage is normally used, the output level of the power supply detection circuit 11 is at a low level, and a low level is input to the connection node 5 of the switching circuit 4. Therefore, the switching circuit 4 selects the first input node 7. When the clock signal CLK is supplied in this state, the output signal of the first delay circuit 1 shown in FIG. 10 has a waveform shown in FIG. The output signal of the first delay circuit 1 has a waveform shown in FIG. 11 (l) via the delay circuit DC8.
The output signal of the delay circuit DC8 is supplied to the first input node 7 of the switching circuit 4. Therefore, a signal delayed by a predetermined time is output through the output terminal 9 of the switching circuit 4 and the inverter circuit IV3, as shown in FIG. 11 (n).

The signal (n) has the waveform shown in FIG. 11 (o) via the inverter circuits IV121 and IV122 constituting the delay circuit DC12. This inverter IV1
The output signal of No. 22 is input to one input terminal of the NAND circuit ND2. The signal (n) is output from the NAND circuit ND131
Of the delay circuit DC12
Is input to one input terminal of the NAND circuit ND131. Therefore, the output of the NAND circuit ND131 is supplied via the inverter circuits IV132 and IV133 as shown in FIG.
The waveform shown in FIG. This signal (p) is supplied to the NAND circuit ND
2 is input to the other input terminal. Therefore, from the output terminal of the NAND circuit ND2 via the inverter circuit IV7,
The sense amplifier enable signal SAE shown in FIG.
N1 is output.

Thereafter, similarly, as shown in FIG. 11 (r), the sense amplifier enable signal SAEN delayed from the signal (q) from the output terminal of the inverter circuit IV8.
2 is output.

The sense amplifier enable signal SAEN
1, SAEN2 is supplied to the sense amplifier 13a,
The sense amplifier is driven in the same manner as the operation in the third embodiment, and a signal is output to the data line DQ.

On the other hand, when a high power supply voltage is supplied to the power supply detection circuit 11 during the voltage acceleration test, the output signal of the power supply detection circuit 11 is at a high level. For this reason,
The switching circuit 4 selects the second input node 8. When the clock signal CLK is supplied in this state, the output signal of the first delay circuit shown in FIG. 10 has a waveform shown in FIG. The output signal of the first delay circuit 1 is a delay circuit D
The signal is input to the other input terminal of the NAND circuit ND91 included in C91, and is input to one input terminal of the NAND circuit ND91 via the delay circuit DC8. This NAND circuit N
The output of D91 is the inverter circuit IV92, IV93, I
Through V94, the waveform becomes longer than in the normal use as shown in FIG. 11 (m). This signal (m) is input to the switching circuit 4. Thereafter, the inverter circuit IV7 and the inverter circuit IV8 are operated in the same manner as in the normal operation described above.
Via the sense amplifier enable signal SAEN which is further delayed than the sense amplifier enable signal during normal use.
1 and SAEN2 are output.

The rise time and fall time of the signal (q) can be changed by changing the outlets of the signals (o) and (p).

According to the fourth embodiment, the delay circuits DC12 to DC14 and the NAND circuits ND2 and N
D3 is provided. With such a configuration,
Sense amplifier enable signal SAE having different delay times
N1 and SAEN2 are generated. Therefore, the control timing of the sense amplifier can be finely adjusted according to the sense amplifier enable signals SAEN1 and SAEN2. Therefore, the sense amplifier can be activated after the potential of the bit line is established, and the potential of the bit line can be detected more reliably than in the first embodiment.

Further, by changing the outlet of the delay circuit input to the switching circuit, the same effect as in the second embodiment can be obtained.

In the first to fourth embodiments,
Although the method of defining the timing for driving the sense amplifier by the clock circuit has been described, the present invention is not limited to this, and can be applied to other methods.

Of course, various modifications can be made without departing from the spirit of the present invention.

[0080]

As described in detail above, according to the present invention,
A semiconductor memory device that can operate normally even when a voltage higher than the power supply voltage during normal operation is applied without hindering high-speed operation during normal operation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a clock circuit according to the present invention.

FIG. 2 illustrates an example of a power supply detection circuit.

FIG. 3 is a diagram showing voltage waveforms at various parts in FIG.

FIG. 4 is a diagram illustrating an example of a sense amplifier.

FIG. 5 is a diagram showing each operation timing by the clock circuit of FIG. 1;

FIG. 6 is a diagram showing a second embodiment of the clock circuit according to the present invention.

FIG. 7 is a diagram showing a third embodiment of the clock circuit according to the present invention.

FIG. 8 is a diagram showing an example of a sense amplifier having two control signal input terminals.

FIG. 9 is a diagram showing voltage waveforms at various parts in FIG. 7;

FIG. 10 is a diagram showing a fourth embodiment of the clock circuit according to the present invention.

FIG. 11 is a diagram showing voltage waveforms at various parts in FIG. 10;

FIG. 12 is a diagram showing a configuration of a general semiconductor memory.

FIG. 13 is a diagram showing operation timings of a conventional clock circuit.

FIG. 14 is a diagram showing a conventional clock circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st delay circuit, 2 ... 2nd delay circuit, 3 ... 3rd delay circuit, 4 ... Switching circuit, 5 ... Connection node, 6 ... Power supply node, ND1 ... NAND circuit, IV1-IV3 ... Inverter circuit QP1 to QP4 ... P-channel MOS transistors; QN1 to QN4 ... N-channel MOS transistors.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B015 HH01 JJ11 JJ24 KB12 KB23 KB84 KB89 KB92 MM07 QQ01 QQ18 RR07

Claims (6)

[Claims] 1. A power supply for outputting a first detection signal when a power supply voltage is a first voltage and outputting a second detection signal when a power supply voltage is a second voltage higher than the first voltage. A first delay circuit for delaying a clock signal; a second delay circuit connected to an output terminal of the first delay circuit; a second delay circuit connected to an output terminal of the first delay circuit; A third delay circuit having a delay time longer than that of the second delay circuit; and when the first detection signal is supplied from the power supply detection circuit, an output signal of the second delay circuit is selected. A switching circuit for selecting an output signal of the third delay circuit when the second detection signal is supplied from a power supply detection circuit. 2. A power supply for outputting a first detection signal when the power supply voltage is a first voltage, and outputting a second detection signal when the power supply voltage is a second voltage higher than the first voltage. A detection circuit; a first delay circuit for delaying a clock signal; and a series circuit in which a plurality of inverter circuits are connected in series. The series circuit outputs a first signal having a first delay time. A second delay circuit having a first output terminal, a second output terminal from which a second signal having a second delay time longer than the first delay time is output, 1 is selected when the output signal of the first output terminal is supplied, and when the second detection signal is supplied from the power supply detection circuit, the output signal of the second output terminal is selected. And a switching circuit for selecting a signal. Storage device. 3. The semiconductor memory device according to claim 2, further comprising a sense amplifier activated in response to an output signal of said switching circuit and detecting a potential of a bit line. 4. A power supply that outputs a first detection signal when the power supply voltage is a first voltage, and outputs a second detection signal when the power supply voltage is a second voltage higher than the first voltage. A detection circuit; a first delay circuit for delaying a clock signal; and a series circuit in which a plurality of inverter circuits are connected in series. The series circuit outputs a first signal having a first delay time. 1 output terminal, a second output terminal from which a second signal having a second delay time longer than the first delay time is output, and a third delay time longer than the second delay time. A third output terminal for outputting a third signal having a third delay time, and a fourth output for outputting a fourth signal having a fourth delay time longer than the third delay time. A delay circuit having an end, and a first detection signal supplied from the power supply detection circuit. The output signal of the first output terminal is selected, and when the second detection signal is supplied from the power supply detection circuit, the output signal of the second output terminal is selected and the first output signal is selected. A first switching circuit that outputs the control signal as a control signal, and when a first detection signal is supplied from the power supply detection circuit, an output signal of the third output terminal is selected. A second switching circuit for selecting the output signal of the fourth output terminal when the second detection signal is supplied and outputting the selected signal as a second control signal. 5. A power supply that outputs a first detection signal when the power supply voltage is a first voltage, and outputs a second detection signal when the power supply voltage is a second voltage higher than the first voltage. A detection circuit; a first delay circuit for delaying a clock signal; and a series circuit in which a plurality of inverter circuits and a NAND circuit are connected in series. The series circuit outputs a first signal having a first delay time. A first output terminal,
A second delay circuit having a second output terminal from which a second signal having a second delay time longer than the second delay time is output; and a first detection signal supplied from the power supply detection circuit. A switching circuit that selects an output signal of the first output terminal and switches to an output signal of the second output terminal when the second detection signal is supplied from the power supply detection circuit; A first output terminal to which an output signal of the circuit is supplied and for outputting a first signal having a first delay time in accordance with the output signal; a second delay time longer than the first delay time; A second output terminal for outputting a second signal having a third delay time, a third output terminal for outputting a third signal having a third delay time longer than the second delay time, and the third delay terminal. A fourth signal that outputs a fourth signal having a fourth delay time longer than A third delay circuit having a power terminal; a first logic circuit connected to the first and second output terminals of the third delay circuit for generating a first control signal; A second logic circuit connected to the third and fourth output terminals of the delay circuit and generating a second control signal delayed from the first control signal. . 6. A sense amplifier for detecting a potential of a bit line, a transistor for connecting a bit line to a sense amplifier in response to the first control signal, and a transistor provided in the sense amplifier, wherein the second control signal 6. The semiconductor memory device according to claim 4, further comprising a second transistor that activates the sense amplifier in response to the request.