JP2002175345A - Verifying method for circuit operation and verifying device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically verify at a high speed whether the respective constitutional elements of a semiconductor circuit to be verified satisfy electrical standard, such as voltages, currents and time standard such as voltage impression times. SOLUTION: In an initialization processing of a step 1, circuit diagram data (net list), standard information of the respective elements and input data as time waveform of the voltage or the current to be used for operational simulation are inputted and the circuit diagram data is developed on a memory. After that, operations of the semiconductor circuit to be verified are simulated by using the circuit diagram data and the input data in steps S2 to S10 and everchanging voltage values, current values in input terminals, etc., of the respective circuit elements are stored on the memory. In the case of the operational simulation, whether the respective circuit elements satisfy the corresponding voltage standard, current standard and time standard is verified simultaneously, based on the voltage values and current values stored in the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a circuit operation for automatically verifying whether or not each circuit element satisfies an element standard determined by device characteristics in the design of a semiconductor circuit having a large number of circuit elements and its layout design. The present invention relates to a verification method and a verification device.

[0002]

2. Description of the Related Art Conventionally, for example, in an LSI having a flash memory or a liquid crystal driver, an internal voltage higher than a power supply voltage is generated by using a booster circuit or the like inside the LSI, and the high voltage rewrites data in the flash memory. LCD display control is performed. Generally, in a flash memory LSI, for example, +10 to +20 V, and a liquid crystal driver L
In SI, a high voltage of +20 V or more is used. Furthermore,
Among LSIs of flash memories, there are LSIs using a negative high voltage of, for example, about −10V. In such an LSI that internally generates a high voltage, a internally generated high voltage is applied to circuit elements such as MOS transistors, capacitors, resistors, and diodes that constitute the LSI circuit.

On the other hand, in today's semiconductor processes, miniaturization and thinning have progressed, and it has become difficult to manufacture semiconductor devices that realize circuit devices that handle high voltages. For example,
When a high voltage is handled by an N-channel MOS transistor, there is a problem that electrons are trapped in a gate oxide film due to a hot electron phenomenon. This phenomenon is
This occurs because a high voltage is applied to the gate terminal of the MOS transistor whose channel is in the ON state. In the MOS transistor after this phenomenon occurs, the electrons are trapped in the gate oxide film, so that the channel is difficult to turn on even if the same gate voltage is applied thereafter.
The characteristics of the MOS transistor deteriorate. This hot electron phenomenon may occur depending on the number of times of applying the voltage or the application time even when a gate voltage that is not so high is applied. Therefore, when designing an LSI, it is necessary to pay attention to the voltage value of the gate voltage, the number of times of voltage application, and the application time. Naturally, if an excessively high voltage is applied, dielectric breakdown occurs, and the LSI itself becomes unusable.

Further, if a high voltage is used inside the LSI,
A large current is generated from this voltage source, and this excessive current
When flowing into the internal wiring of the SI, electromigration occurs, and there is a concern that the internal wiring may be disconnected. Further, as a problem caused by excessive current, there is heat generated by power consumption. When the temperature of the LSI rises due to the generated heat, deterioration of transistor characteristics, electromigration, breakdown of an oxide film, and injection of hot electrons become more remarkable, causing a failure of the LSI. These current and heat generation problems are due to the recent high speed operation of LS.
I is also one of the important design issues.

Conventionally, as a method and apparatus for verifying the operation of an LSI circuit, for example, Japanese Patent Laid-Open No. 2000-132578 proposes a technique for verifying only a voltage value. Hereinafter, this technique will be described with reference to FIG.

In FIG. 1, first, circuit diagram data to be verified and an input pattern used in a circuit operation simulation are prepared. The circuit diagram data is a netlist including element information such as transistors, capacitors, and resistors constituting the circuit and connection information between the circuit elements.
The input pattern is a change pattern on the time axis of a voltage or a current applied to an input terminal or an internal node (a terminal of a circuit element, etc.) of a semiconductor circuit to be analyzed. The circuit diagram data and the input pattern are input to a circuit simulation device, and an operation simulation is performed on a time axis using the simulation device to generate data of an analysis result. The analysis result data, the voltage condition specified by the condition input unit, and the circuit diagram data are input to the applied voltage detection device indicated by reference numeral 13 in FIG. The detection device 13 performs a process of determining whether the analysis result data satisfies the voltage condition or violates the voltage condition, detects a violating circuit element, and graphically displays the circuit element on a circuit diagram. Therefore, the designer grasps the violating part in the circuit diagram in which the violating circuit element is graphically displayed, and feeds it back to the circuit design.

[0007] The determination of the circuit operation on the time axis (time change) described above is referred to as a transient analysis (Transien).
t Analysis). Further, as a circuit operation simulation apparatus for performing a transient analysis using analog values of voltage and current, SPICE (Simu)
Lation Program with Integra
Software called "rated Circuit Emphasis" is generally used. This SPICE is E
WS (Engineering Work Station) and PC (Personal
Computer used in computers.

FIG. 11 shows a flow chart of the SPICE transient analysis. In the figure, first, "Initialize" is performed in step S1. As shown in detail in FIG. 12, this Initialize reads circuit diagram data in step S1a (Load Schematic net-list).
t), the circuit diagram data is expanded (stored) in a memory on the computer in step S1b (Expand
Schematic To memory), then
In step S1c, an input pattern is read (Load Stimulus data), and in step S1d, an initial value analysis (Computation) is performed.
(Initialize-point), the voltage and current value of all terminals of each circuit element at time “0”,
That is, an initial voltage value and an initial current value are obtained.

Next, in FIG. 11, in step S2, a time representing the real time in the operation simulation is shown.
"0" is substituted for TIME ". This time TIME increases as the simulation process proceeds.

When the above processing is completed, the process proceeds to step S3 and the subsequent steps to enter a simulation calculation loop. That is,
First, in step S3, the voltage value and the current value of each node stored in the memory of the computer are output to a file on the hard disk (Store Output).
s). In this case, the output is not limited to all nodes. If a node is specified, the output is performed only for the specified node. Next, in step S4, the current time TIME
Is the simulation end time. If it is the simulation end time, the process ends,
If it is not the end time, the process is continued and the process proceeds to step S5. In step S5, the time step value "DELTA"
Is set as the constant TS in the step value DELTA.
Substitute EP. The step value DELTA is a value indicating the progress of the time TIME in the simulation process, and the constant TSEP is an initial value of the progress. Since the step value DELTA has been determined, the process proceeds to step S
In 6, the voltage value and the current value of each node at time (TIME + DELTA) are calculated (Computa)
tion). Thereafter, in step S7, it is determined whether or not all calculations have converged and a value has been obtained. If converged, the time TIME is updated to (TIME + DELTA) in step S8, and the start of the calculation loop is started. The process returns to step S3. These series of operations are repeated until the simulation end time.

On the other hand, if the calculation result does not converge in step S7, the value of the step value DELTA is reduced in step S9 according to an arbitrary rule.
Returning to step S6, the calculation process is performed again. However, when the step value DELTA becomes smaller than the specific value in step S10, the simulation process is forcibly terminated.

The above step value DELTA and the convergence of the calculation result will be described with reference to FIG. In the drawing, the horizontal axis represents time, and the vertical axis represents the calculation result value of the voltage value or the current value. Assume now that the operation simulation has been completed by time TIME. Based on the voltage value and current value at this time, the voltage and current value at the next time (TIME + DELTA) are calculated, and this time (TIME + DELETE) is calculated.
The convergence of the result in A) is determined. The points that are determined to have not converged are (1) when there is an excessive calculation difference that greatly affects the simulation accuracy, and (2) when the calculation result does not converge at all and no calculation result is obtained. In FIG. 13, since the convergence did not occur at the time (TIME + DELTA), the time (TI) was determined using the step value DELTA ′ which is a smaller value than the step value DELTA.
The figure shows that the voltage value and the current value at (ME + DELTA ′) were calculated and it was determined that the convergence was achieved. As described above, when the convergence does not occur, the calculation accuracy and the convergence can be improved by reducing the step value DELTA as much as possible, but the progress of the operation simulation is slowed down.

[0013]

As described above, conventionally, as a method of automating condition verification and eliminating manual work, only voltage condition verification is automated.
There is no effective technology for automatically verifying voltage, current, and heat at the design stage, and at present, verification is performed visually by a designer.

However, in such a verification method,
There is a disadvantage that the verification accuracy is remarkably reduced due to the increase and complexity of the circuit scale today, and the design efficiency is poor.

Further, the conventional voltage verification method requires two processes, a circuit operation simulation and a condition verification process, so that the time efficiency of the verification operation is not good.

Further, the analysis result data of the condition verification is data in which the terminal voltage and the current of each circuit element transition with time, that is, the data.
Due to the waveform data on the time axis and the data size becoming large, the applied voltage detection device 13 in FIG. 10 needs to search for a violating part from this large size data, and the search time becomes long. In general, when the size of the semiconductor circuit to be verified is large or the simulation time is long, the data size of the analysis result data becomes large, so the terminal data of only the selected circuit element among all the circuit elements is analyzed. The data is output as data to reduce the data size. In this case, the applied voltage detection device 1
In the case of No. 3, since only the circuit elements of the output analysis result data can be verified, sufficient verification cannot be performed in some cases. Therefore, a large amount of analysis data is necessary for performing sufficient verification. Eventually, it was necessary to use analysis data of a large size or to repeat the condition verification processing a plurality of times. As described above, the conventional voltage verification method has a problem in terms of work efficiency.

In addition, the standard condition of the circuit element has a characteristic such that the deterioration resistance is determined by the applied voltage value and the application time, such as the oxide film deterioration characteristic. As described above, although it is necessary to verify the time condition indicating the voltage application time in addition to the electrical condition, conventionally, there was a disadvantage that the condition verification in consideration of the time condition could not be automatically performed. .

[0018]

SUMMARY OF THE INVENTION The present invention focuses on the above points, and an object of the present invention is to automatically verify the voltage, current and heat generation of each element of a semiconductor circuit at the design stage, It is an object of the present invention to provide a circuit operation verification method and a verification apparatus capable of verifying a semiconductor circuit at high speed without dividing the operation simulation and the condition verification process into two processes.

Still another object of the present invention is to automatically verify conditions of each element of a semiconductor circuit in consideration of a time condition in addition to the above-mentioned objects.

That is, a circuit operation verification method according to the present invention is a circuit operation verification method for verifying that each circuit element satisfies a standard in a semiconductor circuit in which a large number of circuit elements are laid out. , Condition information which is an electrical standard of voltage and current applied to each circuit element, circuit diagram data representing connection information of the semiconductor circuit to be verified, and input patterns with respect to time of voltage and current used for circuit operation simulation And, based on the read circuit diagram data and the input pattern, calculate the value of voltage or current with respect to time in each circuit element of the semiconductor circuit to be verified, and while storing the calculated value in a memory, Simulate the operation of the semiconductor circuit to be verified and use the voltage value or current value of each circuit element stored in the memory. Te, characterized in that each circuit element of the object to be verified semiconductor circuit verifies whether meets the specifications of the read condition information.

According to a second aspect of the present invention, in the circuit operation verification method according to the first aspect, the condition information includes an electric standard indicating a current density value and a heat generation amount of each of the circuit elements. The circuit diagram data of the semiconductor circuit to be verified includes layout information. Based on the current value of each circuit element stored in the memory and the layout information, various parts inside the semiconductor circuit to be verified are And a heat density analysis.

According to a third aspect of the present invention, in the circuit operation verification method according to the first aspect, the condition information includes a number of times of violation of an electrical standard or a time indicating a period during which a violation state is allowed. The standard specification is included, and using the voltage value or the current value with respect to the time at each circuit element stored in the memory, the number of violations of each circuit element of the semiconductor circuit to be verified or the allowable period of the violation is the time. It is also characterized by verifying whether it meets the technical standard.

According to a fourth aspect of the present invention, in the circuit operation verifying method of the first aspect, after the operation simulation and the condition verification of the semiconductor circuit to be verified are completed, the result of the condition verification is stored in the circuit. It is characterized in that the result of the operation simulation is displayed on a waveform display device for displaying the result of the operation simulation or on a design device used for semiconductor circuit design or layout design.

According to a fifth aspect of the present invention, in the circuit operation verifying method according to the first aspect, a verification period for performing a condition verification of the semiconductor circuit to be verified or a non-verification period for not performing the condition verification is performed. , And condition verification of the semiconductor circuit to be verified is performed during the verification period, or condition verification of the semiconductor circuit to be verified is not performed during the non-verification period.

According to a sixth aspect of the present invention, in the circuit operation verification method according to the first aspect, the standard of the condition information is the same for all circuit elements included in the semiconductor circuit to be verified. It is characterized by being designated or individually designated for each circuit element.

According to a seventh aspect of the present invention, in the circuit operation verifying method according to the sixth aspect, an operation simulation is performed on the semiconductor circuit to be verified with low accuracy and at high speed by using the input pattern. Creating operation information of each circuit element of the verification semiconductor circuit and circuit hierarchy information of the semiconductor circuit to be verified, and then, based on the operation information, the circuit hierarchy information, and the circuit diagram data, the semiconductor circuit to be verified. Out of the plurality of circuit portions having the same operation pattern and hierarchy, and this one of the plurality of searched circuit portions is subjected to condition verification only for each circuit element in one circuit portion. It is characterized in that the condition information of the standard is individually designated only for the circuit part.

In addition, the invention according to claim 8 is the circuit operation verification method according to claim 1, wherein a low-precision and high-speed operation simulation is performed on the semiconductor circuit to be verified using the input pattern. Operation information of each circuit element of the semiconductor circuit to be verified and circuit hierarchy information of the semiconductor circuit to be verified are created, and then, based on the operation information, the circuit hierarchy information, and the read circuit diagram data, the circuit information is obtained. Searching a plurality of circuit parts having the same operation pattern and hierarchy in the verification semiconductor circuit, integrating the searched plurality of circuit parts into one circuit part, and reducing the circuit diagram data. I do.

According to a ninth aspect of the present invention, there is provided a circuit operation verification apparatus for verifying that each circuit element satisfies a standard in a semiconductor circuit in which a large number of circuit elements are laid out. And condition information, which is an electrical standard of voltage and current applied to each circuit element, circuit diagram data representing connection information of the semiconductor circuit to be verified, and time of voltage and current used for circuit operation simulation. Reading means for reading an input pattern; and calculating a voltage or current value with respect to time in each circuit element of the semiconductor circuit to be verified based on the circuit diagram data and the input pattern read by the reading means, and Operation simulation means for simulating the operation of the semiconductor circuit under verification while storing a value in a memory; Verification means for verifying whether each circuit element of the semiconductor circuit to be verified satisfies the standard of the read condition information using a stored voltage value or current value of each circuit element. Features.

According to a tenth aspect of the present invention, in the circuit operation verification device of the ninth aspect, a waveform display means for displaying an operation simulation result of the semiconductor circuit to be verified by the operation simulation means, and a design of the semiconductor circuit. Or with design means used for layout design,
The result of the condition verification of the semiconductor circuit to be verified by the verification means is displayed on the waveform display means or the design means.

As described above, according to the first and ninth aspects of the present invention, in the operation simulation of the semiconductor circuit to be verified, the calculation result of the voltage or the current at every minute time is stored in the memory. Verify whether the components of the circuit meet the voltage and current standards. Therefore, since the data stored in the memory that can be read and written at high speed is used, the condition verification of the semiconductor circuit to be verified can be performed at high speed, and the verification time is shortened. In addition, since it is not necessary to record the analysis data (voltage value or the like) obtained by the operation simulation in a large-capacity hard disk device as in the related art, it is possible to perform verification with an inexpensive computer system.

According to the second aspect of the present invention, the electrical standard indicating the current density and the amount of heat generation is set as the condition information. Therefore, the concentration of the current density and the heat generation phenomenon due to the current are calculated from the current value obtained by the operation simulation. Can be analyzed. Therefore, the heat generation state of the semiconductor circuit to be verified can be grasped from the analysis result, so that the optimum design for the current and the heat can be performed, and the defect caused by the heat problem can be avoided. In addition, since the verification accuracy is higher than the manual verification, the design quality is improved.

Further, according to the third aspect of the present invention, as the condition information of the semiconductor circuit to be verified, the number of times of violation of the time standard, for example, the electrical standard, and the duration of the violation state are shortened even if the violation state occurs. Therefore, the relationship between the applied voltage and the application time can be verified, such as a deterioration phenomenon of the gate oxide film of the N-channel MOS transistor.

In addition, according to the fourth and tenth aspects of the present invention, the result of the condition verification is displayed on the waveform display device for displaying the operation simulation result. Can be displayed.
In addition, when the result of the condition verification is displayed on a design device used for designing a semiconductor circuit or a layout, a violating circuit element, a node, a layout position, a pattern, and the like can be displayed. Therefore, the visibility is good and the efficiency of verification confirmation is high.

In addition, in the invention according to the fifth aspect, the verification period for performing the condition verification or the non-verification period for not performing the condition verification is specified. Can be terminated.

According to the present invention, the standard of the condition information is specified collectively for all the circuit elements constituting the semiconductor circuit to be verified, or individually specified for each circuit element.
Therefore, it is possible to select both the batch designation and the individual designation as necessary, thereby achieving both the verification accuracy and the verification processing time.

Further, according to the present invention, for a plurality of circuit portions having the same operation pattern and hierarchy among the semiconductor circuits to be verified, the condition verification is performed on only one of the circuit portions. Since the number of circuits to be condition-verified is reduced, the speed of the condition verification process is increased.

In addition, in the invention according to claim 8, a plurality of circuit portions of the semiconductor circuit to be verified having the same operation pattern and hierarchy are integrated into one circuit portion so as to be integrated. Since the circuit diagram data is reduced, the condition verification of the verification target semiconductor circuit is speeded up by the reduction.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a circuit operation verification method and a verification apparatus according to an embodiment of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 shows an entire system including a circuit operation verification device according to an embodiment of the present invention.
The circuit operation verification device 1 shown in FIG. 1 simulates a circuit operation that operates on a computer such as an EWS or a PC.
This device is equipped with DA (Electronics Design Automation) software.

The circuit operation verifying apparatus 1 has, as input data, condition information 2 describing electrical and temporal standards of circuit elements, and circuit diagram data (net list) 3 which is connection information of a semiconductor circuit to be verified. Then, the input pattern 4 of the applied voltage and current necessary for the operation simulation is input. The circuit operation verification apparatus 1 performs an operation simulation based on these three input data, and performs an electrical simulation on each circuit element included in the semiconductor circuit to be verified, with respect to the voltage applied to the input terminal and the current flowing through the node. Alternatively, it is verified whether or not the time standard is satisfied, and a portion (circuit element) that violates the standard is detected. The detailed procedure of this verification is shown in the flowchart of FIG. The description of this procedure will be described later.

In FIG. 1, a simulation analysis result and a verification result 5 are generated upon completion of the verification processing.
Based on the analysis and verification results 5, the presence or absence of a circuit element that violates the electrical or temporal standard and the violating part are confirmed, and the violating part on the circuit diagram is displayed on the display device 6, and the confirmation is performed. I do. The display device 6 includes a voltage / current waveform display device (waveform display means) 6a, a circuit design device (design means).
6b and a layout design device (design means) 6c. The voltage / current waveform display device 6a displays a voltage or current waveform as a result of the operation simulation on a computer display. The circuit operation verification device 1 controls the voltage / current waveform display device 6a so as to automatically display, on the display of the computer, a waveform related to a violation portion of the voltage or current waveform. Therefore, the visibility of the contents of the violation is good, and the work of confirming the verification result is quick. Further, in order to display the information of the violating circuit element, CAD software used for the circuit design and the layout design in the circuit designing apparatus 6b and the layout designing apparatus 6c can be used, and the violation information and the violating circuit element can be easily obtained. Can be displayed on the display of the computer, and the violation part can be clearly grasped from the circuit diagram and the layout.

Next, a processing flow of the circuit operation verification device 1 shown in FIG. 2 will be described. This processing flow is different from the conventional processing flow in FIG. 11 in that a condition verification processing (Verified specificity) is performed after the convergence determination processing S7.
n) The point where the SV is incorporated in the operation simulation, and the process of writing the condition verification result to a file before termination (Terminate) (Store Verify)
d-Result) SR is added. With the configuration shown in FIG. 2, since the condition verification processing is performed in parallel during the operation simulation, the condition verification can be performed by using the analysis data of the voltage or the current developed in the memory. The details will be described below.

FIG. 3 shows a data structure of a circuit element developed on the memory. Individual circuit elements (Elmen
One data configuration is prepared for each t). This data configuration includes instance information (Instant
ce information), device information (De
device information, name of each terminal of the circuit element, voltage value, current value (Terminal nam)
e. Volt. Cur. ), Standard information (Verification condition) of condition verification,
And the result of condition verification (Verification Re
(sult). The instance information is information for distinguishing individual circuit elements, and includes information representing a hierarchical structure of a circuit. The device information includes:
For example, in the case of a MOS transistor, it is a device size such as a gate length or a gate width, and is a device parameter used for calculation of an operation simulation. Further, in the area of the name, voltage, and current value of each terminal of the circuit element, the voltage,
The current value is written. The standard information of the condition verification is information on whether its own circuit element is to be verified or not to be verified,
The contents of the verification condition are included. In the area of the result of the condition verification, if its own circuit element is the target of the condition verification,
The result of condition verification is stored. The result of this condition verification is
There are a value of a verification result (for example, a potential difference between two terminals) corresponding to the verification condition, the number of violations, a violation period, and a start and end time of the violation. The result area of the condition verification is not provided when its own circuit element is out of the target of the condition verification.

The development of the data of the circuit elements on the memory is performed by the initialization processing (I) of the simulation shown in FIG.
initialize). Details of this processing will be described with reference to FIG. In FIG. 4, first, in step S1a, the circuit diagram data stored as a file on the hard disk is read into the circuit operation verification device 1 (Road Schematic net-list).
t) In step S1b, this circuit diagram data is
Is developed on the memory with the data configuration of the circuit element (Exp)
and Schmatic To memory). Then, in step S1c, the standard information of the condition verification is read (Road Verify specific).
3), the contents of the condition verification for each circuit element are described in the area (Verif) of the standard information of the condition verification in the data configuration of FIG.
registration in the event condition). Finally, in step S1d, an input pattern is read (Load Stimulus Data), and in step S1e, an initial value analysis (Computation) is performed.
(initialize-point) to end the initialization processing.

In the processing flow of FIG. 2, step S1, especially steps S1a and S1 of FIG.
Reading means 10 for reading circuit diagram data (net list), condition information and input data is constituted by c and S1d. Further, in steps S2 to S10 of the processing flow, the voltage and current value of each circuit element is calculated for each time step value DELTA based on the read circuit diagram data and input data, and the calculated values are shown in FIG. The operation simulation means 11 simulates the operation of the semiconductor circuit to be verified while storing in the voltage storage area and the current storage area on the memory. Further, by the step SV of the same processing flow, each element of the semiconductor circuit to be verified is stored in the memory as shown in FIG. 3 by using the voltage on the memory, the voltage value and the current value stored in the current storage area. The read standard information for verification of conditions (Verification
and verification means 12 for verifying whether or not the condition (condition) is satisfied.

Next, the condition information of the electrical and temporal standards of specific circuit elements and the contents of verification will be described. N
The verification of the voltage applied to the MOS transistor will be described as an example with reference to FIG. FIG. 3A shows a circuit symbol of the NMOS transistor. The NMOS transistor has a gate (G), a drain (D), a source (S), and a substrate (B).
, And the voltage applied to each of them is Vg, Vg
d, Vs, and Vb. The voltage between terminals is as follows.

Gate-drain voltage Vgd = Vg-Vd Gate-source voltage Vgs = Vg-Vs Gate-substrate voltage Vgb = Vg-Vb Drain-source voltage Vds = Vd-Vs Drain-substrate voltage Vdb = Vd-Vb Source-substrate voltage Vsb = Vs-Vb Here, the electrical standard indicating the range of the applied voltage is set as follows. nvgd, nvgs, nvdb, nvd
s, nvdb, and nvsb are negative maximum values, pvgd, p
vds, pvgb, pvds, pvdb, and pvsb show a positive maximum value.

Nvgd ≤ Vgd ≤ pvgd nvgs ≤ Vgs ≤ pvgs nvgb ≤ Vgb ≤ pvgb nvds ≤ Vds ≤ pvds Nvdb ≤ Vdb ≤ pvdbnbs in the example of the operation shown in FIG. FIG. 4B shows a waveform of a voltage Vds applied between the drain and the source of a certain NMOS transistor. Here, the electrical standard of the drain-source voltage Vds is defined as Vds ≦ + 10V. That is, pvds
= 10V. As a result, reference numeral 8 in FIG.
In the periods indicated by 9, 10, 11, and 12 (hereinafter referred to as violation periods), the drain-source voltage Vds becomes a voltage that violates the standard. The circuit operation verification device 1 detects such a period, and outputs the start time and the end time of the standard violation, the period, the peak voltage value during the violation, and the number of appearances of the violation period together with the information of the circuit element. I do. An example of the verification result of the violation period 8 and the violation period 12 is shown below. In the case of the violation period 8, the start time of the standard violation is 5 ns and the end time is 7 n
s, the violation period is 2 ns, the peak value is 17.5 V, and the number of appearances is the first. In the case of the violation period 12, the start time of the standard violation is 50 ns, the end time is 55 ns, the violation period is 5 ns, the peak value is 15 V, and the number of appearances is the fifth.

Next, the temporal standard will be described. In the temporal standard, a start time and an end time to be verified and an allowable time of violation are specified. The result data of FIG. 5B is verified using this temporal standard. Start time of violation verification is 10 ns,
Assuming that the end time is 50 ns, the target time for violation verification is 1
0 ns to 50 ns, the violation period 9, 1
0 and 11 are detected. On the other hand, the allowable time of violation is 10n
In the case of s, only the violation period 9 is output as the verification result.

The verification of whether the above voltage standard and the time standard are satisfied or violated is performed during the circuit operation simulation (steps S1 to S10) shown in FIG. Processing (Verified
specification). That is, as the circuit element information of FIG. 3 developed on the memory, the area of the voltage value and current value of each terminal of each circuit element (Termin)
al Volt. Cur. ) Stores the voltage value and current value of each terminal obtained by the operation simulation,
Condition verification is performed using the stored voltage value and current value and the calorific value calculated from these values. Since the data on the memory can be read and written at high speed, the condition verification processing is performed at high speed.

Moreover, since the condition verification of the circuit element is performed during the operation simulation operation, the operation efficiency is higher than that in the conventional case where the condition verification is performed after the completion of the circuit operation simulation. Further, in the present embodiment, since the condition verification is performed using the circuit element information of FIG. 3 developed on the memory, it is not necessary to accumulate the analysis data used for the condition verification unlike the related art. Good use efficiency.

Further, for example, a flash memory, an LSI for a liquid crystal driver, or the like which handles a high voltage inside the chip.
In the SI, when the maximum voltage value applied to the circuit element is detected, only the necessary data out of the analysis data in the operation simulation is output as the analysis result, so that the electrical standard of the applied voltage is efficiently verified. be able to. Therefore, design errors such as destruction of circuit elements can be relatively easily avoided as compared with the related art.

Further, by using the time standard together with the voltage standard,
By setting the voltage applied between the gate and the substrate of the MOS transistor and the oxide film such as the capacitor and the voltage application time, the condition verification of the circuit element in consideration of the deterioration characteristics of the gate oxide film of the MOS transistor is also performed. It is possible to do.

Although not mentioned in the present embodiment,
It is also possible to specify a verification start time and an end time, and to specify a verification time. The specification of this verification time
Since the verification processing other than the verification time can be omitted, the verification processing can be speeded up. Further, a start time and an end time of a period during which the condition verification process is not performed may be designated. Furthermore, a plurality of types of electrical standards and time standards may be specified, or may be set for each circuit block or for each circuit element. In this case, it is possible to perform detailed condition analysis on the circuit blocks and circuit elements. Become. In addition, if a region to be subjected to the condition verification is specified in all the circuits, an unnecessary verification process of the circuit element can be omitted, and the processing time can be reduced.

Next, a description will be given of the condition verification for the electric standard of the current, using the NMOS transistor of FIG.
The gate current, drain current, source current and substrate current flowing into the four terminals of the NMOS transistor are represented by I
g, Id, Is, and Ib. Here, similarly to the electrical standard of the voltage, the electrical standard indicating the range of each applied current is set as follows.

Nig ≦ Ig ≦ pig nid ≦ Id ≦ pid nis ≦ Is ≦ pis nib ≦ Ib ≦ pib By defining the current condition information as described above, the current value flowing through each circuit element can be verified. Since the drain current Id and the source current Is of the transistor element are inevitably determined by the current driving capability of the transistor, that is, the ON resistance, it is often thought that the verification of the current value is not necessary. When applied, there is a phenomenon that a substrate current Ib is generated from the drain to the substrate. Therefore, the verification of the current value automatically specifies a location where this phenomenon occurs when designing a current-sensitive analog circuit. It is possible to design efficiently.

By verifying the current value in cooperation with the layout information of the semiconductor circuit, it is possible to verify the electrical standard relating to the current density and the heat generation. The current density is obtained from the current value obtained from the operation simulation and information such as the width of the internal wiring and the number and shape of the wiring contacts extracted from the layout information. By examining the current density, it is possible to identify a disconnection of the internal wiring due to electromigration caused by an excessive current, a power supply voltage drop location where a power supply wiring or a ground wiring is problematic, and a ground voltage rise location. Therefore, by cooperating with the three data of the analysis result of the operation simulation, the verification result of the element standard, and the layout information, it is possible to grasp a part that violates the electrical standard of the current density from the circuit diagram and the layout.

Further, the heat generation energy and the heat generation amount are calculated from the current values obtained by the operation simulation, and these are linked with the layout information, whereby the heat generation distribution in the chip can be known. As a result, thermal design of LSI and L
It is possible to specify a location where the characteristics of the transistor are degraded due to a rise in the temperature inside the SI. The analysis of the heat generation amount can be used for designing an LSI that consumes a large current, an LSI that operates at a high frequency, and the like.

In the present embodiment, the condition verification process is performed simultaneously with the operation simulation even when the current condition verification is performed, so that the working efficiency is high. Moreover, since the condition verification processing of the present embodiment is a form of sequential processing, it is possible to confirm the result of the condition verification during the operation simulation.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
The circuit operation verification method and the verification apparatus according to the embodiment will be described. In the present embodiment, the time for the condition verification processing is reduced in consideration of the hierarchical structure of the semiconductor circuit.

The procedure of the circuit operation verification according to the present embodiment is the same as the entire processing flow shown in FIG. 2, but the Initialize processing in step S1 in FIG. 2 is different. This I
FIG. 6 shows details of the initialize processing. In the figure, first, in step S1a, circuit diagram data is read, and in step S1b, the circuit diagram data is stored in a memory as shown in FIG. Next, step S1c
Reads the information of the condition verification, and verifs in FIG.
Write the information of the condition verification to the Condition Condition area. Here, the setting is such that the condition verification is still performed for all the circuit elements.

After the above processing is completed, step S1d
In step S, the input pattern is read.
Perform a temporary simulation at 1X (Tem
Polarly Transient Analysis
s). This temporary simulation is performed in a final operation simulation (Transient Anal).
Using the same program as that of the above-described method, the operation state or non-operation state of all circuit elements is obtained from the signal transmission state based on the input pattern, and operation information of each circuit element is created.
The operation information of the circuit element only needs to extract the switching state of the circuit element. Therefore, in the temporary simulation in step S1X, the time step value DELTA of the simulation is set to a large constant value TSEP so as to accelerate the time progress of the simulation, or the circuit element is replaced with a simple switch element to obtain a low accuracy. To execute simulation at high speed. The circuit operation information is generated by performing the temporary simulation.

Thereafter, in step S1Y, a process for individually designating condition verification is performed based on the output circuit operation information. In this individual designation process, first, based on the circuit operation information generated by the execution of the temporary simulation, the circuit grasped from the circuit diagram data, and the connection information of the circuit elements constituting the circuit, the hierarchy of the circuit is determined. Generate circuit hierarchy information indicating the structure. Then, based on the circuit hierarchy information, the circuit operation information, and the electrical or temporal standard shown in FIG. 1, a plurality of circuit elements having the same operation pattern and the same hierarchical state are recognized. Finally, the condition verification of FIG. 3 is performed for the circuit element performing the condition verification so that the condition verification is performed only for one circuit element among the plurality of circuit elements that perform the same operation in the same hierarchical state. Standard information (Verificatio
n Condition) is kept as it is, and the condition verification is held valid. On the other hand, the standard information of the condition verification is rewritten invalidly for other circuit elements that do not perform the condition verification (Update Memory). Thus, the specification information of the condition verification is updated, and the individual specification of the condition verification is performed.

After completing the above processing, step S1e
Operating point analysis (Computation Ini)
2 and returns to the main processing flow of FIG. 2, and based on this processing flow, a final circuit operation simulation (steps S1 to S10)
And a condition verification process (steps SV and SR).

Next, a specific example of the individual designation process will be described. FIG. 7A shows a circuit configuration of the memory LSI. This memory LSI includes four decoders having the same circuit structure. Each decoder is composed of two circuits A and B. The circuits A and B are MOS transistor elements MOS0 and MOS0, respectively.
MOS1. Normally, the circuit element range to be subjected to the condition verification for the memory LSI is the entire memory LSI as shown in FIG. That is, the condition verification is repeatedly performed on a plurality of circuit elements having the same operation pattern and the same hierarchical state. However, in the memory LSI of FIG. 7A, the circuits and circuit elements in which the circuits and the circuit elements are connected by thick connection lines are the same circuit and circuit elements, and the underlined circuit element MOS0 Perform the same operation and are in the same hierarchical state. Therefore, in the present embodiment, such hierarchical information is stored in step S1 in FIG.
It is obtained as circuit hierarchy information generated in Y. Therefore,
In the present embodiment, as shown in FIG. 7B, only one of the four decoders # 1 to # 4 having the same circuit configuration is subjected to the condition verification, and the range of the condition verification is limited. Limited. Therefore, as compared with the case of verifying the entire memory LSI, the size of the circuit to be verified is reduced to 1/4, so that the speed of the verification process can be expected.

(Third Embodiment) Next, a circuit operation verification method and a verification device according to a third embodiment of the present invention will be described. In the present embodiment, the Initial shown in FIG.
A part of the ize process is changed to initialize the Initial process shown in FIG.
This is the size processing.

That is, in the Initialize process of FIG. 8, a temporary simulation (T
emporally Transient Analyze
sis), the individual designation process (U
process (Modified Varif.) in the “Update Memory” in order to reduce the circuit diagram data.
Indication condition) is In in FIG.
It is different from the initialize processing. The specific processing contents of this reduction processing are as follows. Only one circuit part is left among a plurality of circuit parts having the same circuit operation and the same circuit configuration, and the other circuit parts are obtained from circuit diagram data stored in a memory. This is the process of deleting.

Therefore, in this embodiment, circuit operation information and circuit hierarchy information are generated by temporary circuit operation simulation as in the second embodiment, and the same circuit operation and the same circuit configuration are generated from these two pieces of information. Is searched, and as a result of the search, only one of the plurality of circuit parts that are the same as each other is left, and the other circuit parts newly create deleted circuit data. After that, a final circuit operation simulation and condition verification are performed using the newly created circuit diagram data. Therefore, the newly created circuit diagram data is subjected to a circuit scale reduction process, and the scale is smaller than the original circuit diagram data, so that the final operation simulation and condition verification can be performed at high speed. It is possible to do.

A specific example of the reduction process will be described with reference to FIG. FIG. 1A shows the hierarchical structure of the initial circuit configuration. When the circuit operation information and the circuit diagram data are analyzed, as shown in FIG.
For # 3 and # 4, the circuit element MOS1 performs the same operation and is in the same hierarchical state. On the other hand, for the decoder # 1, the circuit element MOS0 does not perform the same operation as the circuit elements MOS0 of the other decoders # 2, # 3, and # 4. It is to be noted that the circuit connected by the thick connection line and the circuit element underlined in FIG. Therefore, in the present embodiment, as shown in FIG. 10C, three decoders # 2, which operate in the same manner and are in the same hierarchical state,
For example, new circuit diagram data reduced to only the decoder # 3 among # 3 and # 4 is created.

As described above, the newly generated FIG.
By performing the final circuit operation simulation and the condition verification using the circuit diagram data of (c), the memory L
Verification processing can be speeded up as compared with the case where the entire SI is verified.

[0071]

As described above, according to the first and ninth aspects of the present invention, in the operation simulation of the semiconductor circuit to be verified, the calculation result of the voltage or current at every minute time is stored in the memory. In each case, it is verified whether or not the constituent elements of the semiconductor circuit to be verified satisfy the voltage standard or the current standard. Therefore, the condition verification of the semiconductor circuit to be verified can be performed at high speed, and the verification time can be reduced. This eliminates the need for a large-capacity hard disk device and enables verification with an inexpensive computer system.

According to the second aspect of the present invention, since the electrical information indicating the current density and the heat generation is set as the condition information, the heat generation state of the semiconductor circuit to be verified is grasped, and the optimum current and heat are determined. The design can be made possible and defects caused by thermal problems can be avoided. In addition, since the verification accuracy is higher than the manual verification, the design quality is improved.

Further, according to the third aspect of the present invention, since the time standard is set as the condition information of the semiconductor circuit to be verified, the applied voltage and its applied voltage are reduced like the deterioration phenomenon of the gate oxide film of the N-channel MOS transistor. It is possible to verify the relationship with the application time.

In addition, according to the fourth and tenth aspects of the present invention, the result of the condition verification is displayed on the waveform display device for displaying the operation simulation result or the design device used for designing the semiconductor circuit or layout. Thus, the visibility can be improved, and the efficiency of verification confirmation can be improved.

In addition, according to the fifth aspect of the present invention, since the verification period or the non-verification period is designated, the verification period can be limited and the condition verification can be completed in a short time.

According to the invention of claim 6, since the setting of the condition information standard for the circuit element of the semiconductor circuit to be verified is collectively specified or individually specified, the collective specification and the individual specification can be performed as necessary. By making a selection, it is possible to achieve both verification accuracy and verification processing time.

According to the seventh aspect of the present invention, with respect to a plurality of circuit parts having the same operation pattern and hierarchy among the semiconductor circuits to be verified, condition verification is performed on only one of the circuit parts. Therefore, the speed of the condition verification processing can be increased.

In addition, according to the present invention, a plurality of circuit parts having the same operation pattern and hierarchy among the semiconductor circuits to be verified are integrated into one circuit part. Since the circuit diagram data is reduced, the condition verification of the semiconductor circuit to be verified can be speeded up.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a circuit operation verification system including a circuit operation verification device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing details of an operation verification method by the circuit operation verification device of the embodiment.

FIG. 3 is a diagram illustrating a data configuration of a circuit element developed on a memory;

FIG. 4 is a flowchart illustrating details of an initialization process in step S1 in the operation verification method of FIG. 2;

FIG. 5A is a diagram illustrating a potential difference relationship between respective terminals of an NMOS transistor, and FIG. 5B is a diagram illustrating an example of a result of performing a condition verification;

FIG. 6 is a flowchart illustrating details of an initialization process in the operation verification method according to the second embodiment of this invention.

7A is a diagram showing a specific circuit of a semiconductor circuit to be verified, and FIG. 7B is a diagram showing an operation verification method according to a second embodiment of the present invention applied to the semiconductor circuit to be verified in FIG. It is a figure showing a verification range in the case of having performed.

FIG. 8 is a flowchart illustrating details of an initialization process in an operation verification method according to a third embodiment of the present invention.

9A is a diagram showing a specific circuit of a semiconductor circuit to be verified, FIG. 9B is a diagram showing an analysis result of a hierarchical structure of the semiconductor circuit to be verified in FIG. 9A, and FIG. FIG. 14 is a diagram showing a reduction result of the semiconductor circuit under verification when the operation verification method of the third embodiment is applied to the semiconductor circuit under verification of FIG.

FIG. 10 is a diagram showing a circuit operation verification system including a conventional applied voltage detection device.

FIG. 11 is a flowchart illustrating a procedure of a conventional operation simulation.

FIG. 12 is a diagram illustrating details of an initialization process in step S1 of the flowchart in FIG. 11;

FIG. 13 is a diagram illustrating a relationship between a time step value DELTA in a conventional operation simulation and convergence of a calculation result of a voltage value.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Circuit operation verification device 2 Condition information of electrical standard and time standard 3 Circuit diagram data (net list) 4 Input pattern 5 Analysis result and verification result 6 Display device 6a Voltage / current waveform display device (waveform display means) 6b Circuit Design device (design means) 6c Layout design device (design means) 10 Reading means 11 Operation simulation means 12 Verification means

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor, Kazuichi Nishida 1006, Kazuma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Ikuo Fukugami 1006, Oji Kadoma, Kadoma, Osaka Pref. (72) Inventor Ken Kawai 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. AB02 AC11 AE14 AE16 AE18 AE23 AG01 AL09 AL11 5B046 AA08 BA04 JA01 JA04 5F064 BB12 BB21 BB40 CC09 DD04 HH06 HH07 HH09 HH10 HH14 HH15 HH17

Claims (10)

[Claims] 1. A circuit operation verification method for verifying that each circuit element satisfies a standard in a semiconductor circuit in which a large number of circuit elements are laid out. Condition information, which is a standard, circuit diagram data representing connection information of the semiconductor circuit to be verified, and input patterns with respect to time of voltage and current used for circuit operation simulation, and the read circuit diagram data and input pattern are read. Based on, calculate the value of the voltage or current with respect to time in each circuit element of the semiconductor circuit under verification, and, while storing the calculated value in a memory, simulate the operation of the semiconductor circuit under verification, Each circuit element of the semiconductor circuit to be verified reads out the readout using the voltage value or the current value of each circuit element stored in the memory. A circuit operation verification method characterized by verifying whether or not a standard of embedded condition information is satisfied. 2. The condition information includes an electrical standard indicating a current density value and a heating value of each of the circuit elements, and the circuit diagram data of the semiconductor circuit to be verified includes layout information. 2. The circuit according to claim 1, wherein a current density analysis and a heat generation analysis at various points inside the semiconductor circuit to be verified are performed based on a current value of each circuit element stored in the memory and the layout information. Operation verification method. 3. The condition information includes a number of violations of an electrical standard or a temporal standard indicating a period during which a violation state is allowed, and a time at each circuit element stored in the memory. 2. The circuit according to claim 1, further comprising verifying whether the number of violations of each circuit element of the semiconductor circuit to be verified or the allowable period of the violation satisfies the time standard by using a voltage value or a current value with respect to the circuit. Operation verification method. 4. After the operation simulation and the condition verification of the semiconductor circuit to be verified are completed, the result of the condition verification is used for a waveform display device for displaying the result of the operation simulation, a semiconductor circuit design or a layout design. 2. The circuit operation verification method according to claim 1, wherein the method is displayed on a design device. 5. Specifying a verification period for performing a condition verification of the semiconductor circuit to be verified or a non-verification period not performing the condition verification, performing a condition verification of the semiconductor circuit to be verified during the verification period, or 2. The circuit operation verification method according to claim 1, wherein condition verification of the semiconductor circuit to be verified is not performed during the non-verification period. 6. The standard of the condition information may be specified collectively for all circuit elements included in the semiconductor circuit to be verified, or may be individually specified for each circuit element. 2. The circuit operation verification method according to 1. 7. A low-precision and high-speed operation simulation is performed on a semiconductor circuit to be verified using the input pattern, and operation information of each circuit element of the semiconductor circuit to be verified and circuit hierarchy information of the semiconductor circuit to be verified. Then, based on the operation information, the circuit hierarchy information, and the circuit diagram data, a plurality of circuit portions having the same operation pattern and hierarchy are searched in the semiconductor circuit to be verified. In order to perform condition verification only on each circuit element in one circuit part of the plurality of circuit parts,
7. The circuit operation verification method according to claim 6, wherein the standard condition information is individually designated only for one circuit part. 8. A low-accuracy and high-speed operation simulation is performed on a semiconductor circuit to be verified using the input pattern, and operation information of each circuit element of the semiconductor circuit to be verified and circuit hierarchy information of the semiconductor circuit to be verified. And thereafter, based on the operation information, the circuit hierarchy information, and the read circuit diagram data, search a plurality of circuit portions having the same operation pattern and hierarchy in the semiconductor circuit to be verified, 2. The circuit operation verification method according to claim 1, wherein the plurality of searched circuit parts are integrated into one circuit part, and the circuit diagram data is reduced. 9. A circuit operation verifying apparatus for verifying that each circuit element satisfies a standard in a semiconductor circuit in which a large number of circuit elements are laid out. Means for reading condition information, which is a standard, circuit diagram data representing connection information of the semiconductor circuit to be verified, and input patterns with respect to time of voltage and current used for circuit operation simulation, and read by the reading means Based on the circuit diagram data and the input pattern, a voltage or current value with respect to time in each circuit element of the semiconductor circuit to be verified is calculated, and while the calculated value is stored in the memory, the operation of the semiconductor circuit to be verified Using an operation simulation means for simulating a voltage value or a current value of each circuit element stored in the memory. And a verification means for verifying whether or not each circuit element of the semiconductor circuit to be verified satisfies the standard of the read condition information. 10. A semiconductor circuit to be verified by said verification means, comprising: waveform display means for displaying an operation simulation result of the semiconductor circuit to be verified by said operation simulation means; and design means for use in semiconductor circuit design or layout design. 10. The circuit operation verification device according to claim 9, wherein the result of the condition verification is displayed on the waveform display means or the design means.