JP2002171302A - Circuit and method for processing signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide signal processing technology capable of securing data communication inside a communication network even when the link layer of one node is changed from an active state to an inactive state inside the communication network. SOLUTION: In the signal processing circuit suitable to be used for at least one node of plural nodes forming the communication network, when the state of the link layer of one node is changed from the active state capable of communication to the inactive state incapable of communication, one node automatically issues bus reset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a signal processing circuit and a signal processing method for transmitting / receiving a signal between serially connected electric device networks, which include a standard interface.

[0002]

2. Description of the Related Art Heretofore, personal computers and peripheral devices such as video cameras, digital still cameras, scanners, printers, mice, and keyboards have been connected using different connectors and cables.

According to such a method, a separate interface is required for each peripheral device, and various types of cables extend from a personal computer, which complicates the connection.

Recently, IEEE1394 has been used as a unified interface for connecting peripheral devices such as digital video cameras, handy scanners, and digital still cameras that input and output data related to multimedia technology to information processing devices such as personal computers. Standards have been proposed and their practical use is progressing.

[0005] An interface based on the IEEE 1394 standard is an interface used for serial connection.

FIG. 5 shows an outline of a system configuration of an interface for performing communication via an IEEE 1394 serial bus. The interface is included in a large number of nodes (connection points existing between communication networks, specifically, electronic devices such as personal computers and peripheral devices). As shown in FIG. 5, the IEEE 1394 interface 101 includes a hardware unit 103 and a firmware unit 105. The hardware unit 103 includes a physical layer controller (PHY) 121 and a link layer controller 125. The firmware unit 105 includes the transaction layer 127 and the serial bus manager 113.
And

The physical layer controller 121 is composed of, for example, an integrated circuit (IC) and has functions such as bus initialization, transmission / reception data encoding / decoding, bus arbitration, and bias voltage output / detection. are doing. The link layer controller 125 is also configured by, for example, an IC, and has functions such as cycle control and packet transmission / reception. The physical layer controller 121 is connected to the serial bus 111, and is connected to the physical layer controller of another node via the serial bus 111.

[0008] The transaction layer 127 actually
It controls the entire EE communication network and, together with the link layer controller 125, performs the function of optimizing the bus utilization efficiency. The serial bus manager 113 performs power management of the bus, provision of a speed map, provision of a topology map, and optimization of the bus based on the map.

By using these interfaces, a large number of nodes can be serially connected. Therefore, the connection relationship between the nodes is simplified. The number of connectable nodes is as large as 63, and the distance between the nodes can be increased.

[0010] In a communication network conforming to the IEEE 1394 standard, a change in the physical network state is recognized by the physical layer. Upon recognizing a change in the state of the network, the physical layer automatically issues a bus reset immediately, and bus initialization of the entire network is started. As a result, all nodes on the network can recognize the new network state, and plug and play becomes possible.

[0011]

FIG. 6 shows an example of the IEEE 13 standard.
1 shows a configuration example of a communication network based on the 94 standard.
As shown in FIG. 6, a communication network 131 includes a personal computer (PC) 133, a digital video camera (DVC) 135, and a digital still camera (DS).
C) 137 and three electronic devices (nodes).
The personal computer 133 has two ports 14
1, 143 are included. The digital video camera 135 includes a port 145. Digital still camera 1
37 includes a port 147. Port 141;
The port (145) is connected by a cable (bus line) 151. The port 143 and the port 147 are connected by a cable 155.

In the configuration example of the communication network shown in FIG. 6, the personal computer 1 is connected via a cable 151.
Assume that data communication is being performed between the digital video camera 33 and the digital video camera 135. If one node, for example, a link layer included in the digital still camera 137 changes from an active state indicating a communicable state to an inactive state in which communication is not possible during data communication (for example, the power of the digital still camera 137 may be deactivated) ), Smooth data communication may not be performed.

[0013] The present invention provides a signal which enables smooth data communication in a communication network even when the link layer of one node changes from an active state to an inactive state in a communication network conforming to the IEEE 1394 standard. It is to provide processing technology.

[0014]

According to one aspect of the present invention, there is provided a signal processing circuit suitable for use in at least one of a plurality of nodes forming a communication network conforming to the IEEE 1394 standard. A signal processing circuit for automatically issuing a bus reset when the state of the link layer of the one node changes from an active state in which communication is possible to an inactive state in which communication is not possible. .

According to another aspect of the present invention, an IEEE 13
94. A signal processing method in a communication network including a plurality of nodes according to the H.94 standard, wherein a state of a link layer of at least one of the plurality of nodes is in an active state in which communication is possible or communication is not possible. A first step of determining whether or not the link layer of the one node is in an inactive state, and a physical layer of the one node automatically determines when the link layer of the one node is in an inactive state. And a second step of issuing a bus reset.

According to the above signal processing technique, when the link layer changes from the active state to the inactive state at one node, one node automatically issues a bus reset signal. A new communication network can be recognized, and communication can be quickly resumed.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing embodiments of the present invention, considerations made by the inventor will be described.

In the network as shown in FIG. 6, the inventor has proposed that even if the link layer of one node changes from an active state to an inactive state, another node can know the change in the state of the link layer. Compared to the time required to detect a physical network change,
I thought it would take quite a long time. If the link layer or transaction layer of one node changes from an active state to an inactive state, it may take a considerable time before the other nodes can communicate normally. There is.

For example, when isochronous (synchronous) communication is performed between nodes, when the link layer of the root node changes from an active state to an inactive state, the other nodes are in an inactive state. The cycle start packet is not transmitted until the change to another node is recognized as the root node, and the other nodes cannot transmit the isochronous packet.

Further, even when one node and another node are performing asynchronous communication (asynchronous type), when the state of the link layer of one node changes from an active state to an inactive state. The other node may wait for a response from the one node until the other node recognizes the change from the active state to the inactive state, and the communication may be interrupted. There is.

Therefore, when the physical layer of a node detects that the link layer of one node has changed from the active state to the inactive state, the physical layer of the node automatically issues a bus reset. So came up with the control.

Hereinafter, a signal processing technique according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4 together with an operation of a communication network based on a general IEEE 1394 standard.

FIG. 1A is a schematic diagram showing a configuration example of a communication network using an interface based on the IEEE 1394 standard, and FIG. 1B is a schematic diagram showing an example of the configuration of the communication network shown in FIG. FIG. 2C is a conceptual diagram illustrating a step of determining a node number (self ID). FIG. 2C illustrates a step of requesting a bus use right in the configuration example of the communication network illustrated in FIG. FIG. 2D is a conceptual diagram for explaining a step of licensing a bus or transmitting a DP (data prefix) signal in the configuration example of the communication network shown in FIG. 1A. 3 is a functional block diagram including a link layer controller and a physical layer controller signal processing circuit, and FIGS. 4A and 4B are block diagrams of the signal processing circuit. FIG. 3 is a diagram and a flowchart illustrating an outline of signal processing performed by the signal processing circuit.

FIG. 1A shows a communication network (network) using an interface based on the IEEE 1394 standard.
An example of the configuration will be described. In this example, node A is included in the communication network.
There are six nodes from to F.

There are two types of nodes, a node called a leaf and a node called a branch. A leaf is a node that is connected to only one device (for example, a personal computer). The branch is 2
A node connected to one or more devices. Devices that are not turned on are included in the device count.

In FIG. 1A, nodes A, E, and F are leaves. Nodes B, C, and D are branches. Each node has one or more ports (denoted by c or p). A bus line BL connecting the nodes is connected between the ports included in the nodes.

The first operation to be performed in automatically setting the communication network is to reset the bus line BL. When the reset operation starts, all the nodes stop reading and writing operations and stop data transfer.

Next, a phase for recognizing where the node is located in what kind of tree structure is entered.

By exchanging signals bidirectionally between the nodes, it is determined whether the own port is the parent port p or the child port c with respect to the port included in the partner node.

The port included in the previously inquired node becomes the parent port p. When the parent-child relationship is determined, the whole becomes a complete tree structure.

In FIG. 1A, only node B has no parent port p. Node B is the parent to all nodes and is called the root. There is only one root in a serially connected tree-structured communication network.

It should be noted that a force route (Force root) is
When the (_root) bit is set, the set node is forcibly set as the root node.

The arbitration (ar) described above
When the tree structure of the communication network is determined by the (bitration) step, the node number of the communication network is then determined.
Move on to step D).

Based on FIG. 1B, the node number (self I
The step of determining D) will be described.

After performing the above arbitration step, each node sends out its own ID packet. The information included in the self ID packet includes its own node number, where it is in the communication network, how many ports the node has, how many devices are connected to each port, and how each port is connected. Are they parents or children?
The node that first acquires the arbitration, for example, node A in FIG. 1B, acquires the node number (0).

A bit indicating whether the link layer is active or inactive is included in the self ID packet, and other nodes can recognize that the link layer of this node has become inactive. The contents of the self ID packet will be described later with reference to FIG.

The node A sends out a self ID packet having information of the node number (0). Since this packet is broadcast, all nodes know that “node number (0)” has been allocated.

Next, the node C that has acquired the arbitration becomes the node number (1). By transmitting the self ID packet having the information of the node number (1) by the node E,
Inform other nodes that “node number 1” has also been assigned.

Arbitration is performed so that the order in which all of the nodes A to F send their own ID packets is the leaf first, the branch next, and the root last. The route always sends the self ID packet last. Node B of root
Has the largest node number, for example, (5).

After the step of determining the self ID is completed, the apparatus enters an idle state for a period called a subaction gap. In the idle state, the node does not output an arbitration signal. When the initialization operation of the bus line is completed, asynchronous transfer or synchronous transfer between nodes in the communication network becomes possible.

The time from the start of the initialization operation to the bus line (after reset) to the completion of the initialization operation is about 200 μs. The time required for the initialization varies depending on the number of nodes included in the communication network.

The step of requesting the right to use the bus will be described with reference to FIG. 2C, and the step of sending a bus licensing or sending a DP (data prefix) signal will be described with reference to FIG. 2D.

A communication network serially connected using an interface based on the IEEE 1394 standard always performs arbitration of the right to use the bus prior to data transfer.

At a time, only one node performs data transfer. Therefore, no collision of data signals occurs.

As shown in FIG. 2 (C), when arbitration starts, one or more nodes issue a bus use request to the parent node (indicated by arrows parallel to the bus lines). The parent node further requests the right to use the bus toward the parent node. This request is finally delivered to route B.

As shown in FIG. 2D, route B, which has received the request for the right to use the bus line, determines which node is to use the bus line. A bus license is given to the node that has acquired the arbitration. At the same time, for nodes (nodes A and F) for which arbitration could not be obtained, DP (data pr)
efix) signal. Upon receiving the DP signal, the request for the right to use the bus line is rejected.

The node that has obtained the bus line license sends a signal indicating the transfer speed before starting data transfer. Usually three different data transfer rates (100 Mbit /
Second, 200 Mbit / sec, and 400 Mbit / sec).

In the asynchronous transfer method, data is sent from one node to the address space of another node.
The node ignores data signals applied to other than its own address.

The packet signal is transmitted from the communication transfer source node to the transfer destination node. When the transfer destination node returns an acknowledgment or returns a response packet, a transaction (a series of processing that occurs when transmitting and receiving desired data) is completed.

A communication network using an interface based on the IEEE 1394 standard requires synchronization data (Iss) that must guarantee that information transfer is completed within a fixed time.
Asynchronous data transfer that transfers synchronous data and asynchronous data that guarantees that data is always transmitted to the destination node
data transfer function of asynchronous data transfer for transferring the data.

The synchronous data is transferred on the bus at regular intervals. This time interval is called a synchronization cycle. One synchronization cycle is 125 μs. Root node (B)
Can be a cycle master, and a node called the cycle master controls synchronous transfer. When it becomes necessary to perform the synchronous transfer, the cycle master (node B) adjusts the time of each node. The time is represented by 32-bit data. This time is called a synchronization cycle time.

Cycle master (node B) is 125 μs
A cycle start packet is sent once per packet. A node desiring to transmit synchronous data performs arbitration following the cycle start packet and transmits synchronous data. During this synchronous cycle time, communication by asynchronous data is interrupted.

In the communication network shown in FIG. 2D, a case is considered where synchronous communication is performed between a non-root node, for example, node C, and a non-root node, for example, node D. Corresponding to FIG. 6, node C in FIG. 2D is a personal computer, node D is a digital video camera, and node B (root node) is a digital still camera.

As shown in FIG. 4A, the signal processing circuit 21 included in the physical layer of one node, for example, node B,
Determines whether the link layer of the node B is in an active state or an inactive state, and automatically issues a bus reset immediately when the link layer changes from the active state to the inactive state. The reset issuing circuit 23 is provided.

The signal processing circuit 21 may further include a force route bit clear circuit 25. The force route bit clear circuit 25 transmits a force route (Force_root) to a root node, for example, a node B.
If the t) bit is set, the force root bit is cleared in the above bus reset (initialization) operation so that the inactive root node (node B) does not become the root node again ( Forc
e_root = 0).

In the IEEE 1394 standard, a bus manager can specify a root node. If only one node has the Force_root bit (defined as a function of the physical layer) set on the communication network, this node becomes the root node after the bus reset. If no node with this bit is set on the network, or if there are two or more nodes, it is not known which node will be the root node.

Further, the signal processing circuit 21 is provided with a bus reset issuance control unit 27 for controlling whether a bus reset is issued or not issued when the link layer changes from an active state to an inactive state. May be. A control signal input to the bus reset issuing control unit 27 controls whether a bus reset is issued or a bus reset is not issued when the link layer becomes inactive. If the setting is made so as not to issue the bus reset, the operation is performed based on the general IEEE 1394 standard.

The bus reset issuing circuit 23 will be described in detail. Whether the link layer is active or inactive is determined by the LPS issued from the link layer.
The physical layer determines based on the (Link Power Status) signal (FIG. 3). For example, IEEE1394a_
According to the 2000 standard, when "0" is input to the LPS signal for a time _{equal to} or longer than T _{LPS #DISABLE} , it is recognized that the link layer is in an inactive state. T _{LPS # DISABLE} is, for example, 25
It is set as a value between μs and 30 μs. When recognizing that the link layer is in the inactive state, the signal processing circuit 21 automatically issues a bus reset signal. If the link layer remains active, the signal processing circuit does not issue a bus reset signal.

When the link layer changes from the active state to the inactive state, a bus reset is issued, and all nodes stop reading and writing operations and data transfer. Hereinafter, the signal processing step will be briefly described with reference to the flowchart of FIG.

First, in step S0, it is assumed that the link layer is in an active state. In step S1,
The bus reset issuance control unit 27 determines whether to issue a bus reset when the link layer becomes inactive or not to issue a bus reset. If it is determined in step S1 that a bus reset will be issued, the process proceeds to step S2.

In step S2, the bus reset issuing circuit 23 determines whether the link layer is in an active state. If it is determined that the link layer is in the inactive state, a bus reset is issued in step S4.
If the fourth route bit is set in one node in step S3, the fourth route bit clear circuit 25 clears the fourth route bit.

As described above, the self ID packet output after the bus reset includes data indicating the state of the link layer of the node (bit indicating whether the link layer is active or inactive), Can recognize that the link layer of one node (node B) has become inactive, based on the content of the self ID packet. Therefore, all nodes in the communication network can quickly recognize the state of the new communication network. When the new communication network is recognized, synchronous or asynchronous communication can be performed by an operation similar to the operation described with reference to FIG.

Next, a case where one node and another node perform asynchronous communication will be described. For example, FIG.
It is assumed that the node C is one node and the node D is another node. When the link layer of one node (node C) changes from an active state to an inactive state when one node (node C) and another node (node D) are performing asynchronous communication. , A bus reset is issued from one node (node C) by a signal processing circuit similar to the signal processing circuit shown in FIG. After the bus reset, the other node (node D) trying to communicate with the one node (node C) immediately changes this state (the link layer of the first node (node C) changes from an active state to an inactive state). Changed situation) can be recognized. Accordingly, when the link layer of one node (node C) changes from the active state to the inactive state, the reaction from the one node (node C) with which the other node (node D) has been communicating up to that point is assumed. Never wait.

The present invention has been described in connection with the preferred embodiments. However, the present invention is not limited to these embodiments. It will be obvious to those skilled in the art that various changes, improvements, combinations, and the like can be made.

[0065]

According to the present invention, even when the link layer of one node changes from an active state to an inactive state in a communication network, smooth data communication in the communication network is enabled.

[Brief description of the drawings]

FIG. 1A is a schematic diagram illustrating a configuration example of a communication network using an interface based on the IEEE 1394 standard, and FIG. 1B is a schematic diagram illustrating a configuration example of the communication network illustrated in FIG. , Node number (self I
It is a conceptual diagram for demonstrating the step which determines D).

FIG. 2C is a conceptual diagram for explaining a bus use right requesting step in the configuration example of the communication network shown in FIG. 1A, and FIG.
FIG. 3 is a conceptual diagram for explaining a step of sending a bus license or a DP (data prefix) signal in the configuration example of the communication network shown in FIG.

FIG. 3 is a functional block diagram including a link layer controller and a physical layer controller signal processing circuit.

FIG. 4A is a simplified block diagram of a signal processing circuit according to one embodiment of the present invention, and FIG.
FIG. 3 is a flowchart illustrating an outline of signal processing performed by a signal processing circuit.

FIG. 5 is a functional block diagram schematically showing a system based on the IEEE 1394 standard.

FIG. 6 is a diagram illustrating an example of a communication network based on the IEEE 1394 standard.

[Explanation of symbols]

 A, B, C, D, E, F: Node c: Child port p: Parent port BL: Bus line 11: Link layer controller 15: Physical layer controller 21: Signal processing circuit 23: Bus reset issuing circuit 25: Force route Bit clear circuit 27: Bus reset issue control circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 5B077 NN02 5K032 EC01 5K033 EC01 5K034 GG05 LL02 SS01

Claims (4)

[Claims] 1. A signal processing circuit suitable for use in at least one of a plurality of nodes forming a communication network conforming to the IEEE 1394 standard, wherein a state of a link layer of the one node is communication. A signal processing circuit in which the one node automatically issues a bus reset when a change from a possible active state to a non-active state where communication is not possible; 2. When a force root bit for forcibly becoming a root node is set for the one node, a bus reset is issued and the setting of the force root bit is released. 2. The signal processing circuit according to claim 1, further comprising a force route bit clear circuit. 3. The apparatus according to claim 1, wherein the first node does not issue a bus reset even when the state of the link layer of the one node changes from an active state in which communication is possible to an inactive state in which communication is not possible. 3. The signal processing circuit according to claim 1, further comprising a bus reset issuing control unit capable of performing the resetting. 4. A signal processing method in a communication network including a plurality of nodes in accordance with the IEEE 1394 standard, wherein a state of a link layer of at least one of the plurality of nodes is in an active state in which communication is possible. A first step of determining whether or not the link layer of the one node is in an inactive state. A second step in which the physical layer automatically issues a bus reset.