JP2002164946A - Decoding circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of a conventional decoding circuit that has sometimes selected an erroneous path when the C/N is small because the conventional decoding circuit provides a constant metric independently of the C/N since the metric of decoded information depends on the quantity of the C/N. SOLUTION: The C/N of a signal whose received amplitude is corrected is measured and a value a×mb that results from multiplying a correction value (a) with a branch metric mb is used for a new branch metric, and when the C/N is low, a contribution rate of the branch metric to a state metric is decreased and a weight is provided to a past state metric to select a path.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding circuit.

[0002]

2. Description of the Related Art FIGS.
This will be described with reference to FIG. FIG. 9 is a block diagram showing a configuration of a conventional decoding circuit. 1 is an input terminal of an in-phase component XI of a quadrature modulated wave signal as a received signal, 2 is an input terminal of a quadrature component XQ of a quadrature modulated wave signal as a received signal, 5 is a decoder, and 7 is an output terminal for outputting a decoded signal. It is. In FIG. 9, the decoder 5
Performs soft decision decoding using the in-phase component XI of the quadrature modulated wave signal supplied from the input terminal 1 and the quadrature component XQ of the quadrature modulated wave signal supplied from the input terminal 2. The decoded signal is output via the output terminal 7.

Next, the operation of decoding the input information sequence of the received signal input to the decoding circuit shown in FIG. 9 will be described with reference to FIG. FIG. 10 is a trellis diagram for explaining the decoding operation of the input information sequence. First, the Euclidean distance between the reception point and the identification point of a received signal is called a branch metric, and the sum of the branch metrics is called a state metric. The trellis diagram expresses a temporal change of a state transition of the decoded input information sequence. State transitions at each time are connected by paths. Further, the surviving path 26 is indicated by a thick solid line, and the non-surviving paths are indicated by a broken line and a thin solid line.

[0004] Each state (S ₀₀ ,
From four states) of _{S 10, S 01, S 11} , there paths could be connected toward the rear of the 4 states present 4. However, the value of the branch metric (time t = n) is added to the state metric of the surviving path (time t = n-1) (all weights for each path are added to each path), and the state at time t = n Find the metric,
One path with the lowest value of the state metric is
Select and leave as a surviving path until that time (n is a positive integer). This is repeated until the last time t = L (L = 7 in FIG. 10). As a result, at the last time, the path having the smallest value of the state metric is selected as a surviving path (L is an integer of 1 or more) and decoded.

The selection of a path will be described with reference to FIG. FIG. 11 is an IQ coordinate plan view showing reception points when the signal power to noise power ratio (hereinafter, referred to as C / N) is small. Time t
= n, reception point C + N formed by adding noise N to signal C
think of. The branch metric mb (0) for the discrimination point 28 (coordinates (x0, x1)) on the signal C side and the discrimination point 29 (coordinates (-x0, -x
Given the branch metric mb (1) for 1)), the next time t =
In the n + 1, "t = state in the n S ₀₀ of the state metric" + "branch metric mb (0)" and, "t = state S ₀₁ of the state metric in n" + "branch metric mb (1) smaller path of the value of "is selected, the state metric of the state S ₀₀ at t = n + 1 is a value smaller.

[0006]

In the above-mentioned prior art,
The state metric is obtained by integrating the branch metrics up to that point, and the branch metrics are integrated with equal weight regardless of the magnitude of C / N. However, since the certainty (metric) of the information changes depending on the magnitude of C / N, in the conventional method that provides a constant metric regardless of the magnitude of C / N, when the C / N is small, an incorrect path selection is performed. There is a disadvantage that it may be removed. An object of the present invention is to eliminate the above-mentioned disadvantages, when the C / N is small, reduce the contribution rate of the branch metric to the state metric, perform path selection with emphasis on the past state metric, and An object of the present invention is to provide a decoder capable of selecting a correct path even when / N is small.

[0007]

In order to solve the above problems, a decoding circuit according to the present invention measures the C / N of a signal obtained by correcting the amplitude of a received amplitude of a quadrature modulated wave signal, and obtains a branch metric m.
A value obtained by multiplying the value of b by a predetermined correction coefficient a is defined as a branch metric. Further, when the C / N is low, the decoding circuit of the present invention reduces the value of the branch metric by multiplying by the correction coefficient a, and makes the value of the past state metric dominant. As a result, when the C / N is low, a decoding circuit that can reduce the contribution rate of the branch metric to the state metric and perform path selection with emphasis on the past state metric is realized.

That is, the decoding circuit of the present invention receives a quadrature modulated wave signal and performs soft decision decoding using the received signal.
A C / N calculation circuit for calculating N, and when the calculated signal power-to-noise power ratio C / N is smaller than a predetermined value, reduce the contribution rate of the branch metric to the state metric to reduce the past state Path selection is performed with emphasis on metrics.
Further, the decoding circuit of the present invention receives the quadrature modulated wave signal,
In a decoding circuit that performs soft decision decoding using the received signal of the received signal, an automatic gain control circuit that corrects the amplitude of the in-phase component XI and the quadrature component XQ of the received signal, respectively, and a signal power to noise power ratio C from the received signal C / N calculation unit for calculating / N, and a branch metric mb which is a Euclidean distance between the reception point and the identification point of the amplitude-corrected signal, and a state metric of the surviving path at time t = n-1 is calculated at time t. = n branch metrics are added to obtain the state metric at time t = n.
A state metric having the lowest value as a surviving path at time t = n, repeating until time t = L, and selecting and decoding a surviving path at time t = L (n is a positive integer, L is 1
An integer greater than one), when the value of C / N signal power obtained by the calculation section to noise power ratio C / N is first greater than the predetermined number CN ₁ is to keep the branch metric mb, signal power to If the value of the noise power ratio C / N is smaller than the second predetermined number CN ₀ , the value mb / mb _max divided by the maximum value mb _max of the branch metric is used as the branch metric mb, and the signal power to noise power ratio C When the value of / N is smaller than the first predetermined number CN ₁ and larger than the second predetermined number CN ₂ , the branch metric has a predetermined change according to the signal power to noise power ratio C / N. Is used as a branch metric. Furthermore, as a correction coefficient a ′,

(Equation 2) Is used as the branch metric.

Therefore, the C / N calculator of the decoding circuit of the present invention comprises an automatic gain control circuit for correcting the amplitude of the in-phase component XI and the quadrature component XQ of the received signal, and a signal whose amplitude has been corrected by the automatic gain control circuit. And an average noise power calculation circuit for calculating an average noise power N _ave from the amplitude values of the in-phase component xi and the quadrature component xq, and the instantaneous received signal power (C + the instantaneous received signal power calculating circuit for obtaining the N) _inst, the instantaneous received signal power (C + N) _inst obtained by the instantaneous received signal power calculation circuit, the ratio between the average noise power _{N ave (C + N) inst} / And a C / N calculation circuit for _{obtaining a} signal power-to-noise power ratio C / N from N _ave . The average noise power calculation circuit of the decoding circuit according to the present invention includes a subtracter for obtaining a noise component by subtracting an identification value from an amplitude value of a signal whose amplitude has been corrected by the automatic gain control circuit, and a noise component obtained by the subtractor for determining a predetermined noise component. Accumulated period, average value of in-phase component
an accumulator for _obtaining n _i-ave and an average value n _{q-ave of} orthogonal components;
A square addition means for squarely adding the average values n _i-ave and n _q-ave obtained by the accumulator, and a square root of the value squared by the square addition means are obtained, and the average noise power N _ave = √ (n
_i-ave ² + n _q-ave ² ). The instantaneous received signal power calculation circuit of the decoding circuit according to the present invention includes a root mean square means for root mean square of the amplitude value of the signal whose amplitude has been corrected by the automatic gain control circuit, Circuit gain AGAI
From the ratio of the N, instantaneous received signal power (C + N) _in shea _t = √ (xi ² + x
q ² ) and an instantaneous received signal power calculation circuit for obtaining / AGAIN.

Further, a decoding circuit according to the present invention receives an orthogonal modulation wave signal and corrects a received amplitude value of the received signal. The decoding circuit further includes an in-phase component xi of the signal whose amplitude is corrected by the automatic gain control circuit. A first discriminator for discriminating the first discrimination value di, a first subtractor for subtracting the first discrimination value di from the in-phase component xi of the amplitude-corrected signal, and a value obtained by subtracting the first subtractor. A first absolute value circuit for obtaining an absolute value, a first accumulator for accumulatively adding the absolute value obtained by the first absolute value circuit,
A first divider circuit for calculating an average value of the accumulated value of the first accumulator for each predetermined bit, a first latch for storing an output of the first divider circuit for each predetermined bit, and a first latch A first squaring circuit for squaring the output, and a second identification value based on the quadrature component xq of the signal whose amplitude has been corrected by the automatic gain control circuit.
a second discriminator for identifying dq, a second subtractor for subtracting the second identification value dq from the orthogonal component xq of the amplitude-corrected signal,
A second absolute value circuit for obtaining an absolute value of the value subtracted by the second subtractor, a second accumulator for accumulatively adding the absolute value obtained by the second absolute value circuit, and a second accumulator. A second dividing circuit for calculating an average value of the accumulated value for each predetermined bit; a second latch for storing an output of the second dividing circuit for each predetermined bit; and a second latch for squaring the second latch output Squaring circuit, a first adding circuit for adding the output value of the first squaring circuit and the output value of the second squaring circuit, and a first square root for calculating the square root of the value added by the first adding circuit A first shift register that shifts the in-phase component xi of the amplitude-corrected signal by a predetermined bit, a third square circuit that squares the output value of the first shift register, and a quadrature component xq of the amplitude-corrected signal
A second shift register for shifting a predetermined bit
A fourth squarer circuit for squaring the output value of the shift register, a second adder circuit for adding the output value of the third squarer circuit and the output value of the fourth squarer circuit, and an output value of the second adder circuit A second square root circuit for obtaining a square root of the second square root circuit, a third division circuit for obtaining a ratio of an output value of the second square root circuit to a gain AGAIN of the automatic gain control circuit, an output value of the third division circuit, A fourth division circuit for calculating a ratio with respect to an output value of the first square root circuit. When soft decision decoding is performed using the amplitude value of the amplitude-corrected signal, the fourth division circuit outputs The value of the branch metric is corrected accordingly.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A decoding circuit according to the present invention measures the C / N of a signal obtained by amplitude-correcting a received amplitude value of a quadrature modulated wave signal, and corrects a branch metric mb given by the following equation (1). Coefficient a
Is multiplied by a × mb as a branch metric. If C / N is small, the value of the branch metric is reduced, and the value of the past state metric is dominant.

(Equation 3)

An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram showing the configuration of the decoding circuit of the present invention. 1 is an input terminal of the in-phase component XI of the quadrature modulated wave signal which is the received signal, 2 is an input terminal of the quadrature component XQ of the quadrature modulated wave signal which is the received signal, 3 is an automatic gain control circuit, 5 is a decoder, 56 is An average noise power calculation circuit, 57 is an instantaneous reception signal power calculation circuit, 58 is a C / N calculation circuit, and 7 is an output terminal for outputting a decoded signal.

In FIG. 1, an automatic gain control circuit 3 corrects the amplitudes of the in-phase component XI and the quadrature component XQ of the quadrature modulated wave signal supplied from the input terminals 1 and 2, respectively, to obtain an average noise power calculation circuit. 56 and an instantaneous received signal power calculation circuit 57. The average noise power calculation circuit 56 calculates the average noise power N _ave from the amplitude value of the amplitude-corrected signal.
It is given to the C / N calculation circuit 58. Instantaneous received signal power calculation circuit 57
Calculates the instantaneous received signal power (C + N) _inst from the amplitude value of the signal whose amplitude has been corrected, and _{supplies it} to the C / N calculation circuit 58. C / N calculation circuit 58 calculates the C / N from the ratio of the input instantaneous received signal power and (C + N) _inst and the average noise power _{N a ve (C + N)} inst / N ave, the decoder 5 Give to.

The decoder 5 is separately supplied from the automatic gain control circuit 3 with a signal in which the amplitudes of the in-phase component XI and the quadrature component XQ of the input quadrature modulated wave signal have been corrected in amplitude. The decoder 5 performs the calculation shown in Expression (1), corrects the branch metric and performs soft decision decoding, and outputs the decoded signal via the output terminal 7. When the C / N is small in this way, the contribution ratio of the branch metric to the state metric is reduced, and path selection is performed with emphasis on the past state metric.

One embodiment of the average noise power calculation circuit 56 used in FIG. 1 will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of one embodiment of the average noise power calculation circuit 56.
30 is an identification value di generator, 31 is an identification value dq generator, 50 and 51 are subtractors, 32 and 33 are absolute value circuits, 34 and 35 are accumulators, 53 and 54 are division circuits, and 36 and 37 are latches. , 38 and 39 are squaring circuits, 42 is an adding circuit, 44 is a square root circuit, 55 is a cumulative number M generator, 61 and 62
Is an accumulation register, and 59 and 60 are adders. The accumulator 34 includes an accumulation register 61 and an adder 59, and the accumulator 35 includes an accumulation register 62 and an adder 60.

In FIG. 2, the identification value di generator 30 has an identification value
di is generated and applied to the subtraction input side terminal of the subtractor 50. Further, the in-phase component XI of the quadrature modulated wave signal is provided to the addition input terminal side of the subtractor 50. Similarly, the identification value qi generation unit 31 generates the identification value qi and supplies it to the subtraction input side terminal of the subtractor 51. Further, the orthogonal component XQ of the orthogonal modulation wave signal is provided to the addition input terminal side of the subtractor 51. The subtractor 50 determines the identification value from the input in-phase component XI.
The di is subtracted, and a noise component ni (ni = XI-di) is output and given to the absolute value circuit 32. Similarly, the subtractor 51 subtracts the discrimination value dq from the input orthogonal component XQ and outputs a noise component nq (nq = XQ−d
q) is output and given to the absolute value circuit 33. The absolute value circuit 32 calculates the absolute value | ni | of the noise component ni of the in-phase component, and
Similarly, the absolute value circuit 33 obtains the absolute value | nq | of the noise component nq of the orthogonal component, and supplies it to the accumulator 35.

Next, an average value is obtained for each of the in-phase component and the quadrature component.
Since the signal points are arranged point-symmetrically with respect to the origin of the signal plane (IQ plane), the average value becomes 0 if averaged as it is. Therefore, an average is calculated after obtaining the absolute values of the in-phase component and the quadrature component. Thus, all signal points on the signal plane are all in the first quadrant (in-phase component I, quadrature component Q
(Both positive polarity), and the average value is obtained.

That is, the absolute value circuits 32 and 33 generate the noise component ni
The absolute values | ni | and | nq | of nq are output, and accumulators 34 and 35 are output.
Is the absolute value of the noise component, respectively, and M times accumulating outputs the accumulated value n _i-total and n _q-total expressed by the following equation (2).

(Equation 4)

Assume that the accumulator operates with the operation clock f _CLK (Hz), and it takes M / f _{CL K} (sec) to accumulate the noise component M times. The division circuits 53 and 54 divide the cumulative values _ni-total and _nq-total by the cumulative number M and output the average values _{ni -avg} and _nq-avg . formula
(3) is a calculation formula for calculating the average values _{ni -avg} and _nq-avg .

(Equation 5)

The output of the accumulator 34 is given to a division circuit 53,
The output of the accumulator 35 is provided to a division circuit 54. Division circuit 53
And the division circuit 54, separately, given the coefficients M output from the cumulative number M generator 55, and the n _q-avg orthogonal components and the average value n _i-avg-phase component are respectively determined by the factor M , Respectively, to latches 36 and 37, respectively. Latches 36 and 37 store the average values n _i-avg and n _q-avg for each M bits, respectively.
To the squaring circuits 38 and 39, respectively. Squared circuits 38 and 39
Squares the outputs of latches 36 and 37, respectively, and n _i-avg ²
And n _q-avg ² are output to the adder 42. Adder circuit 42
Adds the input squared value n _i-avg ² and n _q-avg ² to _obtain n
_i-avg ² + _{nq -avg} ² is output and given to the square root circuit 44.

The square root circuit 44 outputs the output _ni-avg of the adding circuit 42.
Take the square root of ² + n _q-avg ² , find the average noise power by equation (4), and output through the output terminal 73.

(Equation 6)

The instantaneous received signal power calculation circuit 57 used in FIG.
One embodiment will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of an embodiment of the instantaneous received signal power calculation circuit 57. 46 and 47 are shift registers, 40 and 41 are square circuits, 43
Is an addition circuit, 45 is a square root circuit, 48 is a division circuit, and 52 is a gain of the automatic gain control circuit. In the accumulative addition operation of the average noise power calculation circuit 56, M / f _{CL K} (s
ec), the shift registers 46 and 47, which shift the amplitude values xi and xq of the amplitude-corrected signal by M bits, to the operation clock f _CLK (H
Operate in z).

The squaring circuit 40 squares the output of the shift register 46 and supplies the squared value xi ² to the adding circuit 43. Square circuit 4
1 squares the output of the shift register 47 and gives the squared value xq ² to the addition circuit 43. The addition circuit 43 adds the outputs of the squaring circuits 40 and 41 and supplies the added value xi ² + xq ² to the square root circuit 45. The square root circuit 45 takes the square root of the output (xi ² + xq ² ) of the adder circuit 43 and outputs the square root value √ (xi ² + xq ² ). Division circuit 4
8 is obtained by dividing the output √ (xi ² + xq ² ) of the square root circuit 45 by the gain AGAIN of the automatic gain control circuit, and dividing the divided value by the instantaneous received signal power (C
+ N) _Inst . That is, (C + N) _inst = √ (xi ² + xq ² ) / AGAIN is calculated and output. The output こ の (xi
² + xq ² ) is divided by the gain AGAIN of the automatic gain control circuit 3.
This is because the reception amplitude value is multiplied by the gain AGAIN in the automatic gain control circuit 3.

An embodiment of the C / N calculation circuit used in FIG. 1 will be described with reference to FIG. FIG. 4 is a block diagram showing a configuration of one embodiment of the C / N calculation circuit of the present invention. 49 is a division circuit. The dividing circuit 49 calculates the instantaneous received signal power (C + N) _inst
= √ (xi ² + xq ² ) / AGAIN to the average noise power N _ave = √ (n _i-ave ²
+ n _q-ave Divide by ² ) and output the signal power to noise power ratio C / N. That is, C / N = (C + N) _inst / N _ave = (√ (xi ² + xq ² ) / AGAIN) / √
(N _i-ave ² + n _q-ave ² )

FIG. 5 shows the operation timing of the decoding circuit of the present invention.
It will be explained by. FIG. 5 is a diagram showing the operation timing of one embodiment of the decoding circuit of the present invention. As mentioned above Figure 4, C / N is a noise component accumulates M times, determined from the ratio of the future to determine the average noise power N _{a ve,} and the instantaneous received signal power (C + N) _inst. However, since the average noise power N _ave is determined for the first time by the M-th noise component, C / N
Can not ask. Therefore, the average noise power N _ave obtained from the accumulated value of the noise components during the period of time t = n−1 is held by using a latch during the next period of time t = n. Then, the instantaneous received signal power (C + N) _{inst at} time t = n−1 is delayed by one time period. As a result, at time t = n, time t
= n-1 for each C / N. That is, the cumulative calculation of the noise component and the calculation of the average noise power N _ave are performed in the period of time t = n−1, and the calculation of each C / N is performed in the period of time t = n.

The correction of the branch metric of the decoding circuit of the present invention will be described. For example, at time t = n, the signal C (x0,
x1) Identification point 2 on the signal C side of the reception point C + N with noise N added
Branch metric mb (0) for 8 (x0, x1) and identification point 29
(-X0, -x1) consider the branch metric mb (1) with respect to, in the next time t = n + 1, "the state S ₀₀ of the state metric (t =
n) “+ mb (0)” and “state S ₀₁ state metric (t =
n) The path with the smaller value of "+ mb (1) is selected, and the state S
The state metric of ₀₀ becomes the smaller value.

The area of the receiving point depending on the C / N will be described with reference to FIG. FIG. 6 shows an embodiment of the decoding circuit of the present invention.
FIG. 6 is a diagram illustrating a region of a reception point according to a difference in C / N. CN ₁ <C /
In the case of N (see FIG. 6 (a)), the area where the receiving point C + N exists is near the identification point 28 (the hatched portion in FIG. 6 (a)), You do not move from one quadrant. Therefore a "state metric of state _{S 00" + mb (0)} ,
"State S ₀₁ of the state metric" + mb may be selected the smaller path of the value of (1). In this case, there is no need to correct the branch metric, and the branch metric mb is used as it is, so the correction coefficient a = 1. From this, the branch metric is a × mb = m
becomes b. However, the maximum value of the branch metric is mb _max . For example, identification point 28 (+1, +1), signal C = √2, noise N = (√2) / 3
Then, CN ₁ becomes as follows. That is, CN ₁ = (√2) / ((√2) / 3) = 3 (true value) = 20 × log ₁₀ 3 = 9.54 ≒ 10 (dB)

If C / N <CN ₀ (see FIG. 6B), the receiving point C
The area where + N exists is the shaded area in FIG. 6B, and the receiving point may move from the first quadrant depending on the magnitude of the noise N. Therefore a "state metric of state _{S 00" + mb (0)} ,
"State S ₀₁ of the state metric" + mb (1) of not be able to choose the path of smaller value. So the branch metric
By multiplying mb (0) and mb (1) by the correction coefficient a = 1 / mb _max , the value of each branch metric is set to 1 or less. And then "state S ₀₀ of the state metric" + mb (0), "state S ₀₁ of the state metric" +
Select the path with the smaller value of mb (1). That maximum value of the branch metric because it is mb _max, the value of if the branch metric is a mb _{m ax,} that'll divided by mb _max,
The value of the branch metric can be 1.

When the branch metric corrected to a value of 1 or less is added to the state metric, the size of the compared state metric at the time of selecting a path is smaller than the value of the added branch metric. , The value of the past state metric becomes dominant. In other words, the value of the branch metric
By setting the value to 1 or less, the contribution to the state metric is minimized, and the path is selected with emphasis on the past state metrics. For example, identification point 28 (+1, +1), signal C = √
2, if noise N = 1, CN ₀ becomes as follows. That is, CN ₀ = (√2) / 1 = √2 (true value) = 20 × log ₁₀ (√2) = 3.01 ≒ 3 (dB)

When CN ₀ <C / N <CN ₁ (see FIG. 6C),
The region where the receiving point C + N exists is indicated by the hatched portion in FIG.
The receiving point does not move from the first quadrant due to the size of N. Therefore "state metric of state S _00" + mb (0)
When, "state S ₀₁ state metrics" + mb may be selected smaller path of the value of (1) as the state metric. However, compared to the case where CN ₁ <C / N, the value of the branch metric is large because the reception point C + N is far from the identification point 28. That is, the contribution rate of the branch metric to the state metric increases. In order to prevent this, the correction coefficient a =
Multiply by a ′ (1 / mb _max <a ′ <1) to reduce the value of the branch metric and reduce the contribution to the state metric.
That is, the path is selected with emphasis on the past state metrics. FIG. 7 shows a correction function of the branch metric. FIG. 7 is a diagram illustrating an embodiment of the relationship between the C / N value and the correction coefficient a of the decoding circuit of the present invention. The horizontal axis represents the value of C / N, and the vertical axis represents the correction coefficient a. When CN <C / N ₀ , correction coefficient a = 1 / mb _max , C / N ₀
When ≤CN≤C / N ₁ , correction coefficient a = a ', where a' is C / N
And the following equation (5).

(Equation 7) In the above embodiment, the correction coefficient a ′ is between 1 / mb _max and 1,
Although it is a function of CN expressed by a linear function, it is not necessary to be a temporary function, and for example, when CN becomes smaller, a correction coefficient a ′
May be a function in which the value of?

FIG. 8 shows the C / N and the correction coefficient a of the decoding circuit of the present invention.
FIG. 6 is a diagram showing an example of the relationship of FIG. FIG. 8 uses the average noise power calculation circuit described in FIG. 2, the instantaneous received signal power calculation circuit described in FIG. 3, and the C / N calculation circuit described in FIG. 3 is an automatic gain control circuit, 5 is a decoder, 30 is an identification value di generator, 31 is an identification value dq generator, 32 and 33 are absolute value circuits, 34 and 35 are cumulative adders, 36 and 37 are latches, 38 to 41 are square circuits, 42 and 43 are addition circuits, 44 and 45 are square root circuits, 46 and
47 is a shift register, 48 and 49 are division circuits, 50 and 51 are subtractors, 53 and 54 are division circuits, and 55 is a cumulative number M.

In FIG. 8, the automatic gain control circuit 3 corrects the amplitudes of the received amplitude values 1 and 2 of the quadrature modulated wave signal. The average noise power calculation circuit 56 calculates an average noise power N _ave from the amplitude value of the amplitude-corrected signal. The instantaneous received signal power calculation circuit 57 calculates the instantaneous received signal power (C + N) from the amplitude value of the amplitude-corrected signal.
_{Find inst} . The C / N calculation circuit 58 calculates the instantaneous received signal power (C +
N) Ratio of _inst and average noise power N _ave (C + N) The signal power to noise power ratio C / N is obtained from _inst / N _ave . Decoder 5 is given by equation (1)
And performs soft decision decoding. Like this
When the C / N is low, the contribution rate of the branch metric to the state metric is reduced, and path selection is performed with emphasis on the past state metric.

[0033]

According to the present invention, when the C / N is low, the contribution ratio of the branch metric to the state metric can be reduced, and the path selection can be performed with emphasis on the past state metric.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a decoding circuit of the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of an average noise power calculation circuit according to the present invention.

FIG. 3 is a block diagram showing a configuration of an embodiment of an instantaneous received signal power calculation circuit of the present invention.

FIG. 4 is a block diagram showing a configuration of an embodiment of a C / N calculation circuit according to the present invention.

FIG. 5 is a diagram showing operation timing of an embodiment of the decoding circuit of the present invention.

FIG. 6 is a diagram showing a region of a reception point due to a difference in C / N in an embodiment of the decoding circuit of the present invention.

FIG. 7 is a diagram showing an embodiment of the relationship between the C / N and the correction coefficient a of the decoding circuit of the present invention.

FIG. 8 is a block diagram showing a configuration of one embodiment of a decoding circuit of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional decoding circuit.

FIG. 10 is a trellis diagram for explaining an operation of decoding an input information sequence.

FIG. 11 is an IQ plan view showing reception points when C / N is low.

[Explanation of symbols]

1, 2: input terminal, 3: automatic gain control circuit, 5: decoder, 7: output terminal, 26: surviving path, 28, 29: identification point, 30, 31: identification value generator, 32, 33: absolute Value circuit, 34, 35: accumulator, 36, 37: latch, 38, 39,
40, 41: Square circuit, 42, 43: Adder circuit, 44, 45: Square root circuit, 46, 47: Shift register, 48, 49: Divider circuit, 50, 51: Subtractor, 52: Gain of automatic gain control circuit , 53, 54: Divider circuit, 55: Cumulative number M generator, 5
6: Average noise power calculation circuit, 57: Instantaneous reception signal power calculation circuit, 58: C / N calculation circuit, 59, 60: Addition circuit, 61, 6
2: Cumulative register.

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 5B001 AA10 AD06 5J065 AA01 AB01 AC02 AD10 AF02 AG05 AH02 AH03 AH05 AH06 AH12 AH21 5K004 AA08 JA02 JD05 JH03 JJ10 5K014 AA01 BA10 BA11 EA01 FA11 GA01 HA05

Claims (7)

[Claims] 1. A decoding circuit for receiving a quadrature modulated wave signal and performing soft-decision decoding using the received signal, comprising a C / N calculation circuit for obtaining a signal power-to-noise power ratio C / N of the received signal. If the obtained signal power-to-noise power ratio C / N is smaller than a predetermined value, the contribution rate of the branch metric to the state metric is reduced, and the path selection is performed with emphasis on the past state metric. A decoding circuit. 2. A decoding circuit for receiving a quadrature modulated wave signal and performing soft-decision decoding using a received signal of the received signal, comprising: an automatic gain for amplitude correcting the in-phase component XI and the quadrature component XQ of the received signal, respectively. A control circuit, and C / N for obtaining a signal power to noise power ratio C / N from the received signal.
The calculation unit, obtains a branch metric mb which is a Euclidean distance between the reception point and the identification point of the amplitude-corrected signal, and calculates a branch metric at time t = n as a state metric of a surviving path at time t = n-1. The state metric at the time t = n is obtained by addition, and the state metric having the lowest value is set as the surviving path at the time t = n, and the surviving path at the time t = L is repeated until the time t = L. (N is a positive integer, L is an integer of 1 or more), and the value of the signal power to noise power ratio C / N obtained by the C / N calculation unit is If it is larger than the predetermined number CN _{1 of 1} ,
Said branch metric mb used as is, the signal power when the value of noise power ratio C / N is a second predetermined number CN ₀ smaller than the maximum value mb _max divided by the value mb / mb _max branch metrics Is a branch metric mb, and when the value of the signal power-to-noise power ratio C / N is smaller than a _first predetermined number CN ₁ and larger than a _second predetermined number CN ₂ , The signal power to noise power ratio
A decoding circuit characterized by using a value obtained by multiplying a correction coefficient a 'that changes a predetermined value according to C / N as a branch metric. 3. The decoding circuit according to claim 2, wherein said correction coefficient a ′ is given by: A decoding circuit characterized in that: 4. The decoding circuit according to claim 2, wherein the C / N calculation unit corrects an amplitude of each of the in-phase component XI and the quadrature component XQ of the received signal. A circuit for calculating an average noise power N _ave from the amplitude values of the in-phase component xi and the quadrature component xq of the signal whose amplitude has been corrected by the automatic gain control circuit; and an in-phase component xi of the amplitude-corrected signal. An instantaneous received signal power (C + N) _inst circuit for calculating an instantaneous received signal power (C + N) _inst from the amplitude value of the orthogonal component xq; and an instantaneous received signal power (C + N) _{ins t} obtained by the instantaneous received signal power calculation circuit. And a C / N calculation circuit for calculating a signal power-to-noise power ratio C / N from a ratio (C + N) _inst / N _{ave of the} average noise power N _ave . 5. The decoding circuit according to claim 4, wherein the average noise power calculation circuit subtracts an identification value from an amplitude value of the signal whose amplitude has been corrected by the automatic gain control circuit to obtain a noise component. The noise component obtained by the subtracter is accumulated for a predetermined period, and the average value n _{i -ave} of the in-phase component and the average value n _{q-ave of the} quadrature component are accumulated.
An accumulator that calculates the square root of the value obtained by the square addition by the square addition means for square-adding the average values n _i-ave and n _q-ave obtained by the accumulator. And a mean noise power calculation circuit for _{obtaining a} noise power N _ave = √ ( _{ni -ave} ² + n _q-ave ² ). 6. The decoding circuit according to claim 4, wherein said instantaneous received signal power calculation circuit comprises: a root mean square means for root mean square of an amplitude value of the signal corrected in amplitude by said automatic gain control circuit; from the ratio of the gain AGAIN the square mean value said automatic gain control circuit by the instantaneous received signal power (C + N) _in shea ^{_{t = √ (xi 2 + xq}} 2) / AGAIN instantaneous received signal power calculation for determining the And a decoding circuit. 7. An automatic gain control circuit that receives a quadrature modulated wave signal and corrects a received amplitude value of the received signal, and a first identification value di from an in-phase component xi of the signal whose amplitude is corrected by the automatic gain control circuit. A first discriminator for discriminating the signal; a first subtractor for subtracting the first discrimination value di from the in-phase component xi of the amplitude-corrected signal; and an absolute value of a value subtracted by the first subtractor. And a first absolute value circuit for cumulatively adding the absolute values obtained by the first absolute value circuit.
An accumulator, a first divider circuit for calculating an average value of the accumulated value of the first accumulator for each predetermined bit, and a first divider for storing an output of the first divider circuit for each predetermined bit. A first squaring circuit for squaring the first latch output, and a second discriminator for discriminating a second discrimination value dq from a quadrature component xq of the signal whose amplitude has been corrected by the automatic gain control circuit. A second subtractor for subtracting the second identification value dq from the quadrature component xq of the amplitude-corrected signal, a second absolute value circuit for obtaining an absolute value of the value subtracted by the second subtractor, A second method for cumulatively adding the absolute values obtained by the second absolute value circuit;
An accumulator, a second divider circuit for obtaining an average value of the accumulated value of the second accumulator for each predetermined bit, and a second divider for storing an output of the second divider circuit for each predetermined bit. A second squaring circuit for squaring the second latch output; a first adding circuit for adding an output value of the first squaring circuit to an output value of the second squaring circuit; A first square root circuit for calculating a square root of the value added by the first adding circuit; a first shift register for shifting the in-phase component xi of the amplitude-corrected signal by a predetermined bit; and an output of the first shift register A third square circuit for squaring the value, a second shift register for shifting the quadrature component xq of the amplitude-corrected signal by the predetermined bit, and a fourth square circuit for squaring the output value of the second shift register. And the output value of the third squaring circuit and the A second addition circuit for adding the output value of the square circuit of the second addition circuit, a second square root circuit for obtaining a square root of the output value of the second addition circuit, an output value of the second square root circuit, and an automatic gain control circuit A third division circuit for calculating a ratio of the third division circuit to a gain, and a fourth division circuit for calculating a ratio between an output value of the third division circuit and an output value of the first square root circuit. A decoding circuit for correcting a value of a branch metric according to an output of the fourth division circuit when performing soft decision decoding using the amplitude value of the amplitude-corrected signal.