JP2002164387A - Method for mounting semiconductor device - Google Patents

Method for mounting semiconductor device

Info

Publication number
JP2002164387A
JP2002164387A JP2000362669A JP2000362669A JP2002164387A JP 2002164387 A JP2002164387 A JP 2002164387A JP 2000362669 A JP2000362669 A JP 2000362669A JP 2000362669 A JP2000362669 A JP 2000362669A JP 2002164387 A JP2002164387 A JP 2002164387A
Authority
JP
Japan
Prior art keywords
semiconductor device
amount
outer pad
lead frame
contaminant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000362669A
Other languages
Japanese (ja)
Inventor
Nobuaki Maruoka
伸明 丸岡
Yasuo Nakatsuka
康雄 中塚
Norikane Nahata
憲兼 名畑
Hitoshi Takano
均 高野
Yoshihisa Furuta
喜久 古田
Sadatoshi Tanegajima
貞利 種ヶ嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to JP2000362669A priority Critical patent/JP2002164387A/en
Publication of JP2002164387A publication Critical patent/JP2002164387A/en
Pending legal-status Critical Current

Links

Classifications

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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for mounting a semiconductor device having, proper soldering wettability, when the device is mounted, even if silicone adhesive is used as a heat resistant adhesive tape and the semiconductor device used therefor. SOLUTION: The method for mounting the semiconductor device comprises a step of soldering a circuit board using the device, in which a contaminant substance caused by the silicone adhesive is adhered to an outer pad and its adhering amount of the substance is 20 mg/m2 or less.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、製造時に使用した
耐熱性粘着テープのシリコーン系粘着剤に由来する汚染
物質が、アウターパッドに付着した半導体装置（ＬＳＩ
等）を用いて、配線基板へのはんだ付けを行う半導体装
置の実装方法、並びにそれに用いる半導体装置に関す
る。The present invention relates to a semiconductor device (LSI) in which a contaminant derived from a silicone-based pressure-sensitive adhesive of a heat-resistant pressure-sensitive adhesive tape used in manufacturing adheres to an outer pad.
And the like, and a method for mounting a semiconductor device to be soldered to a wiring board using the same, and a semiconductor device used therefor.

【０００２】[0002]

【従来の技術】近年、ＬＳＩの実装技術において、ＣＳ
Ｐ（Ｃｈｉｐ Ｓｉｚｅ／ＳｃａｌｅＰａｃｋａｇｅ）
技術が注目されている。この技術のうち、ＱＦＮ（Ｑｕ
ａｄＦｌａｔ Ｎｏｎ−ｌｅａｄｅｄ ｐａｃｋａｇ
ｅ）に代表されるリード端子がパッケージ内部に取り込
まれた形態のパッケージについては、小型化と高集積の
面で特に注目されるパッケージ形態のひとつである。こ
のようなＱＦＮの製造方法のなかでも、近年では複数の
ＱＦＮ用チップをリードフレームのパッケージパターン
領域のダイパッド上に整然と配列し、金型のキャビティ
内で、封止樹脂にて一括封止したのち、切断によって個
別のＱＦＮ構造物に切り分けることにより、リードフレ
ーム面積あたりの生産性を飛躍的に向上させる製造方法
が、特に注目されている。2. Description of the Related Art In recent years, in LSI mounting technology, CS
P (Chip Size / ScalePackage)
Technology is attracting attention. Among these technologies, QFN (Quu
adFlat Non-leaded package
The package in which the lead terminal represented by e) is taken in the package is one of the package forms that is particularly noted in terms of miniaturization and high integration. Among such QFN manufacturing methods, recently, a plurality of QFN chips are neatly arranged on a die pad in a package pattern area of a lead frame, and are collectively sealed with a sealing resin in a mold cavity. In particular, attention has been paid to a manufacturing method that dramatically improves productivity per lead frame area by cutting into individual QFN structures by cutting.

【０００３】このような、複数の半導体チップを一括封
止するＱＦＮの製造方法においては、樹脂封止時のモー
ルド金型によってクランプされる領域はパッケージパタ
ーン領域より更に外側に広がった樹脂封止領域の外側だ
けである。従って、パッケージパターン領域、特にその
中央部においては、アウターリード面をモールド金型に
十分な圧力で押さえることができず、封止樹脂がアウタ
ーリード側に漏れ出すことを抑えることが非常に難し
く、ＱＦＮの端子等が樹脂で被覆されるという問題が生
じ易い。In such a method of manufacturing a QFN that collectively seals a plurality of semiconductor chips, a region to be clamped by a mold during resin sealing is a resin sealing region extending further outside a package pattern region. Just outside of the. Therefore, in the package pattern area, especially in the center thereof, the outer lead surface cannot be pressed with sufficient pressure to the mold, and it is very difficult to suppress the sealing resin from leaking to the outer lead side. The problem that the terminals of the QFN and the like are covered with the resin is likely to occur.

【０００４】このため、上記の如きＱＦＮの製造方法に
対しては、リードフレームのアウターリード側に粘着テ
ープを貼り付け、この粘着テープの自着力（マスキン
グ）を利用したシール効果により、樹脂封止時のアウタ
ーリード側への樹脂漏れを防ぐ製造方法が特に効果的と
考えられる。For this reason, in the above-described method of manufacturing a QFN, an adhesive tape is attached to the outer lead side of a lead frame, and a resin sealing is performed by a sealing effect utilizing the self-adhesive force (masking) of the adhesive tape. It is considered that a manufacturing method for preventing the resin from leaking to the outer lead side at the time is particularly effective.

【０００５】このような製造方法において、耐熱性粘着
テープは最初の段階でリードフレームのアウターパット
面に貼り合わせられ、その後、半導体チップの搭載工程
やワイヤボンディングの工程を経て、封止樹脂による封
止工程まで貼り合わせられることが望ましい。したがっ
て、耐熱性粘着テープとしては、単に封止樹脂の漏れ出
しを防止するだけでなく、半導体チップの搭載工程に耐
える高度な耐熱性や、ワイヤボンデイング工程における
繊細な操作性に支障をきたさないなど、これらのすべて
の工程を満足する特性が要求される。[0005] In such a manufacturing method, the heat-resistant adhesive tape is bonded to the outer pad surface of the lead frame in an initial stage, and thereafter, is subjected to a semiconductor chip mounting step and a wire bonding step, and is then sealed with a sealing resin. It is desirable that the bonding be performed until the stopping step. Therefore, as a heat-resistant adhesive tape, it not only prevents leakage of the sealing resin, but also does not hinder the high heat resistance that can withstand the mounting process of the semiconductor chip and the delicate operability in the wire bonding process. Characteristics that satisfy all of these steps are required.

【０００６】このような特性を有する耐熱性粘着テープ
としては、粘着剤が優れた耐熱性と適度な弾性率および
粘着力を有することが好ましいため、シリコーン系粘着
剤の使用が適切と考えられる。As the heat-resistant pressure-sensitive adhesive tape having such characteristics, it is preferable that the pressure-sensitive adhesive has excellent heat resistance and an appropriate elastic modulus and adhesive strength. Therefore, it is considered appropriate to use a silicone-based pressure-sensitive adhesive.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、シリコ
ーン系粘着剤を耐熱性粘着テープに使用すると、次によ
うな問題が生じることが判明した。即ち、耐熱性粘着テ
ープのシリコーン系粘着剤が、上記一連の工程後の剥離
の際に、アウターパッド部へ移行してその表面を汚染
し、その結果、半導体装置を実装基板にはんだ付けする
際に濡れ性不良が生じ、実装の歩留りが低下するという
問題が生じた。However, it has been found that the following problems occur when a silicone-based pressure-sensitive adhesive is used for a heat-resistant pressure-sensitive adhesive tape. That is, when the silicone-based pressure-sensitive adhesive of the heat-resistant pressure-sensitive adhesive tape is peeled off after the above-described series of steps, it migrates to the outer pad portion and contaminates the surface thereof. As a result, when the semiconductor device is soldered to the mounting substrate, This causes a problem that poor wettability occurs and the yield of mounting is reduced.

【０００８】一方、上記のリードフレームとしては、単
層構造の銅リードフレーム（以下Ｃｕ−Ｌ／Ｆという）
と、銅リードフレーム上にＮｉ（１．０μｍ），Ｐｄ
（０．１μｍ），Ａｕ（０．０１μｍ）が順次めっきさ
れた積層構造のＮｉ／Ｐｄ／フラッシュＡｕめっきリー
ドフレーム（以下Ｎｉ／Ｐｄ−Ｌ／Ｆという）とが代表
的であるが、Ｃｕ−Ｌ／Ｆでは耐熱性粘着テープを剥離
後、その剥離面を前処理してから電解はんだめっきし
て、実装基板にはんだ付けするのに対し、Ｎｉ／Ｐｄ−
Ｌ／Ｆでは耐熱性粘着テープを剥離後、そのまま実装基
板にはんだ付けするため、リードフレームの種類により
半導体装置の実装工程に違いがある。このため、リード
フレームの種類により、濡れ性不良を防止するためのア
ウターパッド部の清浄度が異なることが判明した。On the other hand, as the lead frame, a copper lead frame having a single layer structure (hereinafter referred to as Cu-L / F) is used.
And Ni (1.0 μm), Pd
(0.1 μm) and a Ni / Pd / flash Au plating lead frame (hereinafter referred to as Ni / Pd-L / F) having a laminated structure in which Au (0.01 μm) is sequentially plated. In the L / F, after the heat-resistant adhesive tape is peeled off, the peeled surface is pre-treated and then subjected to electrolytic solder plating and soldered to a mounting substrate, whereas Ni / Pd-
In the L / F, since the heat-resistant adhesive tape is peeled off and then directly soldered to the mounting substrate, the mounting process of the semiconductor device differs depending on the type of the lead frame. For this reason, it was found that the degree of cleanliness of the outer pad portion for preventing poor wettability differs depending on the type of the lead frame.

【０００９】そこで、本発明の目的は、耐熱性粘着テー
プにシリコーン系粘着剤を使用した場合でも、半導体装
置を実装する際に、はんだ付けの濡れ性が良好となる半
導体装置の実装方法、並びにそれに用いる半導体装置を
提供することにある。Therefore, an object of the present invention is to provide a method of mounting a semiconductor device which has good soldering wettability when mounting a semiconductor device even when a silicone-based pressure-sensitive adhesive is used for a heat-resistant pressure-sensitive adhesive tape. It is to provide a semiconductor device used for the same.

【００１０】[0010]

【課題を解決するための手段】本発明者らは、上記目的
を達成すべく、はんだ付けの濡れ性低下の原因やその対
策について鋭意研究したところ、実装プロセスに応じ
て、アウターパッドに付着する汚染物質の量を一定値以
下とすることにより、上記目的を達成できることを見出
し、本発明を完成するに至った。Means for Solving the Problems In order to achieve the above object, the present inventors have conducted intensive studies on the cause of the decrease in wettability of soldering and its countermeasures, and found that it adheres to the outer pad according to the mounting process. It has been found that the above object can be achieved by controlling the amount of contaminants to a certain value or less, and the present invention has been completed.

【００１１】即ち、本発明の半導体装置の実装方法は、
シリコーン系粘着剤に由来する汚染物質がアウターパッ
ドに付着し、その汚染物質の付着量が蛍光Ｘ線分析によ
るケイ素原子の付着量で２０ｍｇ／ｍ2 以下である半導
体装置を用いて、配線基板へのはんだ付けを行う工程を
含むことを特徴とする。ここで、蛍光Ｘ線分析によるケ
イ素原子の付着量は、実施例の測定方法により測定され
る値である。That is, the method of mounting a semiconductor device according to the present invention comprises:
A contaminant derived from a silicone-based adhesive adheres to the outer pad, and the amount of the contaminant is 20 mg / m 2 or less in terms of the amount of silicon atoms by X-ray fluorescence analysis. And a step of performing soldering. Here, the attached amount of silicon atoms by the fluorescent X-ray analysis is a value measured by the measuring method of the example.

【００１２】また、本発明の半導体装置の別の実装方法
は、シリコーン系粘着剤に由来する銅製のアウターパッ
ドに付着し、その汚染物質の付着量が蛍光Ｘ線分析によ
るケイ素原子の付着量で１００ｍｇ／ｍ2 以下である半
導体装置を用いて、そのアウターパッドを酸洗浄する工
程と、酸洗浄したアウターパッドをはんだメッキする工
程と、はんだメッキした半導体装置を配線基板へはんだ
付けする工程とを含むことを特徴とする。In another mounting method of the semiconductor device of the present invention, the amount of contaminants adhered to a copper outer pad derived from a silicone-based adhesive is determined by the amount of silicon atoms adhered by X-ray fluorescence analysis. Using a semiconductor device having a concentration of 100 mg / m 2 or less, pickling the outer pad with acid, solder plating the pickled outer pad, and soldering the solder-plated semiconductor device to the wiring board. It is characterized by including.

【００１３】上記において、前記半導体装置が、プラズ
マエッチング処理又はアルカリ電解処理により前記汚染
物質が洗浄されたものであることが好ましい。In the above, it is preferable that the semiconductor device is one in which the contaminants have been cleaned by plasma etching or alkaline electrolysis.

【００１４】また、前記半導体装置が、耐熱性粘着テー
プを貼り合わせた金属製のリードフレームのダイパッド
上に半導体チップをボンディングする搭載工程と、前記
リードフレームの端子部先端と前記半導体チップ上の電
極パッドとをボンディングワイヤで電気的に接続する結
線工程と、封止樹脂により半導体チップ側を片面封止す
る封止工程とを含み、前記リードフレームの温度を常に
２００℃以下に制御する製造方法によって製造されたも
のであることが好ましい。A mounting step of bonding the semiconductor chip to a die pad of a metal lead frame to which a heat-resistant adhesive tape is attached; and a step of connecting a tip of a terminal portion of the lead frame and an electrode on the semiconductor chip. The method includes a connection step of electrically connecting a pad with a bonding wire, and a sealing step of sealing the semiconductor chip side on one side with a sealing resin, and a manufacturing method for constantly controlling the temperature of the lead frame to 200 ° C. or lower. It is preferably manufactured.

【００１５】一方、本発明の半導体装置は、シリコーン
系粘着剤に由来する汚染物質がアウターパッドに付着
し、その汚染物質の付着量が蛍光Ｘ線分析によるケイ素
原子の付着量で２０ｍｇ／ｍ2 以下であることを特徴と
する。On the other hand, in the semiconductor device of the present invention, a contaminant derived from the silicone-based adhesive adheres to the outer pad, and the amount of the contaminant is 20 mg / m 2 as the amount of silicon atoms adhered by X-ray fluorescence analysis. It is characterized by the following.

【００１６】また、本発明の別の半導体装置は、シリコ
ーン系粘着剤に由来する汚染物質が銅製のアウターパッ
ドに付着し、その汚染物質の付着量が蛍光Ｘ線分析によ
るケイ素原子の付着量で１００ｍｇ／ｍ2 以下であるこ
とを特徴とする。In another semiconductor device according to the present invention, a contaminant derived from a silicone-based adhesive adheres to an outer pad made of copper, and the amount of the contaminant is determined by the amount of silicon atoms adhered by X-ray fluorescence analysis. It is characterized in that it is not more than 100 mg / m 2 .

【００１７】［作用効果］本発明の半導体装置の実装方
法によると、シリコーン系粘着剤に由来するアウターパ
ッドに付着した汚染物質の付着量が蛍光Ｘ線分析による
ケイ素原子の付着量で２０ｍｇ／ｍ2 以下である半導体
装置を用いて配線基板へのはんだ付けを行うため、実施
例の結果が示すように、はんだ付けの濡れ性が良好とな
り、実装の歩留りを高めることができる。According to the semiconductor device mounting method of the present invention, the amount of contaminants adhering to the outer pad derived from the silicone-based adhesive is 20 mg / m2 in terms of the amount of silicon atoms adhered by X-ray fluorescence analysis. Since soldering to a wiring board is performed using a semiconductor device of 2 or less, as shown in the results of the examples, the wettability of soldering is improved, and the yield of mounting can be increased.

【００１８】また、アウターパッドを酸洗浄する工程を
含む場合では、汚染物質の付着量が蛍光Ｘ線分析による
ケイ素原子の付着量で１００ｍｇ／ｍ2 以下である半導
体装置を用いるため、実施例の結果が示すように、はん
だ付けの濡れ性が良好となり、実装の歩留りを高めるこ
とができる。In the case where the step of washing the outer pad with an acid is included, a semiconductor device having an attached amount of contaminants of 100 mg / m 2 or less as an attached amount of silicon atoms by X-ray fluorescence analysis is used. As shown by the results, the wettability of soldering is improved, and the yield of mounting can be increased.

【００１９】前記半導体装置が、プラズマエッチング処
理又はアルカリ電解処理により前記汚染物質が洗浄され
たものである場合、比較的短時間で目的とする汚染物質
の付着量まで、アウターパッド表面を清浄化することが
でき、工業生産にも容易に適用できるようになる。If the semiconductor device has been cleaned of the contaminants by plasma etching or alkaline electrolysis, the outer pad surface is cleaned in a relatively short time until the desired amount of contaminants adheres. It can be easily applied to industrial production.

【００２０】また、前記半導体装置が、上記のような搭
載工程と結線工程と封止工程とを含み、前記リードフレ
ームの温度を常に２００℃以下に制御する製造方法によ
って製造されたものである場合、リードフレームの温度
が２００℃を超えないため、実施例の結果が示すよう
に、汚染物質の付着量を低減することで、はんだ付けの
濡れ性が良好となり、実装の歩留りを高めることができ
る。Further, in the case where the semiconductor device includes a mounting step, a wiring step, and a sealing step as described above, and is manufactured by a manufacturing method in which the temperature of the lead frame is always controlled to 200 ° C. or less. Since the temperature of the lead frame does not exceed 200 ° C., as shown in the results of the examples, by reducing the amount of adhered contaminants, the wettability of soldering is improved, and the yield of mounting can be increased. .

【００２１】一方、本発明の半導体装置によると、シリ
コーン系粘着剤に由来する汚染物質の付着量が蛍光Ｘ線
分析によるケイ素原子の付着量で２０ｍｇ／ｍ2 以下で
あるため、そのままはんだ付けを行う場合でも、上述の
ようにはんだ付けの濡れ性が良好となり、実装の歩留り
を高めることができる。On the other hand, according to the semiconductor device of the present invention, the amount of contaminants derived from the silicone-based pressure-sensitive adhesive is 20 mg / m 2 or less as the amount of silicon atoms adhered by X-ray fluorescence analysis. Even in the case of performing, as described above, the wettability of soldering is improved, and the yield of mounting can be increased.

【００２２】また、別の半導体装置によると、シリコー
ン系粘着剤に由来する汚染物質の付着量が蛍光Ｘ線分析
によるケイ素原子の付着量で１００ｍｇ／ｍ2 以下であ
り、銅製のアウターパッドでは酸化物除去のため酸洗浄
を行うのが通常のため、後のはんだメッキやハンダ付け
の際に、上述のようにはんだ付けの濡れ性が良好とな
り、実装の歩留りを高めることができる。According to another semiconductor device, the adhered amount of contaminants derived from the silicone-based adhesive is 100 mg / m 2 or less in terms of the adhered amount of silicon atoms by fluorescent X-ray analysis. Since acid cleaning is usually performed to remove the object, the wettability of soldering is improved during solder plating and soldering as described above, and the yield of mounting can be increased.

【００２３】[0023]

【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照しながら説明する。まず、本発明に用い
られる半導体装置の製造方法について説明する。図１
は、当該半導体装置の製造方法の一例を示す工程図であ
る。Embodiments of the present invention will be described below with reference to the drawings. First, a method for manufacturing a semiconductor device used in the present invention will be described. FIG.
FIG. 4 is a process diagram showing an example of a method for manufacturing the semiconductor device.

【００２４】本発明に用いられる半導体装置の製造方法
は、図１（ａ）〜（ｅ）に示すように、半導体チップ１
５の搭載工程と、ボンディングワイヤ１６による結線工
程と、封止樹脂１７による封止工程と、封止された構造
物２１を切断する切断工程とを少なくとも含むものであ
る。As shown in FIGS. 1A to 1E, the method of manufacturing a semiconductor device used in the present invention is as follows.
5, a connection step using a bonding wire 16, a sealing step using a sealing resin 17, and a cutting step for cutting the sealed structure 21.

【００２５】搭載工程は、図１（ａ）〜（ｂ）に示すよ
うに、アウターパッド側（図の下側）に耐熱性粘着テー
プ２０を貼り合わせた金属製のリードフレーム１０のダ
イパッド１１ｃ上に半導体チップ１５をボンディングす
る工程である。As shown in FIGS. 1 (a) and 1 (b), the mounting step is performed on a die pad 11c of a metal lead frame 10 in which a heat-resistant adhesive tape 20 is bonded to the outer pad side (the lower side in the figure). This is a step of bonding the semiconductor chip 15 to the substrate.

【００２６】リードフレーム１０とは、例えば銅などの
金属を素材としてＱＦＮの端子パターンが刻まれたもの
であり、その電気接点部分には、銀，ニッケル，パラジ
ウム，金などのなどの素材で被覆（めっき）されている
場合もある。リードフレーム１０の厚みは、１００〜３
００μｍが一般的である。The lead frame 10 is formed by engraving a QFN terminal pattern using a metal such as copper as a material, and its electrical contact portions are covered with a material such as silver, nickel, palladium, gold or the like. (Plated) in some cases. The thickness of the lead frame 10 is 100 to 3
00 μm is common.

【００２７】リードフレーム１０は、後の切断工程にて
切り分けやすいよう、個々のＱＦＮの配置パターンが整
然と並べられているものが好ましい。例えば図２に示す
ように、リードフレーム１０上に縦横のマトリックス状
に配列された形状などは、マトリックスＱＦＮあるいは
ＭＡＰ−ＱＦＮなどと呼ばれ、もっとも好ましいリード
フレーム形状のひとつである。The lead frame 10 is preferably one in which the arrangement patterns of the individual QFNs are arranged neatly so that the lead frame 10 can be easily separated in a later cutting step. For example, as shown in FIG. 2, a shape arranged in a vertical and horizontal matrix on the lead frame 10 is called a matrix QFN or MAP-QFN, and is one of the most preferable lead frame shapes.

【００２８】図２（ａ）〜（ｂ）に示すように、リード
フレーム１０のパッケージパターン領域１１には、隣接
した複数の開口１１ａに端子部１１ｂを複数配列した、
ＱＦＮの基板デザインが整然と配列されている。一般的
なＱＦＮの場合、各々の基板デザイン（図２（ａ）の格
子で区分された領域）は、開口１１ａの周囲に配列れさ
た、アウターリード面を下側に有する端子部１１ｂと、
開口１１ａの中央に配置されるダイパッド１１ｃと、ダ
イパッド１１ｃを開口１１ａの４角に支持させるダイバ
ー１１ｄとで構成される。As shown in FIGS. 2A and 2B, in the package pattern region 11 of the lead frame 10, a plurality of terminals 11b are arranged in a plurality of adjacent openings 11a.
The QFN board design is neatly arranged. In the case of a general QFN, each of the board designs (regions divided by the lattice in FIG. 2A) includes a terminal portion 11b having an outer lead surface on the lower side, which is arranged around the opening 11a.
It comprises a die pad 11c arranged at the center of the opening 11a, and a diver 11d for supporting the die pad 11c at four corners of the opening 11a.

【００２９】耐熱性粘着テープ２０は、少なくともパッ
ケージパターン領域１１より外側に貼着され、樹脂封止
される樹脂封止領域の外側の全周を含む領域に貼着する
のが好ましい。リードフレーム１０は、通常、樹脂封止
時の位置決めを行うための、ガイドピン用孔１３を端辺
近傍に有しており、それを塞がない領域に貼着するのが
好ましい。また、樹脂封止領域はリードフレーム１０の
長手方向に複数配置されるため、それらの複数領域を渡
るように連続して粘着テープ２０を貼着するのが好まし
い。The heat-resistant pressure-sensitive adhesive tape 20 is adhered at least outside the package pattern region 11 and is preferably adhered to a region including the entire periphery outside the resin-sealed region to be resin-sealed. Normally, the lead frame 10 has a guide pin hole 13 near the end side for positioning at the time of resin sealing, and it is preferable that the lead frame 10 is adhered to a region where the hole is not closed. In addition, since a plurality of resin sealing regions are arranged in the longitudinal direction of the lead frame 10, it is preferable that the adhesive tape 20 be continuously applied so as to extend over the plurality of regions.

【００３０】上記のようなリードフレーム１０上に、半
導体チップ１５、すなわち半導体集積回路部分であるシ
リコンウエハ・チップが搭載される。リードフレーム１
０上にはこの半導体チップ１５を固定するためダイパッ
ド１１ｃと呼ばれる固定エリアが設けられており、この
ダイパッド１１ｃヘのボンディング（固定）の方法は導
電性ペースト１９を使用したり、接着テープ、接着剤な
ど各種の方法が用いられる。導電性ペーストや熱硬化性
の接着剤等を用いてダイボンドする場合、一般的に１５
０〜２００℃程度の温度で３０分〜９０分程度加熱キュ
アする。On the above-described lead frame 10, a semiconductor chip 15, that is, a silicon wafer chip which is a semiconductor integrated circuit portion is mounted. Lead frame 1
A fixing area called a die pad 11c for fixing the semiconductor chip 15 is provided on the semiconductor chip 15, and a method of bonding (fixing) to the die pad 11c uses a conductive paste 19, an adhesive tape, an adhesive, or the like. Various methods are used. In the case of die bonding using a conductive paste or a thermosetting adhesive, generally, 15
Heat and cure at a temperature of about 0 to 200 ° C. for about 30 to 90 minutes.

【００３１】結線工程は、図１（ｃ）に示すように、リ
ードフレーム１０の端子部１１ｂ（インナーリード）の
先端と半導体チップ１５上の電極パッド１５ａとをボン
ディングワイヤ１６で電気的に接続する工程である。ボ
ンディングワイヤ１６としては、例えば金線あるいはア
ルミ線などが用いられる。一般的には１６０〜２３０℃
に加熱された状態で、超音波による振動エネルギーと印
加加圧による圧着エネルギーの併用により結線される。
その際、リードフレーム１０に貼着した耐熱性粘着テー
プ２０面を真空吸引することで、ヒートブロックに確実
に固定することができる。In the connection step, as shown in FIG. 1C, the tip of the terminal portion 11b (inner lead) of the lead frame 10 and the electrode pad 15a on the semiconductor chip 15 are electrically connected by the bonding wire 16. It is a process. For example, a gold wire or an aluminum wire is used as the bonding wire 16. Generally 160-230 ° C
In this state, the wires are connected by the combined use of vibration energy by ultrasonic waves and compression energy by applied pressure.
At this time, the surface of the heat-resistant adhesive tape 20 attached to the lead frame 10 can be reliably fixed to the heat block by vacuum suction.

【００３２】封止工程は、図１（ｄ）に示すように、封
止樹脂１７により半導体チップ側を片面封止する工程で
ある。封止工程は、リードフレーム１０に搭載された半
導体チップ１５やボンディングワイヤ１６を保護するた
めに行われ、とくにエポキシ系の樹脂をはじめとした封
止樹脂１７を用いて金型中で成型されるのが代表的であ
る。その際、図３に示すように、複数のキャビティを有
する上金型１８ａと下金型１８ｂからなる金型１８を用
いて、複数の封止樹脂１７にて同時に封止工程が行われ
るのが一般的である。具体的には、例えば樹脂封止時の
加熱温度は１７０〜１８０℃であり、この温度で数分間
キュアされた後、更に、ポストモールドキュアが数時間
行われる。なお、耐熱性粘着テープ２０はポストモール
ドキュアの前に剥離するのが好ましい。In the sealing step, as shown in FIG. 1D, the semiconductor chip side is sealed on one side with a sealing resin 17. The sealing step is performed to protect the semiconductor chip 15 and the bonding wires 16 mounted on the lead frame 10 and is molded in a mold using a sealing resin 17 such as an epoxy resin. Is typical. At this time, as shown in FIG. 3, a sealing step is performed simultaneously with a plurality of sealing resins 17 using a mold 18 including an upper mold 18a and a lower mold 18b having a plurality of cavities. General. Specifically, for example, the heating temperature at the time of resin sealing is 170 to 180 ° C. After curing at this temperature for several minutes, post-mold curing is further performed for several hours. Preferably, the heat-resistant adhesive tape 20 is peeled off before the post-mold cure.

【００３３】切断工程は、図１（ｅ）に示すように、封
止された構造物２１を個別の半導体装置２１ａに切断す
る工程である。一般的にはダイサーなどの回転切断刃を
用いて封止樹脂１７の切断部１７ａをカットする切断工
程が挙げられる。なお、１つの半導体チップ１５に対し
て、１つのキャビティを複数有する上金型１８ａを使用
する場合、切断工程は不要となる。The cutting step is a step of cutting the sealed structure 21 into individual semiconductor devices 21a as shown in FIG. In general, a cutting step of cutting the cut portion 17a of the sealing resin 17 using a rotary cutting blade such as a dicer is exemplified. When the upper die 18a having a plurality of cavities is used for one semiconductor chip 15, a cutting step is not required.

【００３４】上述のような製造工程に用いられる耐熱性
粘着テープ２０は基材層と粘着剤層とから通常構成され
るが、前述の製造工程における加熱条件に対して、これ
らの耐熱性を満足する耐熱性粘着テープであることが好
ましい。The heat-resistant pressure-sensitive adhesive tape 20 used in the above-mentioned manufacturing process is usually composed of a base material layer and an adhesive layer, but satisfies these heat resistances with respect to the heating conditions in the above-mentioned manufacturing process. It is preferably a heat-resistant pressure-sensitive adhesive tape.

【００３５】上記の基材層としては、アルミなどの金属
箔や各種の耐熱性樹脂シート等が挙げられるが、ポリイ
ミドが加工性やハンドリング性も高く、もっとも好まし
い素材のひとつである。耐熱性粘着テープ２０の基材層
の厚みは、折れや裂けを防止し、好適なハンドリング性
に鑑みて５〜２５０μｍが好ましい。Examples of the base material layer include metal foils such as aluminum and various heat-resistant resin sheets. Polyimide is one of the most preferable materials because of its high workability and handleability. The thickness of the base layer of the heat-resistant pressure-sensitive adhesive tape 20 is preferably from 5 to 250 μm in consideration of suitable handling properties to prevent breakage and tearing.

【００３６】また、粘着テープ２０を構成する粘着剤層
としては、優れた耐熱性と適度な弾性率および粘着力を
有するシリコーン系粘着剤を用いるのが好ましい。ま
た、粘着剤層が更に酸化防止剤を含有してよもい。当該
酸化防止剤としては、例えばヒンダートフェノール系酸
化防止剤、燐系酸化防止剤、ラクトン系酸化防止剤等が
挙げられ、これらは単体または組み合わせて使用でき
る。As the pressure-sensitive adhesive layer constituting the pressure-sensitive adhesive tape 20, it is preferable to use a silicone-based pressure-sensitive adhesive having excellent heat resistance, an appropriate elastic modulus and adhesive strength. Further, the pressure-sensitive adhesive layer may further contain an antioxidant. Examples of the antioxidant include a hindered phenol antioxidant, a phosphorus antioxidant, a lactone antioxidant, and the like, and these can be used alone or in combination.

【００３７】シリコーン系粘着剤としては、ジメチルシ
ロキサン、あるいはそのメチル基の一部をフェニル基で
置換したものなどを主体とする公知のシリコーン系粘着
剤を用いることができる。粘着層は架橋構造とすること
が一般的でありその場合、過酸化物等による適宜な架橋
方式を採ることができるが、シリコーン系粘着剤中に予
めＳi −ＣＨ＝ＣＨ2 基やＳi −Ｈ基を導入しておいて
白金系触媒で付加反応させる架橋方式が好ましい。ま
た、接着性を調整するために、カーボニッケル等のフィ
ラー類等を添加してもよい。As the silicone-based pressure-sensitive adhesive, a known silicone-based pressure-sensitive adhesive mainly composed of dimethylsiloxane or a substance in which a part of the methyl group is substituted with a phenyl group can be used. The pressure-sensitive adhesive layer generally has a cross-linked structure. In this case, an appropriate cross-linking method using a peroxide or the like can be adopted. However, a Si-CH = CH 2 group or a Si-H A crosslinking method in which a group is introduced and an addition reaction is performed with a platinum-based catalyst is preferable. Further, fillers such as carbon nickel may be added to adjust the adhesiveness.

【００３８】以上のような半導体装置の製造方法におい
ては、その加熱履歴にもよるが、耐熱性粘着テープのシ
リコーン系粘着剤が、上記一連の工程後の剥離の際に、
アウターパッド部へ移行してその表面を汚染し、その結
果、半導体装置を実装基板にはんだ付けする際に濡れ性
不良が生じ易い。本発明では、これを解消すべく、アウ
ターパッド部の粘着剤移行汚染によるはんだ付け濡れ性
不良を防ぐための判定基準を明確にし、その判定基準を
クリアーする方法として、付着した汚染物の除去方法お
よび改善された半導体製造方法（工程条件）を例示す
る。In the method of manufacturing a semiconductor device as described above, depending on the heating history, the silicone-based pressure-sensitive adhesive of the heat-resistant pressure-sensitive adhesive tape may be peeled off after the above series of steps.
It migrates to the outer pad portion and contaminates its surface, and as a result, poor wettability tends to occur when the semiconductor device is soldered to the mounting board. In the present invention, in order to solve this, a criterion for preventing poor soldering wettability due to adhesive transfer contamination of the outer pad portion is clarified, and as a method of clearing the criterion, a method of removing adhered contaminants is used. And an improved semiconductor manufacturing method (process conditions).

【００３９】はんだ濡れ性不良の判定基準としては、蛍
光Ｘ線分析法（ＸＲＦ）を用いたＳｉ付着量を採用す
る。即ち、モールド樹脂により半導体チップ側を片面封
止後、耐熱性粘着テープをリードフレームから剥離後、
リードフレームの表面上に残った（付着した）シリコー
ン系粘着剤は、Ｓｉ原子の付着量（ｍｇ／ｍ2 ）として
蛍光Ｘ線分析装置（ＸＲＦ；Ｘ−ｒａｙ Ｆｌｕｏｒｅ
ｓｃｅｎｃｅ Ｓｐｅｃｔｒｏｍｅｔｅｒ）を用いて測
定できる。As a criterion for judging poor solder wettability, the amount of Si deposited using X-ray fluorescence analysis (XRF) is employed. That is, after sealing the semiconductor chip side on one side with mold resin, peeling off the heat-resistant adhesive tape from the lead frame,
The silicone adhesive remaining on (adhered to) the surface of the lead frame is converted into an X-ray Fluorescence analyzer (XRF; X-ray Fluore) as an attached amount of Si atoms (mg / m 2 ).
Spectrometer).

【００４０】銅リードフレーム（Ｃｕ−Ｌ／Ｆ）に対し
ては、リードフレームアウターパッド上のＳｉ付着量が
１００ｍｇ／ｍ2 以下の場合に良好なはんだ濡れ性を得
ることができる。１００ｍｇ／ｍ2 を超える場合は、酸
洗いによる電解はんだめっき前処理にてＣｕ−Ｌ／Ｆ上
に付着したシリコーン粘着剤（Ｓｉ）を除去できず、シ
リコーン粘着剤とＣｕ酸化皮膜がともにリードフレーム
アウターパッド上に残存するため、はんだ濡れ性を阻害
する。For a copper lead frame (Cu-L / F), good solder wettability can be obtained when the amount of Si deposited on the lead frame outer pad is 100 mg / m 2 or less. If it exceeds 100 mg / m 2 , the silicone adhesive (Si) adhered on the Cu-L / F cannot be removed by the pretreatment of electrolytic solder plating by pickling, and both the silicone adhesive and the Cu oxide film are lead frames. Since it remains on the outer pad, it impairs solder wettability.

【００４１】一方、銅リードフレーム上にＮｉ，Ｐｄ，
Ａｕが順次めっきされた積層構造のＮｉ／Ｐｄ／フラッ
シュＡｕめっきリードフレーム（Ｎｉ／Ｐｄ−Ｌ／Ｆ）
に対しては、リードフレームアウターパッド上のＳｉ検
出量が２０ｍｇ／ｍ2 以下の場合に良好なはんだ濡れ性
を得ることができる。２０ｍｇ／ｍ2 を超える場合は、
リードフレームアウターパッド上に付着したシリコーン
粘着剤が、はんだ濡れ性を阻害する。On the other hand, Ni, Pd,
Ni / Pd / flash Au-plated lead frame (Ni / Pd-L / F) with a laminated structure in which Au is sequentially plated
In contrast, when the amount of Si detected on the outer lead frame pad is 20 mg / m 2 or less, good solder wettability can be obtained. If it exceeds 20 mg / m 2 ,
The silicone adhesive adhered on the outer lead frame pad inhibits solder wettability.

【００４２】Ｃｕ−Ｌ／Ｆでは耐熱性粘着テープを剥離
後、その剥離面を前処理〜電解はんだめっきして、実装
基板に付けするのに対し、Ｎｉ／Ｐｄ−Ｌ／Ｆ では耐
熱性粘着テープを剥離後、そのまま実装基板にはんだ付
けされるため、判定基準となるＳｉ付着量にも違いが生
じる。In the case of Cu-L / F, after peeling off the heat-resistant adhesive tape, the peeled surface is subjected to pretreatment or electrolytic solder plating, and is attached to a mounting board, whereas in the case of Ni / Pd-L / F, the heat-resistant adhesive tape is peeled off. After the tape is peeled off, it is soldered to the mounting substrate as it is, so that the amount of Si adhered as a criterion differs.

【００４３】従って、本発明の半導体装置の実装方法
は、シリコーン系粘着剤に由来する汚染物質がアウター
パッドに付着し、その汚染物質の付着量が蛍光Ｘ線分析
によるケイ素原子の付着量で２０ｍｇ／ｍ2 以下である
半導体装置を用いて、配線基板へのはんだ付けを行う工
程を含むものである。また、シリコーン系粘着剤に由来
する汚染物質が銅製のアウターパッドに付着し、その汚
染物質の付着量が蛍光Ｘ線分析によるケイ素原子の付着
量で１００ｍｇ／ｍ2 以下である半導体装置を用いて、
そのアウターパッドを酸洗浄する工程と、酸洗浄したア
ウターパッドをはんだメッキする工程と、はんだメッキ
した半導体装置を配線基板へはんだ付けする工程とを含
むものである。更に、本発明の半導体装置は、上記の如
きケイ素原子の付着量を有する半導体装置である。Therefore, in the method of mounting a semiconductor device according to the present invention, the contaminant derived from the silicone adhesive adheres to the outer pad, and the amount of the contaminant is 20 mg as the amount of silicon atoms adhered by X-ray fluorescence analysis. / M 2 or less, including a step of soldering to a wiring board using a semiconductor device having a capacity of / m 2 or less. In addition, using a semiconductor device in which a contaminant derived from a silicone-based adhesive adheres to an outer pad made of copper and the amount of the contaminant is 100 mg / m 2 or less in terms of the amount of silicon atoms by fluorescent X-ray analysis. ,
The method includes a step of acid cleaning the outer pad, a step of solder plating the outer pad that has been acid cleaned, and a step of soldering the solder-plated semiconductor device to a wiring board. Further, the semiconductor device of the present invention is a semiconductor device having the above-mentioned amount of silicon atoms attached.

【００４４】上記のような半導体装置を得るには、その
製造後にアウターパッドに付着した汚染物質を上記の判
定基準以下まで洗浄するか、或いは製造工程において付
着する汚染物質を上記の判定基準以下とする必要があ
る。In order to obtain the semiconductor device as described above, the contaminants adhering to the outer pad after its manufacture are washed to the above-mentioned criteria or the contaminants adhering in the manufacturing process are reduced to the above-mentioned criteria or less. There is a need to.

【００４５】製造後にアウターパッドに付着した汚染物
質を洗浄する方法としては、乾式処理方法でも湿式処理
方法でもよく、例えばプラズマエッチング処理、スパッ
タエッチング処理、アルカリ洗浄、溶剤による洗浄、酸
による洗浄、又はアルカリ電解処理等が挙げられる。な
かでも、プラズマエッチング処理、又はアルカリ電解処
理が好ましい。The method of cleaning contaminants adhering to the outer pad after manufacturing may be a dry processing method or a wet processing method, for example, plasma etching, sputter etching, alkali cleaning, cleaning with a solvent, cleaning with an acid, or Alkali electrolytic treatment and the like can be mentioned. Among them, a plasma etching treatment or an alkaline electrolytic treatment is preferable.

【００４６】乾式処理方法としては、酸素やアルゴンガ
ス又は水素ガスあるいはその混合ガスを用いたプラズマ
エッチング処理が有効である。一般的にＡｒプラズマは
電子衝突による熱エネルギーとイオン衝突による物理エ
ネルギーにより対象物表面の有機物を除去できる。本法
は対象材質の限定が少ないため、乾式クリーニング法と
して広く用いられている。また、一般的にＯ2 プラズマ
は酸化ラジカルによる酸化反応エネルギーにより対象物
表面の有機物を除去できる。本法は特に酸化されない材
質で、はんだを含む場合などに適用される。As a dry treatment method, a plasma etching treatment using oxygen, argon gas, hydrogen gas or a mixed gas thereof is effective. In general, Ar plasma can remove organic matter on the surface of an object using thermal energy due to electron collision and physical energy due to ion collision. This method is widely used as a dry cleaning method because there are few limitations on the target material. In general, O 2 plasma can remove organic substances on the surface of an object by the energy of an oxidation reaction caused by oxidation radicals. This method is particularly applicable to materials that do not oxidize and contain solder.

【００４７】湿式処理としては、リードフレームアウタ
ーパッド上に移行したシリコーン系粘着剤は、アルカリ
溶液に溶けやすいので、アルカリ溶液への浸漬で除去可
能であるが、浸漬時間を１時間程度必要とし、工業生産
には適用できにくい。それに対して、アルカリ電解処理
は、電解時に発生する水素ガスを利用して、リードフレ
ームアウターパッド表面の粘着剤層を除去するので、１
〜５分程度の短時間で除去可能なので、工業生産に容易
に適用することができる。アルカリ電解処理では、アウ
ターパッドを一方の電極とするため、ダイシング前のリ
ードフレームが接続された状態でアルカリ電解処理を行
うのが好ましい。In the wet treatment, the silicone-based pressure-sensitive adhesive that has migrated onto the lead frame outer pad can be easily removed by immersion in an alkaline solution because it is easily dissolved in an alkaline solution. It is difficult to apply to industrial production. On the other hand, the alkaline electrolysis treatment uses hydrogen gas generated during electrolysis to remove the adhesive layer on the outer surface of the lead frame outer pad.
Since it can be removed in a short time of about 5 minutes, it can be easily applied to industrial production. In the alkaline electrolysis, since the outer pad is used as one electrode, it is preferable to perform the alkaline electrolysis with the lead frame before dicing connected.

【００４８】製造工程において付着する汚染物質を上記
の判定基準以下とするための製造方法としては、Ｃｕ−
Ｌ／Ｆ、Ｎｉ／Ｐｄ−Ｌ／Ｆともに製造履歴における量
大加熱温度を２００℃以下とすることによって、実現す
ることができる。２００℃を越えた最大加熱温度履歴を
受けると、リードフレームアウターパッド上のＳｉ付着
量を、ＣｕＬ／Ｆでは１００ｍｇ／ｍ2 以下、Ｎｉ／Ｐ
ｄ Ｌ／Ｆでは２０ｍｇ／ｍ2 以下とすることができ
ず、はんだ濡れ性不良をきたす。As a manufacturing method for controlling the amount of contaminants adhering in the manufacturing process to the above-mentioned criteria, Cu-
Both L / F and Ni / Pd-L / F can be realized by setting the large heating temperature in the manufacturing history to 200 ° C. or less. When a maximum heating temperature history exceeding 200 ° C. is received, the amount of Si deposited on the outer lead pad of the lead frame is reduced to 100 mg / m 2 or less for CuL / F, Ni / P
d L / F cannot be less than 20 mg / m 2 , resulting in poor solder wettability.

【００４９】本発明において、銅製のリードフレーム
（アウターパッド）を使用する場合のアウターパッドを
酸洗浄する工程としては、はんだメッキ前に行われる一
般的な酸洗浄を想定している。例えば、下記の表１の順
序１〜４のような工程や、表２の順序１〜４のような工
程等が例示される。In the present invention, as the step of acid cleaning the outer pad when a copper lead frame (outer pad) is used, general acid cleaning performed before solder plating is assumed. For example, steps such as steps 1 to 4 in Table 1 below and steps such as steps 1 to 4 in Table 2 are exemplified.

【００５０】また、酸洗浄したアウターパッドをはんだ
メッキする工程としては、一般的な電解はんだメッキを
想定している。例えば、下記の表１の順序５〜６のよう
な工程や、表２の順序５〜６のような工程等が例示され
る。The process of solder plating the acid-washed outer pad is assumed to be general electrolytic solder plating. For example, steps such as steps 5 to 6 in Table 1 below and steps such as steps 5 to 6 in Table 2 are exemplified.

【００５１】[0051]

【表１】 表中の試薬類は全て日本マクダーミッド（株）製のもの
である。[Table 1] All the reagents in the table are manufactured by McDermid Japan.

【００５２】[0052]

【表２】 表中の試薬類は全て奥野製薬（株）製のものである。[Table 2] All the reagents in the table are manufactured by Okuno Pharmaceutical Co., Ltd.

【００５３】本発明において、直接、又ははんだメッキ
した後に、半導体装置を配線基板へはんだ付けする工程
としては、リフローソルダリング等による各種の表面実
装方法が何れも採用できる。例えば、配線基板へソルダ
ーペーストを印刷後、接着剤等を介して半導体装置を配
線基板へ装着し、加熱によるリフローソルダリングにて
はんだ付けを行う工程が一般的である。In the present invention, any of various surface mounting methods such as reflow soldering can be adopted as the step of soldering the semiconductor device to the wiring board directly or after plating the solder. For example, it is common to print a solder paste on a wiring board, mount the semiconductor device on the wiring board via an adhesive or the like, and perform soldering by reflow soldering by heating.

【００５４】使用されるはんだとしては、Ｓｎ−Ｐｂ
系、Ｓｎ−Ａｇ系、Ｓｎ−Ｃｕ系、Ｓｎ−Ｂｉ系、Ｓｎ
−Ｚｎ系の２元素あるいは上記元素の３元素が挙げられ
る。The solder used is Sn-Pb
System, Sn-Ag system, Sn-Cu system, Sn-Bi system, Sn
—Zn-based two elements or three of the above elements.

【００５５】[0055]

【実施例】以下、本発明の構成と効果を具体的に示す実
施例等について説明する。なお、実施例等におけるケイ
素原子の付着量や評価データ等は、次のようにして測定
したものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments and the like specifically showing the configuration and effects of the present invention will be described below. In addition, the attached amount of silicon atoms, evaluation data, and the like in Examples and the like were measured as follows.

【００５６】（１）ケイ素原子の付着量 蛍光Ｘ線強度は目的元素の含有率に比例するが、発生し
たＸ線は共存元素の吸収または励起（マトリックス）に
より影響をうける。目的元素の含有率を精度良く分析す
るためには、マトリックスの影響を補正する必要があ
る。(1) Attachment amount of silicon atom The fluorescent X-ray intensity is proportional to the content of the target element, but the generated X-ray is affected by the absorption or excitation (matrix) of the coexisting element. In order to accurately analyze the content of the target element, it is necessary to correct the influence of the matrix.

【００５７】ファンダメンタルパラメーター法は、マト
リックスの影響を理論的に補正して目的元素の蛍光Ｘ線
強度を自動算出する方法である。ファンダメンタルパラ
メーター法では質量吸収係数・蛍光収率・Ｘ線源のスペ
クトル分布などの物理定数（ファンダメンタルパラメー
ター）を用いて、蛍光Ｘ線強度の理論式から理論Ｘ線強
度を求め、測定Ｘ線強度との対比を行って含有率が算出
される。そのため検量線法と異なり、標準試料は分析試
料マトリックスが同じである必要はなく、各成分含有率
の正しくわかった標準試料（一種類で良い）を用いて理
論強度と測定強度から装置定数（装置感度）を求め、目
的元素の含有率およびＸ線強度を算出できる。標準試料
にはＳｉＯ2 （理学製Ｓｔａｎｄａｒｄ Ｓａｍｐｌｅ
Ｎｏ，３５９０）を用いた。The fundamental parameter method is a method of automatically calculating the fluorescent X-ray intensity of the target element by theoretically correcting the influence of the matrix. In the fundamental parameter method, the theoretical X-ray intensity is calculated from the theoretical formula of the fluorescent X-ray intensity using physical constants (fundamental parameters) such as mass absorption coefficient, fluorescence yield, and spectral distribution of the X-ray source. The content ratio is calculated by comparing. Therefore, unlike the calibration curve method, the standard sample does not need to have the same analytical sample matrix. Sensitivity) and the content of the target element and the X-ray intensity can be calculated. The standard sample is SiO 2 (Rigaku Standard Sample)
No. 3590) was used.

【００５８】分析する試料がバルク試料である場合、得
られる定量分析値は含有率であるが、ある基板上に形成
された薄膜である場合には薄膜の付着量（ｍｇ／ｍ2 ）
も求まる。リードフレーム上に付着したシリコーン粘着
剤を薄膜とみなし、理学電機工業（株）製ＲＩＸ２００
０を用い下記条件にてＳｉ−Ｋαスペクトルのピーク高
さよりリードフレーム上に付着したＳｉ原子の量を測定
した。When the sample to be analyzed is a bulk sample, the quantitative analysis value obtained is the content, but when the sample is a thin film formed on a certain substrate, the amount of the thin film attached (mg / m 2 )
Is also found. The silicone adhesive adhered on the lead frame is regarded as a thin film, and Rig200 manufactured by Rigaku Denki Kogyo Co., Ltd.
Using 0, the amount of Si atoms attached to the lead frame was measured from the peak height of the Si-Kα spectrum under the following conditions.

【００５９】 ・装置 ：理学電機工業（株）製、ＲＩＸ２０００ ・Ｘ線源 ：Ｒｈ ・測定スペクトル ：Ｓｉ−Ｋα ・管電圧 ：５０ｋＶ ・管電流 ：５０ｍＡ ・スリット ：ＣＯＡＲＳＥ ・分光結晶 ：ＲＸ４ ・測定面積 ：５ｍｍφ ・ピーク位置（２θ）：１４４．７ｄｅｇ ・ピーク位置（２θ）：１４６．７ｄｅｇ ・積算時間 ：４０秒／サンプル （２）メニスコグラフ法を用いたはんだ濡れ性評価 メニスコグラフ法（別名：はんだ槽平衡法：日本電子機
械工業会規格ＥＩＡＪＥＴ−７４０１，「平衡法による
表面実装部品のはんだ付け性試験方法」）ははんだの濡
れ過程を定量的に測定でき、またはんだ付け性試験のみ
ならず濡れ現象の解析にも応用できるため、各種部品の
はんだ濡れ性やフラックスの性能評価等に広く用いられ
ている。• Apparatus: RIX2000, manufactured by Rigaku Corporation • X-ray source: Rh • Measurement spectrum: Si-Kα • Tube voltage: 50 kV • Tube current: 50 mA • Slit: COARSE • Spectral crystal: RX4 • Measurement area : 5mmφ ・ Peak position (2θ): 144.7 deg ・ Peak position (2θ): 146.7 deg ・ Integration time: 40 seconds / sample (2) Evaluation of solder wettability using meniscograph method Method: EIAJET-7401, "Electronic Industries Association of Japan Standard," Method of Testing Solderability of Surface Mounted Components by Balance Method ") can quantitatively measure the wetting process of solder, Since it can be applied to analysis, it is widely used for evaluation of solder wettability and flux performance of various components.

【００６０】その原理は、溶融はんだ中へ濡れ性を評価
したい試験片を垂直に浸漬し、試験片に作用する力の時
間変化（濡れ曲線）をエレクトロバランスセンサ（電子
天秤）により連続的に検出する。この際、はんだ濡れ性
指標には濡れ力および濡れ時間がある。濡れ力は、浸漬
開始から引き上げ直前までに基板に作用した力の最大値
（最大濡れ力：Ｆｍａｘ）とし、濡れ時間は浸漬開始か
ら（２／３）Ｆｍａｘに達するまでの時間とした。図４
にメニスコグラフ法濡れ曲線の代表例を示す。このとき
濡れ力は値が大きいほど、濡れ時間は短いほどはんだ濡
れ性は良いと判断される。（株）マルコム製ＳＰ−２を
用い、下記条件にてメニスコグラフ法評価を行い、得ら
れる濡れ力、濡れ時間の値にてはんだ濡れ性を評価す
る。The principle is that a test piece whose wettability is to be evaluated is vertically immersed in molten solder, and the time change (wet curve) of the force acting on the test piece is continuously detected by an electrobalance sensor (electronic balance). I do. At this time, the solder wettability index includes a wetting force and a wetting time. The wetting force was a maximum value (maximum wetting force: Fmax) of the force applied to the substrate from the start of the immersion to immediately before the lifting, and the wetting time was a time from the start of the immersion to reach (2/3) Fmax. FIG.
Shows a typical example of a meniscograph wetting curve. At this time, it is judged that the larger the value of the wetting force and the shorter the wetting time, the better the solder wettability. Using SP-2 manufactured by Malcolm Co., Ltd., the evaluation by the meniscograph method is performed under the following conditions, and the solder wettability is evaluated by the obtained values of the wetting force and the wetting time.

【００６１】この試験法を用いて求めた単位長さあたり
の濡れ力Ｆｍａｘが０．７ｍＮ／ｍｍ以上で、かつ２／
３Ｆ ｍａｘまでの濡れ時間Ｔが１．０Ｓ以下の場合に
良好なはんだ濡れ性を得ることができる。濡れ力Ｆｍａ
ｘが０．７ｍＮ／ｍｍ以下で、かつ２／３Ｆｍａｘまで
の濡れ時間Ｔ１が１．０Ｓ以上の場合は、転写・移行し
たＳｉがはんだ濡れ性を阻害する。The wetting force per unit length Fmax obtained by using this test method is 0.7 mN / mm or more, and 2 /
When the wetting time T up to 3F max is 1.0 S or less, good solder wettability can be obtained. Wetting power Fma
When x is 0.7 mN / mm or less and the wetting time T1 up to 2/3 Fmax is 1.0 S or more, the transferred and transferred Si inhibits solder wettability.

【００６２】 ・装置 ：（株）マルコム製、型式ＳＰ−２ ・はんだ浴組成 ：Ｓｎ６０ｗｔ％／Ｐｂ４０ｗｔ％共晶はんだ ・フラックス ：ＲＭＡタイプ ・浸漬速度 ：５［ｍｍ／ｍｉｎ］ ・引き離し速度 ：５［ｍｍ／ｍｉｎ］ ・浸漬深さ ：０．５［ｍｍ］ ・浸漬時間 ：１０［ｓ］ ・はんだ浴温度 ：２３５［℃］ ・試験片寸法 ：５ｍｍ幅×８ｍｍ長さ （参考製造例１）２５μｍ厚のポリイミドフィルム（東
レデュポン製カプトン１００Ｈ）を基材として、シリコ
ーン系粘着剤（東レダウコーニング製ＳＤ−４５８７
Ｌ）を用いた厚さ５μｍの粘着剤層を設けた耐熱性粘着
テープを作成した。この耐熱性粘着テープを、端子部に
一辺１６ＰｉｎタイプのＱＦＮが４個×４個に配列され
た銅製のリードフレーム（Ｃｕ−Ｌ／Ｆ）のアウターパ
ット側に貼り合わせた。このリードフレームのダイパッ
ド部分に半導体チップをエポキシフェノール系の銀ぺー
ストを用いて接着し、１８０℃にて１時間ほどキュアす
ることで固定した。· Apparatus: Model SP-2, manufactured by Malcolm Co. · Solder bath composition: Sn60wt% / Pb40wt% eutectic solder · Flux: RMA type · Immersion speed: 5 [mm / min] · Separation speed: 5 [ mm / min]-Immersion depth: 0.5 [mm]-Immersion time: 10 [s]-Solder bath temperature: 235 [° C]-Specimen dimensions: 5 mm width x 8 mm length (Reference Production Example 1) 25 µm Using a thick polyimide film (Kapton 100H manufactured by Toray Dupont) as a base material, a silicone-based adhesive (SD-4587 manufactured by Toray Dow Corning)
L) was used to prepare a heat-resistant pressure-sensitive adhesive tape provided with a 5 μm-thick pressure-sensitive adhesive layer. This heat-resistant pressure-sensitive adhesive tape was bonded to the outer pat side of a copper lead frame (Cu-L / F) in which 4 × 4 QFNs of 16 pins per side were arranged in the terminal portion. A semiconductor chip was adhered to the die pad portion of the lead frame using an epoxyphenol-based silver paste, and was fixed by curing at 180 ° C. for about 1 hour.

【００６３】つぎに、リードフレームは耐熱性粘着テー
プ側から真空吸引する形で２５０℃に加熱したヒートブ
ロックに固定し、さらにリードフレームの周辺部分をウ
インドクランパーにて押さえて固定した。これらを、６
０ＫＨｚワイヤボンダー（日本アビオニクス製）を用い
てφ２５μｍの金線（田中貴金属製ＧＬＤ−２５）にて
下記の条件でワイヤボンディングを行った。なお、すべ
てのボンディングを完了するのに約１時間を要した。Next, the lead frame was fixed to a heat block heated to 250 ° C. by vacuum suction from the heat-resistant adhesive tape side, and the peripheral portion of the lead frame was pressed and fixed with a wind clamper. These are 6
Using a 0 KHz wire bonder (manufactured by Nippon Avionics), wire bonding was performed with a φ25 μm gold wire (Tanaka Kikinzoku Kinzoku GLD-25) under the following conditions. It took about 1 hour to complete all bonding.

【００６４】ファーストボンディング加圧：３０ｇ ファーストボンディング超音波強度：２５ｍＷ ファーストボンディング印加時間：１００ｍｓｅｃ セカンドボンディング加圧：２００ｇ セカンドボンディング超音波強度：５０ｍＷ セカンドボンディング印加時間：５０ｍｓｅｃ さらにエポキシ系封止樹脂（日東電工製ＨＣ−３００）
により、これらをモールドマシン（ＴＯＷＡ製Ｍｏｄｅ
ｌ−Ｙ−ｓｅｒｉｓｅ）を用いて、１７５℃で、プレヒ
ート４０秒、インジェクション時間１１．５秒、キュア
時間１２０秒にてモールドした後、耐熱性テープを剥離
した。なお、さらに１７５℃にて３時間ほどポストモー
ルドキュアを行って樹脂を十分に硬化させた後、ダイサ
ーによって切断して、個々のＱＦＮタイプ半導体装置を
得た。First bonding pressure: 30 g First bonding ultrasonic intensity: 25 mW First bonding application time: 100 msec Second bonding pressure: 200 g Second bonding ultrasonic intensity: 50 mW Second bonding application time: 50 msec Further, epoxy-based sealing resin (Nitto Denko) HC-300)
By using a molding machine (TOWA Mode)
Using l-Y-series), the mold was molded at 175 ° C at a preheat of 40 seconds, an injection time of 11.5 seconds, and a cure time of 120 seconds, and then the heat-resistant tape was peeled off. After further performing post-mold curing at 175 ° C. for about 3 hours to sufficiently cure the resin, the resin was cut with a dicer to obtain individual QFN type semiconductor devices.

【００６５】このようにして得られたＱＦＮは、樹脂の
はみ出しもなく、またワイヤボンディングなどの各工程
も阻害なく実施することができた。但し、上記一連工程
においては、ワイヤボンディング工程でリードフレーム
の温度が約２５０℃となり、その結果、アウターパッド
に付着した汚染物質のＳｉ付着量が、１５９８ｍｇ／ｍ
2 となった。The thus obtained QFN did not protrude the resin, and could carry out each step such as wire bonding without hindrance. However, in the above series of steps, the temperature of the lead frame was about 250 ° C. in the wire bonding step, and as a result, the amount of contaminants deposited on the outer pad was 1598 mg / m 2.
It became 2 .

【００６６】（参考製造例２）参考製造例１において、
銅製のリードフレーム（Ｃｕ−Ｌ／Ｆ）の代わりに、銅
リードフレーム上にＮｉ（１．０μｍ），Ｐｄ（０．１
μｍ），Ａｕ（０．０１μｍ）が順次めっきされたリー
ドフレーム（Ｎｉ／Ｐｄ−Ｌ／Ｆという）を用いること
以外は、参考製造例１と同様にしてＱＦＮタイプ半導体
装置を製造した。このようにして得られたＱＦＮは、樹
脂のはみ出しもなく、またワイヤボンディングなどの各
工程も阻害なく実施することができた。但し、上記一連
工程においては、ワイヤボンディング工程でリードフレ
ームの温度が約２５０℃となり、その結果、アウターパ
ッドに付着した汚染物質のＳｉ付着量が、３２ｍｇ／ｍ
2となった。(Reference Production Example 2)
Instead of a copper lead frame (Cu-L / F), Ni (1.0 μm), Pd (0.1
A QFN type semiconductor device was manufactured in the same manner as in Reference Production Example 1, except that a lead frame (referred to as Ni / Pd-L / F) in which Au (0.01 μm) and Au (0.01 μm) were sequentially plated was used. The thus obtained QFN was able to be carried out without protruding the resin and without impeding the respective steps such as wire bonding. However, in the above series of steps, the temperature of the lead frame was about 250 ° C. in the wire bonding step, and as a result, the amount of contaminants adhering to the outer pad was 32 mg / m 2.
It became 2 .

【００６７】（参考試験例） （１）熱処理温度とリードフレーム上のＳｉ付着量との
関係 Ｃｕ−Ｌ／ＦおよびＮｉ／Ｐｄ−Ｌ／Ｆの各Ｌ／Ｆ両面
に耐熱性粘着テープ（シリコーン系粘着テープ）を貼り
付け、所定温度で２時間大気中で熱処理後、シリコーン
粘着テープを剥離し、蛍光Ｘ線装置によりＬ／Ｆ上に付
着したＳｉ付着量（ｍｇ／ｍ2 ）を分析した。得られた
分析結果を図５に示す。なお、Ｓｉ付着量（ｍｇ／ｍ
2 ）は測定ｎ数４の平均値を採用した。(Reference Test Example) (1) Relationship between heat treatment temperature and Si adhesion amount on lead frame Heat-resistant adhesive tape (silicone) is applied to both L / F surfaces of Cu-L / F and Ni / Pd-L / F. Adhesive tape), heat-treated in air at a predetermined temperature for 2 hours, peeled off the silicone adhesive tape, and analyzed the amount of Si attached on the L / F (mg / m 2 ) using a fluorescent X-ray apparatus. . FIG. 5 shows the obtained analysis results. In addition, Si adhesion amount (mg / m
For 2 ), the average value of the measured n number 4 was adopted.

【００６８】その結果、Ｃｕ−Ｌ／Ｆでは２００℃以上
で急激にＳｉ付着量が増加した。なお、熱処理温度２１
０℃以上のものではＬ／Ｆ表面を指で触るとタックがあ
った。また、Ｎｉ／ＰｄＬ／Ｆ では２００℃以上でＳ
ｉ付着量が増加し始めた。As a result, in Cu-L / F, the amount of deposited Si rapidly increased at 200 ° C. or higher. The heat treatment temperature 21
When the temperature was 0 ° C. or higher, the L / F surface was tacky when touched with a finger. For Ni / PdL / F, S
i The amount of adhesion started to increase.

【００６９】（２）熱処理温度とメニスコグラフ法はん
だ濡れ性との関係 Ｃｕ−Ｌ／ＦおよびＮｉ／Ｐｄ−Ｌ／Ｆの各Ｌ／Ｆ両面
に耐熱性粘着テープ（シリコーン系粘着テープ）を貼り
付け、所定温度で２時間大気中で熱処理後シリコーン粘
着テープを剥離し、所定の寸法（５ｍｍ幅×８ｍｍ長
さ）の試料片に切断後メニスコグラフ法評価を行った。
この際、Ｃｕ−Ｌ／Ｆは性質として酸化しやすくそのま
まの状態ではメニスコグラフ法評価が不可能であるた
め、メニスコグラフ法評価前に酸洗いによる前処理を行
った。一方、Ｎｉ／Ｐｄ−Ｌ／Ｆについてはシリコーン
粘着テープ剥離後そのままの状態でメニスコグラフ法評
価を行った。(2) Relation between heat treatment temperature and solder wettability by meniscograph method A heat-resistant adhesive tape (silicone-based adhesive tape) is attached to both L / F surfaces of Cu-L / F and Ni / Pd-L / F. After heat treatment in the air at a predetermined temperature for 2 hours, the silicone pressure-sensitive adhesive tape was peeled off, cut into a sample piece having a predetermined size (5 mm width × 8 mm length), and evaluated by a meniscograph method.
At this time, since Cu-L / F is easily oxidized as a property and cannot be evaluated by the meniscography method as it is, pretreatment by pickling was performed before the evaluation by the meniscography method. On the other hand, Ni / Pd-L / F was evaluated by the meniscograph method as it was after the silicone pressure-sensitive adhesive tape was peeled off.

【００７０】前記の表１に示す電解はんだめっき工程の
うち順序１〜４を今回のメニスコグラフ法の前処理とし
て行った。各評価Ｌ／Ｆで得られた濡れ力・濡れ時間を
図６に示す（（ａ）はＣｕ−Ｌ／Ｆ、（ｂ）はＮｉ／Ｐ
ｄ−Ｌ／Ｆ）。なお、濡れ力・濡れ時間の値には測定ｎ
数４の平均値を採用した。Among the electrolytic solder plating steps shown in Table 1 above, orders 1 to 4 were performed as pretreatment for the present meniscograph method. FIG. 6 shows the wetting power and the wetting time obtained in each evaluation L / F ((a) is Cu-L / F, (b) is Ni / P
d-L / F). The values of the wetting force and the wetting time are measured n
The average of Equation 4 was adopted.

【００７１】Ｃｕ−Ｌ／ＦおよびＮｉ／Ｐｄ−Ｌ／Ｆ
ともに熱処理温度２００℃までは濡れ力３．５ｍＮ以上
および濡れ時間１．０ｓ以下の値が得られた。以下この
条件をはんだ濡れ性良好レベルと判断する。Ｃｕ−Ｌ／
Ｆでは２１０℃でははんだが全く濡れなくなった（はん
だ未着：濡れ力０）。このとき、２１０℃以上酸洗いに
よる前処理でシリコーン粘着剤が残存していた。Ｎｉ／
Ｐｄ−Ｌ／Ｆでは２００℃以上ではんだ濡れ性が低下し
始め、３００℃ではんだ未着となる。Cu-L / F and Ni / Pd-L / F
In both cases, values of a wetting force of 3.5 mN or more and a wetting time of 1.0 s or less were obtained up to the heat treatment temperature of 200 ° C. Hereinafter, this condition is judged to be a solder wettability favorable level. Cu-L /
In F, the solder did not wet at 210 ° C. (no solder adhered: no wetting force). At this time, the silicone pressure-sensitive adhesive remained in the pretreatment by pickling at 210 ° C. or higher. Ni /
In the case of Pd-L / F, the solder wettability starts to decrease at 200 ° C. or higher, and no solder adheres at 300 ° C.

【００７２】（３）Ｓｉ付着量とはんだ濡れ性との関係 上記（１）項で求めた熱処理温度とＳｉ付着量との関
係、および（２）項で求めた熱処理温度とはんだ濡れ性
との関係から、粘着剤（Ｓｉ）付着量とはんだ濡れ性
（濡れ力，濡れ時間）の対応を図７にプロットした
（（ａ）はＣｕ−Ｌ／Ｆ、（ｂ）はＮｉ／Ｐｄ−Ｌ／
Ｆ）。(3) Relationship between Si adhesion amount and solder wettability The relationship between the heat treatment temperature and the Si adhesion amount determined in the above item (1), and the relationship between the heat treatment temperature and the solder wettability determined in the item (2). From the relationship, the correspondence between the adhesive (Si) adhesion amount and the solder wettability (wetting force, wet time) was plotted in FIG. 7 ((a) is Cu-L / F, (b) is Ni / Pd-L /
F).

【００７３】良好なはんだ濡れ性（濡れ力３．５ｍＮ以
上、濡れ時間１．０ｓ以下）を得るための許容Ｓｉ付着
量は、Ｎｉ／Ｐｄ−Ｌ／Ｆについては２０ｍｇ／ｍ2 以
下であった。このＳｉ付着量条件を満たす最大加熱温度
は２００℃であった。一方Ｃｕ−Ｌ／ＦについてはＳｉ
付着量１００ｍｇ／ｍ2 以下であり、このＳｉ付着量条
件を満たす最大加熱温度はＮｉ／Ｐｄ−Ｌ／Ｆと同様に
２００℃であった。The allowable Si adhesion amount for obtaining good solder wettability (wetting force 3.5 mN or more, wetting time 1.0 s or less) was 20 mg / m 2 or less for Ni / Pd-L / F. . The maximum heating temperature that satisfies the Si deposition amount condition was 200 ° C. On the other hand, for Cu-L / F, Si
The deposition amount was 100 mg / m 2 or less, and the maximum heating temperature satisfying the Si deposition amount condition was 200 ° C. as in Ni / Pd-L / F.

【００７４】（実施例１）参考製造例２で得られた半導
体装置（Ｎｉ／Ｐｄ−Ｌ／Ｆタイプ）を用いて、下記条
件にてＬ／Ｆ面にＡｒプラズマ処理を８分間施した。そ
の結果、アウターパッドに付着した汚染物質のＳｉ付着
量が、１０ｍｇ／ｍ2 になった。その後、直ちにメニス
コグラフ法評価を行ったところ、何れについても、はん
だ濡れ性を大幅に改善できた。Example 1 Using the semiconductor device (Ni / Pd-L / F type) obtained in Reference Production Example 2, an Ar plasma treatment was applied to the L / F surface for 8 minutes under the following conditions. As a result, the amount of Si of contaminants adhering to the outer pad was 10 mg / m 2 . Immediately after that, the evaluation by the meniscograph method was performed, and in each case, the solder wettability was significantly improved.

【００７５】 ・装置 ：九州松下電器（株）製、型式ＰＣ３２Ｐ−Ｍ ・Ａｒガス流量 ：５ｍｌ／ｍｉｎ ・プラズマ出力 ：５００Ｗ ・モード ：ＲＩＥ（Ｒｅａｃｔｉｖｅ ｉｏｎ ｅｔｃｈｉｎｇ） （実施例２）参考製造例１〜２で得られた半導体装置
（Ｃｕ−Ｌ／ＦタイプおよびＮｉ／Ｐｄ−Ｌ／Ｆタイ
プ）を用いる一方で、アルカリ液（メテックスＳ‐１７
０７，日本マクダミッド（株）製：液体状）を濃度１０
ｖｏｌ％で調製し、浴温度６０℃で１時間、各々の半導
体装置を浸漬処理してシリコーン粘着剤を除去した。そ
の結果、アウターパッドに付着した汚染物質のＳｉ付着
量が、それぞれ８８ｍｇ／ｍ2 と４ｍｇ／ｍ2 になっ
た。その後、直ちにメニスコグラフ法評価を行ったとこ
ろ、何れについても、はんだ濡れ性を大幅に改善でき
た。Equipment: Model PC32P-M, manufactured by Kyushu Matsushita Electric Co., Ltd. Ar gas flow rate: 5 ml / min Plasma output: 500 W Mode: RIE (Reactive ion etching) (Example 2) Reference Production Examples 1 to While using the semiconductor device (Cu-L / F type and Ni / Pd-L / F type) obtained in 2, the alkaline solution (Metex S-17)
07, made by MacDamid Japan Ltd .: liquid) at a concentration of 10
Each semiconductor device was immersed at a bath temperature of 60 ° C. for 1 hour to remove the silicone adhesive. As a result, Si deposition amount of contaminants attached to the outer pad became 88 mg / m 2 and 4 mg / m 2, respectively. Immediately after that, the evaluation by the meniscograph method was performed, and in each case, the solder wettability was significantly improved.

【００７６】また、Ｃｕ−Ｌ／Ｆタイプについては、前
記の表１に示す酸性クリーナ、ソフトエッチング、酸洗
い工程にて前処理後、ホウフッ化物浴での光沢系電解は
んだめっき工程にて良好なはんだめっき性が得られた。For the Cu-L / F type, after the pretreatment in the acidic cleaner, soft etching, and pickling steps shown in Table 1 described above, a good glossy electrolytic solder plating step in a borofluoride bath was performed. Solder plating property was obtained.

【００７７】（実施例３）参考製造例１〜２において、
ダイサーによる切断前のＬ／Ｆが付いた半導体装置（Ｃ
ｕ−Ｌ／ＦタイプおよびＮｉ／Ｐｄ−Ｌ／Ｆタイプ）を
用いる一方で、アルカリ液（パクナエレクターＮ−１，
ユケン工業（株）製：粉末状）を濃度１００ｇ／ｌで調
製し、陰極に各々の半導体装置のＬ／Ｆを、陽極にカー
ボン電極をつなげ、浴温度６０℃，電流密度５Ａ／ｄｍ
2 で５秒間電解脱脂処理を施して、シリコーン粘着剤を
除去した。その結果、アウターパッドに付着した汚染物
質のＳｉ付着量が、それぞれ５ｍｇ／ｍ2 と２ｍｇ／ｍ
2 になった。その後、直ちにメニスコグラフ法評価を行
ったところ、何れについても、はんだ濡れ性を大幅に改
善できた。Example 3 In Reference Production Examples 1 and 2,
Semiconductor device with L / F before cutting by dicer (C
While the u-L / F type and Ni / Pd-L / F type are used, the alkaline liquid (Pakna Elector N-1,
Yken Industry Co., Ltd .: powder) was prepared at a concentration of 100 g / l, the L / F of each semiconductor device was connected to the cathode, the carbon electrode was connected to the anode, the bath temperature was 60 ° C., and the current density was 5 A / dm.
2 was subjected to electrolytic degreasing treatment for 5 seconds to remove the silicone adhesive. As a result, the amounts of contaminants adhering to the outer pad were 5 mg / m 2 and 2 mg / m 2 , respectively.
It became 2 . Immediately after that, the evaluation by the meniscograph method was performed, and in each case, the solder wettability was significantly improved.

【００７８】また、Ｃｕ−Ｌ／Ｆタイプについては、前
記の表１に示す酸性クリーナ、ソフトエッチング、酸洗
い工程にて前処理後、ホウフッ化物浴での光沢系電解は
んだめっき工程にて良好なはんだめっき性が得られた。For the Cu-L / F type, after the pretreatment in the acidic cleaner, soft etching, and pickling steps shown in Table 1 described above, a favorable glossy electrolytic solder plating step in a borofluoride bath was performed. Solder plating property was obtained.

【００７９】（実施例４〜５）参考製造例１〜２におい
て、ワイヤボンディング工程の設定温度を１８０℃に代
える以外は、参考製造例１〜２と同様にしてＱＦＮタイ
プ半導体装置を製造した。このようにして得られたＱＦ
Ｎは、樹脂のはみ出しもなく、またワイヤボンディング
などの各工程も阻害なく実施することができた。その
際、何れの工程においてもリードフレームが２００℃を
超えることがなく、その結果、アウターパッドに付着し
た汚染物質のＳｉ付着量が、それぞれ９５ｍｇ／ｍ2 と
２０ｍｇ／ｍ2 となった。(Examples 4 and 5) A QFN type semiconductor device was manufactured in the same manner as in Reference Production Examples 1 and 2, except that the set temperature in the wire bonding step was changed to 180 ° C. QF obtained in this way
N was able to be carried out without protruding the resin and without impeding the respective steps such as wire bonding. At that time, without the lead frame is more than 200 ° C. In either process, the result, Si deposition amount of contaminants attached to the outer pad became 95 mg / m 2 and 20 mg / m 2, respectively.

【００８０】このようにして得られた半導体装置につい
て、メニスコグラフ法評価を行ったところ、何れについ
ても、はんだ濡れ性を大幅に改善できた。The semiconductor devices obtained in this manner were evaluated by the meniscograph method. As a result, the solder wettability was significantly improved in each case.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に用いられる半導体装置の製造方法の一
例を示す工程図FIG. 1 is a process chart showing an example of a method for manufacturing a semiconductor device used in the present invention.

【図２】本発明におけるリードフレームの一例を示す図
であり、（ａ）は正面図、（ｂ）は要部拡大図、（ｃ）
は樹脂封止後の状態を示す底面図FIGS. 2A and 2B are diagrams showing an example of a lead frame according to the present invention, wherein FIG. 2A is a front view, FIG.
Is a bottom view showing the state after resin sealing

【図３】本発明における樹脂封止工程の一例を示す縦断
面図FIG. 3 is a longitudinal sectional view showing an example of a resin sealing step in the present invention.

【図４】メニスコグラフ法を用いたはんだ濡れ性評価を
説明するための説明図FIG. 4 is an explanatory diagram for explaining solder wettability evaluation using a meniscograph method;

【図５】実施例における熱処理温度とケイ素原子付着量
との関係を示すグラフFIG. 5 is a graph showing a relationship between a heat treatment temperature and an attached amount of silicon atoms in Examples.

【図６】実施例における熱処理温度と濡れ性との関係を
示すグラフFIG. 6 is a graph showing the relationship between heat treatment temperature and wettability in Examples.

【図７】実施例におけるケイ素原子付着量と濡れ性との
関係を示すグラフFIG. 7 is a graph showing the relationship between the amount of silicon atoms attached and wettability in Examples.

【符号の説明】[Explanation of symbols]

１０ リードフレーム １１ａ 開口 １１ｂ 端子部 １１ｃ ダイパッド １５ 半導体チップ １５ａ 電極パッド １６ ボンディングワイヤ １７ 封止樹脂 ２０ 粘着テープ ２１ 封止された構造物 ２１ａ 半導体装置 DESCRIPTION OF SYMBOLS 10 Lead frame 11a Opening 11b Terminal part 11c Die pad 15 Semiconductor chip 15a Electrode pad 16 Bonding wire 17 Sealing resin 20 Adhesive tape 21 Sealed structure 21a Semiconductor device

───────────────────────────────────────────────────── フロントページの続き (72)発明者 名畑 憲兼 大阪府茨木市下穂積１丁目１番２号 日東 電工株式会社内 (72)発明者 高野 均 大阪府茨木市下穂積１丁目１番２号 日東 電工株式会社内 (72)発明者 古田 喜久 大阪府茨木市下穂積１丁目１番２号 日東 電工株式会社内 (72)発明者 種ヶ嶋 貞利 大阪府茨木市下穂積１丁目１番２号 日東 電工株式会社内 Ｆターム(参考） 5F044 KK01 LL01 QQ06  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor, Kenkane Nabata 1-2-1, Shimohozumi, Ibaraki-shi, Osaka Nitto Denko Corporation (72) Inventor Hitoshi Takano 1-1-1, Shimohozumi, Ibaraki-shi, Osaka No. 2 Nitto Denko Corporation (72) Inventor Yoshihisa Furuta 1-1-2 Shimohozumi, Ibaraki City, Osaka Prefecture Nitto Denko Corporation (72) Inventor Sadatoshi Tanegashima 1-1, Shimohozumi Ibaraki City, Osaka Prefecture No. 2 Nitto Denko Corporation F term (reference) 5F044 KK01 LL01 QQ06

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 シリコーン系粘着剤に由来する汚染物質
がアウターパッドに付着し、その汚染物質の付着量が蛍
光Ｘ線分析によるケイ素原子の付着量で２０ｍｇ／ｍ2
以下である半導体装置を用いて、配線基板へのはんだ付
けを行う工程を含む半導体装置の実装方法。1. A contaminant derived from a silicone-based pressure-sensitive adhesive adheres to an outer pad, and the amount of the contaminant is 20 mg / m 2 as the amount of silicon atoms adhered by X-ray fluorescence analysis.
A method of mounting a semiconductor device including a step of soldering to a wiring board using the following semiconductor device. 【請求項２】 シリコーン系粘着剤に由来する汚染物質
が銅製のアウターパッドに付着し、その汚染物質の付着
量が蛍光Ｘ線分析によるケイ素原子の付着量で１００ｍ
ｇ／ｍ2 以下である半導体装置を用いて、そのアウター
パッドを酸洗浄する工程と、酸洗浄したアウターパッド
をはんだメッキする工程と、はんだメッキした半導体装
置を配線基板へはんだ付けする工程とを含む半導体装置
の実装方法。2. A contaminant derived from a silicone-based pressure-sensitive adhesive adheres to an outer pad made of copper, and the amount of the contaminant is 100 m as the amount of silicon atoms adhered by X-ray fluorescence analysis.
g / m < 2 > or less, using a semiconductor device having a g / m < 2 > or less, the step of pickling the outer pad, the step of solder-plating the pickled outer pad, and the step of soldering the solder-plated semiconductor device to a wiring board. Semiconductor device mounting method including: 【請求項３】 前記半導体装置が、プラズマエッチング
処理又はアルカリ電解処理により前記汚染物質が洗浄さ
れたものである請求項１又は２に記載の半導体装置の実
装方法。3. The method of mounting a semiconductor device according to claim 1, wherein the contaminant is cleaned by a plasma etching process or an alkaline electrolysis process. 【請求項４】 前記半導体装置が、耐熱性粘着テープを
貼り合わせた金属製のリードフレームのダイパッド上に
半導体チップをボンディングする搭載工程と、前記リー
ドフレームの端子部先端と前記半導体チップ上の電極パ
ッドとをボンディングワイヤで電気的に接続する結線工
程と、封止樹脂により半導体チップ側を片面封止する封
止工程とを含み、前記リードフレームの温度を常に２０
０℃以下に制御する製造方法によって製造されたもので
ある請求項１又は２に記載の半導体装置の実装方法。4. A mounting step in which the semiconductor device bonds a semiconductor chip onto a die pad of a metal lead frame to which a heat-resistant adhesive tape is attached, and a terminal end of the lead frame and an electrode on the semiconductor chip. A connection step of electrically connecting the pads with bonding wires, and a sealing step of sealing the semiconductor chip side on one side with a sealing resin.
3. The semiconductor device mounting method according to claim 1, wherein the semiconductor device is manufactured by a manufacturing method controlling the temperature to 0 ° C. or lower. 【請求項５】 シリコーン系粘着剤に由来する汚染物質
がアウターパッドに付着し、その汚染物質の付着量が蛍
光Ｘ線分析によるケイ素原子の付着量で２０ｍｇ／ｍ2
以下である半導体装置。5. A contaminant derived from a silicone-based pressure-sensitive adhesive adheres to the outer pad, and the amount of the contaminant is 20 mg / m 2 as the amount of silicon atoms adhered by X-ray fluorescence analysis.
A semiconductor device which is as follows. 【請求項６】 シリコーン系粘着剤に由来する銅製のア
ウターパッドに付着し、その汚染物質の付着量が蛍光Ｘ
線分析によるケイ素原子の付着量で１００ｍｇ／ｍ2 以
下である半導体装置。6. A fluorescent X-ray adhering to a copper outer pad derived from a silicone-based pressure-sensitive adhesive and the amount of contaminants adhering thereto.
A semiconductor device having a silicon atom adhesion amount of 100 mg / m 2 or less as determined by linear analysis.
JP2000362669A 2000-11-29 2000-11-29 Method for mounting semiconductor device Pending JP2002164387A (en)

Priority Applications (1)

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Publication Number Publication Date
JP2002164387A true JP2002164387A (en) 2002-06-07

Family

ID=18833905

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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004224857A (en) * 2003-01-21 2004-08-12 Lintec Corp Pressure-sensitive adhesive tape for electronic device
JP2012109529A (en) * 2010-09-16 2012-06-07 Hitachi Cable Ltd Substrate for mounting semiconductor light-emitting element, and semiconductor light-emitting device using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004224857A (en) * 2003-01-21 2004-08-12 Lintec Corp Pressure-sensitive adhesive tape for electronic device
JP4553553B2 (en) * 2003-01-21 2010-09-29 リンテック株式会社 Adhesive tape for electronic devices
JP2012109529A (en) * 2010-09-16 2012-06-07 Hitachi Cable Ltd Substrate for mounting semiconductor light-emitting element, and semiconductor light-emitting device using the same

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