JP2002158890A - Device and method for detecting phase locking and picture processor using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably detect the phase locked state of PLL. SOLUTION: When a PLL circuit which is synchronized with a first reference signal and generates a clock signal having a frequency which is N (N is the integer of one or above) times as much as the first reference signal is in the locked state or not, a locking detection signal showing that the PLL circuit is in the locked state is generated if the signal showing that the PLL circuit is in the locked state is outputted to an unlocking signal outputted from the PLL circuit in the periods of M periods (M is the integer of two or above) where first reference pulses generated at a prescribed period continue in the first reference signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for stably detecting whether a PLL circuit for generating a clock signal synchronized with a reference signal is in a locked state.

[0002]

2. Description of the Related Art In various image processing devices such as a liquid crystal display device and an image scan converter, in order to process an image signal supplied from an image reproducing device such as a computer, a horizontal synchronizing signal indicating a timing of the image signal is processed. The synchronized dot clock signal is generated by a clock generator including a PLL circuit.

FIG. 6 is a block diagram showing an example of a conventional clock generator and phase lock detecting device.
The clock generator 1000 generally includes a phase difference detector (PD) 1010 and a low-pass filter (LPF)
(Also referred to as a loop filter) 1020, a voltage controlled oscillator (VCO) 1030, and a frequency divider (DIV) 1040. The phase difference detector 1010 has an input terminal RE.
A horizontal synchronization signal HD as a reference signal input to F;
The phase difference signal corresponding to the phase difference of the edge with the feedback signal HFD input to the feedback input terminal FB is output. The phase difference signal from the phase difference detector 1010 is
To the voltage controlled oscillator 1030 as a control voltage. The voltage controlled oscillator 1030 oscillates at a frequency corresponding to the applied control voltage, and its output is output as the dot clock signal DCK and the frequency divider 104
Input to 0. The frequency divider 1040 divides the frequency of the dot clock signal DCK by the set multiplication number N, and outputs a feedback signal H
Output as FD. Each block constituting the clock generator 1000 constitutes a PLL circuit, and operates so that the reference signal HD and the feedback signal HFD have the same phase and the same frequency. Thereby, the dot clock signal D
CK is a signal having a frequency N times that of the reference signal HD and having the same phase as the reference signal HD.

[0004] A phase difference detector 1010 outputs an unlock signal UL. The unlock signal UL includes
When there is a phase difference between the edges of the reference signal HD and the feedback signal HFD, an unlock pulse having a length corresponding to the phase difference is generated.

[0005] The phase lock detecting device 1100 includes an integrator 1.
110 and a comparator 1120. FIG.
9 is a timing chart showing the operation of the phase lock detection device 1100. As shown in FIG. 7C, the unlock signal UL output from the clock generator 1000 has a phase difference between the pulse of the reference signal HD and the pulse of the feedback signal HFD in FIG. 7A. A pulse having a length corresponding to the phase difference is output. In the unlock signal UL of this example, the phase difference between rising edges is shown, but there may be a phase difference between falling edges or a phase difference between one rising edge and the other falling edge. . In some cases, a pulse synchronized with the dot clock signal DCK is output.

An unlock signal U including an unlock pulse
L is smoothed by the integrator 1110 as shown in FIG. The smoothed unlock signal IL output from the integrator 1110 is input to the comparator 1120, is compared with the comparison voltage Von, and is converted into a low-level or high-level signal as shown in FIG. .
In this example, a low level corresponds to an unlocked state, and a high level corresponds to a locked state. This level signal is output as a phase lock detection signal LF and is used for various controls. For example, the phase lock detection signal LF is used as a timing signal for starting image processing using a dot clock signal after detecting a lock state.

[0007]

In an actual circuit, jitter (phase fluctuation) frequently occurs in each signal.
Normally, even if the reference input signal and the feedback signal are slightly shifted in phase due to the jitter, it is often acceptable that the phase is in a normal phase locked state. In the conventional phase lock detection device 1100, the phase difference generated by the jitter is absorbed by smoothing the unlock signal UL.

However, the conventional phase lock detecting device 110
In the case of 0, near the critical point where a phase difference actually occurs and switches from the locked state to the unlocked state, or from the unlocked state to the locked state, it is absorbed by jitter despite the unlocked state. As a result, an erroneous detection of the locked state or an erroneous detection of the unlocked state despite the locked state may occur. In particular, erroneously detecting the unlocked state as the locked state is not preferable because the reliability of image processing is reduced.

When the unlock signal UL is output as a signal synchronized with the dot clock signal DCK, the reference signal HD and the feedback signal H are output near the critical point.
Since the phase difference with the FD is small, the dot clock signal DC
In some cases, synchronization by K cannot be performed, and the unlock signal UL malfunctions. As a result, the phase lock detector 110
0 may be erroneously detected.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the prior art, and has as its object to provide a technique capable of stably detecting a phase locked state of a PLL circuit.

[0011]

Means for Solving the Problems and Their Functions / Effects To solve at least a part of the above-mentioned problems, the present invention provides:
A PLL circuit that generates a clock signal from the first reference signal, the clock signal being synchronized with the first reference signal and having a frequency N times (N is an integer of 1 or more) of the first reference signal; In the case of detecting whether or not the following conditions are satisfied, over a period equal to or more than M consecutive periods (M is an integer of 2 or more) of a first reference pulse generated at a constant period in the first reference signal,
When an unlock signal output from the PLL circuit maintains a state indicating that the PLL circuit is locked, a lock detection signal indicating that the PLL circuit is locked is generated. And

According to the above invention, when the PLL circuit is in the locked state for a period of M or more continuous M cycles of the first reference pulse generated in the first reference signal at a fixed cycle, the PLL circuit is locked. Since the lock detection signal indicating the state is generated, the locked state of the PLL circuit can be detected when the phase locked state of the PLL circuit is stable.

Here, detection of whether or not the PLL circuit is in a locked state may be stopped within a predetermined period determined by a second reference pulse generated at a constant period of the second reference signal. preferable.

When the cycle of the first reference signal is unstable, the output of the phase lock detection device may be unstable due to the instability of the PLL circuit. If this happens,
By setting the unstable period to a predetermined period, the phase lock detection within the predetermined period can be stopped, so that the locked state of the PLL circuit can be stably detected.

It is preferable that the first reference signal is a horizontal synchronization signal of an image signal, and the second reference signal is a vertical synchronization signal of the image signal.

The cycle of the horizontal synchronizing signal of the image signal may become unstable during the vertical blanking period determined by the vertical synchronizing signal depending on the type of the image signal. In such a case, if the first reference synchronization signal is a horizontal synchronization signal and the second reference signal is a vertical synchronization signal, a period including at least a vertical blanking period is set as a predetermined period. Since the phase lock detection during the period can be stopped, the phase lock state of the PLL circuit can be stably detected.

Here, the phase lock detection is reset when the unlock signal indicates that the PLL circuit is in an unlocked state, and counts the first reference pulse. This can be performed by generating the lock detection signal when the count value of one reference pulse is M or more.

Further, the counting of the first reference pulse may be stopped within a predetermined period determined by the second reference pulse of the second reference signal generated at a constant cycle. Good.

The present invention can be realized in various modes such as a phase lock detecting method, a phase lock detecting device, a clock generator having the phase lock detecting device, and an image processing device having the phase lock detecting device.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an image display device (image processing device) provided with a phase lock detection device as one embodiment of the present invention. The image display device 10 includes a CPU 20, an image input unit 30,
Image processing unit 40, display unit 50, synchronization signal analysis unit 60
, A clock generator 70, and a phase lock detection device 80. Each block 20 to 80 is a bus 2
0b. The CPU 20 controls the operation of each of the blocks 30 to 80.

The image input unit 30 receives a video signal VS supplied from an external image reproducing device, for example, a video recorder or a personal computer. The image input unit 30
A component image signal PS composed of three color signals of RGB, a vertical synchronization signal VD, and a horizontal synchronization signal HD
Is output. As the video signal VS, for example, an RGB signal output from a personal computer, a composite signal output from a video tape recorder, and the like are input. When the video signal VS is a composite signal, the image input unit 30 demodulates the composite signal and separates the composite signal into a component signal and a synchronization signal.
In the case where the video signal VS is an RGB signal output from a personal computer, the signal is originally input as a component signal and the synchronization signal is also input separately, so that no separation processing is required. Also, of the RGB signals, the G signal is a sync-on signal in which the horizontal and vertical synchronization signals are superimposed.
In the case of a green signal, the synchronization signal is separated from the G signal.

The image processing section 40 receives the image signal PS from the image input section 30, the horizontal synchronizing signal HD and the vertical synchronizing signal VD, and executes various image processing. The image signal processed by the image processing unit 40 is supplied to the display unit 50, and an image corresponding to the image signal PS is displayed.

The synchronizing signal analyzing section 60 analyzes the synchronizing signal output from the image input section 30. The analyzed result is
The specification (type) of the video signal VS supplied to the CPU 20 is determined. The CPU 20 sets the operating conditions of each block according to the determined specification.

The clock generator 70 generates a dot clock signal DCK synchronized with the horizontal synchronizing signal HD. Further, the clock generator 70 outputs an unlock signal UL. As the clock generator 70, a PLL frequency synthesizer is generally used. The basic configuration of the clock generator is the same as the configuration described in the conventional example, and the description is omitted here. As described in the related art, the unlock signal UL includes the edge position of the pulse of the reference signal (horizontal synchronization signal) HD input to the phase difference detector PD constituting the PLL frequency synthesizer and the pulse of the feedback signal HFD. When there is a phase difference with the edge position, a pulse corresponding to the phase difference is output.

The phase lock detector 80 receives a vertical synchronizing signal VD, a horizontal synchronizing signal HD, and an unlock signal UL. The phase lock detection device 80 detects whether the PLL circuit of the clock generator 70 is in a phase locked state or an unlocked state, and outputs a phase lock detection signal LF. The CPU 20 determines whether the clock generator 70 is in the phase locked state or the unlocked state according to the phase lock detection signal LF, and controls the operation of each block.

FIG. 2 is a schematic block diagram showing the internal configuration of the phase lock detection device 80. The phase lock detection device 80 includes a mask generation unit 80A and a phase lock detection unit 8
0B. The mask generation unit 80A and the phase lock detection unit 80B are connected to the CPU 2 via the bus 20b.
Connected to 0.

The mask generator 80A includes a mask timing generator 810 and a mask generator 820.

The clear terminal Clr of the mask timing generation circuit 810 has a vertical synchronization signal VD and a reset signal RS.
An OR signal with T is input via an OR circuit 812. Further, a horizontal synchronization signal HD is input to a clock terminal CK of the mask timing generation circuit 810. The mask timing generation circuit 810 is reset in response to the vertical synchronization signal VD or the reset signal RST, and outputs a mask timing signal MTD synchronized with the horizontal synchronization signal HD.

The clear terminal Clr of the mask generation circuit 820
, An OR signal representing an OR of a reset signal RST supplied from the outside and a mask timing signal MTD supplied from the mask timing generation circuit 810 is input via an OR circuit 822. The horizontal synchronizing signal HD is input to the clock terminal CK of the mask generation circuit 820. The mask generation circuit 820 outputs the reset signal R
It is reset in response to ST or the mask timing signal MTD, and outputs a mask signal VMD synchronized with the horizontal synchronization signal HD.

FIG. 3 is a timing chart showing the operation of the mask generator 80A. As shown in FIG. 3 (c), the mask timing generation circuit 810 sets the mask timing signal MTD before the rising edge timing tvr of the vertical synchronization signal VD of FIG. A pulse that rises at a timing tmr of a synchronizing signal cycle (f is an integer of 0 or more) is output.

The mask timing generation circuit 810
Can be easily constituted by, for example, a counter using the horizontal synchronization signal HD as a clock signal. Specifically, the length of one cycle of the vertical synchronization signal VD is aH (a is 1
When the above integer, a> f), the vertical synchronization signal VD
The counter starts counting at the rising edge timing tvr, and ends counting at the count number (af). Thereby, the mask timing signal MT
D can be generated.

The mask generation circuit 820 outputs the mask signal VM
As shown in FIG. 3D, D rises at the rising edge timing tmr of the mask timing signal MTD, and after the falling edge timing tvf of the vertical synchronizing signal VD of FIG. A pulse (pulse width m · H) that falls at a timing tmf of “b” is an integer of 0 or more is output.

Note that the mask generation circuit 820 is, for example,
It can be easily constituted by a counter using the horizontal synchronization signal HD as a clock signal. Specifically, when the pulse width (vertical synchronization period) of the vertical synchronization pulse of the vertical synchronization signal VD is s · H (s is an integer of 1 or more), the rising edge timing tmr of the mask timing signal MTD
To start a count, and terminate the count with the count number m (= f + s + b). This allows
The mask signal VMD having the length m · H of the mask period can be generated.

The lengths f · H and b · H are such that the length m · H of the generated mask period includes at least the vertical blanking period (front porch period + vertical synchronization period + back porch period). Is set according to the specifications of the video signal analyzed by the synchronization signal analysis unit 60.
Normally, it is preferable to set the period to include a period from several H before the start timing of the vertical blanking period (start timing of the front porch period) to several H after the end timing (end timing of the back porch period).

The above-described mask timing generation circuit 8
10 and the setting of the operating conditions of the mask generation circuit 820 are as follows:
It is executed by the CPU 20 via the bus 20b.

The phase lock detector 80B of FIG. 2 includes a counter 830, a comparator 840, and a mask register 8
50. The reset signal RST is input to the clear terminal Clr of the counter 830 via the OR circuit 832 as the clear signal CR. Further, the reset signal RST is input to the clear terminal Clr of the comparator 840 and the mask register 850. Thus, the counter 830, the comparator 840, and the mask register 850 can be reset according to the reset signal RST.

The OR circuit 832 has a reset signal RST
When the output signal of the AND circuit 834 is input and the reset signal RST is in an inactive state (low level), the output signal of the AND circuit 834 is output to the clear terminal Clr of the counter 830 as the clear signal CR. Is entered. The AND circuit 834 has an input terminal A
1 and the inverted input terminal A2
ANDing with the mask signal VMD input to
Output a signal. Therefore, the clear signal CR indicates the same level as the unlock signal UL when the mask signal VMD is in an inactive state (low level), and goes to a low level when the mask signal VMD is active (high level).

The enable signal En output from the AND circuit 836 is supplied to the enable terminal En of the counter 830.
E has been entered. The AND circuit 836 has two inverting input terminals, and represents an AND of the mask signal VMD output from the mask generation circuit 820 and the phase lock detection signal LF output from the comparator 840.
The D signal is output.

The comparator 840 sets the count value HCNT input to the A terminal and the set value HSET of the mask register 850 input to the B terminal (here, p is set.
p is an integer of 1 or more. ) And compare. And B> A,
That is, when HSET> HCNT, the phase lock detection signal LF is set to an inactive state (low level). When B ≦ A, that is, when HSET ≦ HCNT, the phase lock detection signal LF is set to an active state (high level).

The operation of the phase lock detection unit 80B will be described below in two cases: a case where the mask signal VMD is at the high level and a case where the mask signal VMD is at the low level.

FIG. 4 is a timing chart showing the operation of the phase lock detector 80B during the non-mask period.
As shown in FIG. 4C, the count value HCNT of the counter 830 is reset to 0 when the clear signal CR corresponding to the unlock signal UL in FIG.

When the count value HCNT of the counter 830 is reset to 0 by the clear signal CR, HC
NT <HSET, and the phase lock detection signal LF output from the comparator 840 is in an inactive state (low level). At this time, since the enable signal CE in FIG. 4E is in an active state (high level), the counter 830 becomes operable. That is, the counter 830 counts horizontal synchronization pulses using the horizontal synchronization signal HD in FIG. 4A as a clock signal. HC
When the unlock signal UL goes high while NT <HSET, the count value HCNT of the counter 830 is reset to 0 each time, and the counter 830 is reset.
Repeats counting from 0. When the count value HCNT becomes HCNT = HSET (= p), the phase lock detection signal LF output from the comparator 840 becomes active (high level), as shown in FIG. 4D. When the phase lock detection signal LF goes high, the enable signal CE goes low as shown in FIG. 4E, and the counting operation of the counter 830 is stopped. At this time, the count value HCNT is equal to the set value HSET =
Stop with the value equal to p. Accordingly, the phase lock detection signal LF maintains the high level until the unlock signal UL becomes the high level again and the count value HCNT of the counter 830 is reset to 0. As a result, it is possible to detect whether or not the unlock detection signal UL changes to a high level within a period corresponding to the set value HSET = p set in the mask register 850.

Therefore, the phase lock detecting section 80B outputs the unlock signal UL within a period corresponding to the set value HSET = p.
Changes to a high level, HCNT <HSET
As a result, the phase lock detection signal LF becomes a low level indicating an unlocked state. If the unlock signal UL remains at the low level during the period of the set value HSET = P, HCNT = HSET, and the phase lock detection signal LF goes to the high level indicating the locked state. Therefore, C
The PU 20 can know whether the clock generator 70 is in the locked state or the unlocked state by checking the level of the phase lock detection signal LF.
Further, the phase lock detection signal LF is at the high level (indicating the locked state) only when the locked state of the PLL circuit is stable and the pulse of the unlock signal UL is not generated for the HSET period of the horizontal synchronization pulse. )become. Therefore, by checking the level of the phase lock detection signal LF, the CPU 20 can determine that the PLL circuit is in a sufficiently stable state.

FIG. 5 is a timing chart showing the operation of the phase lock detector 80B during the mask period. In the mask period, that is, when the mask signal VMD in FIG. 5A is at a high level, as shown in FIG. 5E, the enable signal CE is in an inactive state (low level). Thus, the counting operation of the counter 830 stops. Also, as shown in FIG. 5C, even if the unlock signal UL changes to a high level during the mask period,
As shown in (d), the clear signal CR does not change and remains at the low level. As a result, the count value HCNT (FIG. 5 (f)) of the counter 830 maintains the value before the enable signal CE changes to low level. As a result, the operation of the phase lock detection unit 80B is effectively masked during the mask period.

As described above, by stopping the phase lock detector 80B during the mask period, the following advantages are obtained. For some video signals, the cycle of the horizontal synchronization signal HD during the vertical blanking period becomes unstable. As such a video signal, for example, there is a video signal in which a synchronization signal is superimposed on a G signal, that is, a so-called sync-on-green video signal. in this way,
If the cycle of the horizontal synchronizing signal HD becomes unstable during the vertical blanking period, the operation of the clock generator 70 also becomes unstable, so that a pulse of the unlock signal UL is likely to be generated. However, since the unlock pulse of the unlock signal is caused by the instability of the cycle of the horizontal synchronizing signal HD, if this signal is used to control other signals, a malfunction may occur. In the phase lock detection device 80 of the present embodiment, the operation of the phase lock detection unit 80B is masked during the period in which the cycle of the horizontal synchronization signal HD is unstable, so that such a malfunction can be prevented. Note that, as can be seen from the above description, the mask period corresponds to a predetermined period of the present invention.

The set value HS of the mask register 850 is used.
If ET is set to a value corresponding to a period in which the lock state of the PLL circuit can be considered to be kept sufficiently stable,
The phase lock detector 80B can realize stable phase lock detection. The set value HSET is determined according to various characteristics (characteristic frequency, damping coefficient, lock-up time, etc.) of the PLL circuit of the clock generator 70.

For example, in the case of a clock generator built in a CXA3516 (manufactured by Sony), as an example, for a video signal compatible with UXGA (effective pixel number 1600 × 1200, clock frequency 162 MHz),
By setting HSET = 32, stable phase lock detection can be performed. Also, VGA (640 effective pixels)
(* 480, clock frequency 25.18 MHz), a stable phase lock can be detected by setting HSET = 4.

The set value HSET is stored in C via the bus 20b.
This is set in the mask register 850 by the PU 20.

Here, the setting of the set value HSET may be set to each specification when one image processing apparatus corresponds to the specification of a plurality of video signals, or may be set to the largest value. You may keep it. When setting to each specification, a set value HSET corresponding to each specification may be prepared in advance as a table. Then, a set value HSET corresponding to the specification determined by the synchronization signal analysis unit 60 is read from the table, and the
What is necessary is just to set it to 50.

The mask generator 80A is not always necessary when the period of the horizontal synchronizing signal HD is stable during the vertical blanking period. When only such a stable horizontal synchronizing signal HD is input, the mask generation unit 80A and the AND circuit 834 may be omitted, and the AND circuit 836 may be a NOT circuit.

It should be noted that the phase lock detection device 80 of this embodiment is
The configuration and the timing chart are merely examples, and the present invention is not limited thereto. That is, if a phase lock detection signal indicating that the PLL circuit is locked is generated when an unlock pulse is not generated during a period in which a predetermined number of horizontal sync pulses are generated in the horizontal sync signal. Good. Also, a period determined by the vertical synchronization pulse of the vertical synchronization signal (a period during which the horizontal synchronization signal is unstable).
Any device that can stop detection of whether or not the PLL circuit is in the locked state may be used.

As can be understood from the above description, the horizontal synchronization signal and the vertical synchronization signal correspond to the first reference signal and the second reference signal of the present invention. The period determined by the set value HSET corresponds to a first period. A period including at least the vertical blanking period corresponds to a second period. Note that the first reference signal and the second reference signal are not necessarily limited to the horizontal synchronization signal and the vertical synchronization signal, and various reference signals can be applied. However, the second
Is preferably synchronized with the first reference signal.

The present invention is not limited to the above-described examples and embodiments, but can be implemented in various modes without departing from the scope of the invention.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an image display device (image processing device) including a phase lock detection device as one embodiment of the present invention.

FIG. 2 is a schematic block diagram showing an internal configuration of a phase lock detection device 80.

FIG. 3 is a timing chart showing an operation of a mask generation unit 80A.

FIG. 4 shows a phase lock detection unit 80B during a non-mask period.
6 is a timing chart showing the operation of FIG.

FIG. 5 is a timing chart showing an operation of a phase lock detection unit 80B during a mask period.

FIG. 6 is a block diagram illustrating an example of a conventional clock generator and a phase lock detection device.

FIG. 7 is a timing chart showing the operation of the phase lock detection device 1100.

[Explanation of symbols]

 Reference Signs List 10 image display device 20 CPU 20b bus 30 image input unit 40 image processing unit 50 display unit 60 synchronization signal analysis unit 70 clock generator 80 phase lock detection device 80A mask generation unit 810 mask timing Generation circuit 820: Mask generation circuit 80B: Phase lock detection unit 830: Counter 840: Comparator 850: Mask register

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) MM49 MM56 MM62

Claims (7)

[Claims] 1. A method according to claim 1, wherein the first reference signal is synchronized with the first reference signal and is N times (N is 1) of the first reference signal.
A phase lock detection device for detecting whether or not a PLL circuit that generates a clock signal having a frequency of the above (integer) is in a locked state, wherein the first reference signal generated at a constant period in the first reference signal When an unlock signal output from the PLL circuit maintains a state indicating that the PLL circuit is in a locked state for a period of M or more consecutive M cycles (M is an integer of 2 or more) of the pulse, A phase lock detection device for generating a lock detection signal indicating that a PLL circuit is locked. 2. The phase lock detection device according to claim 1, wherein the phase lock detection device is provided within a predetermined period determined by a second reference pulse generated at a constant period of the second reference signal. A phase lock detection device for stopping detection of whether or not the PLL circuit is in a locked state. 3. The phase lock detection device according to claim 2, wherein the first reference signal is a horizontal synchronization signal of an image signal,
The phase lock detection device, wherein the second reference signal is a vertical synchronization signal of the image signal. 4. The phase lock detection device according to claim 1, wherein the unlock signal is reset when the unlock signal is in a state indicating that the PLL circuit is in an unlock state, and the first reference pulse is reset. A phase lock detection device comprising: a counter that counts; and a comparator that generates the lock detection signal when the count value of the first reference pulse is equal to or greater than M. 5. The phase lock detecting device according to claim 4, wherein the counter is configured to be configured such that, within a predetermined period determined by a second reference pulse of a second reference signal generated in a constant cycle, A phase lock detection device that stops counting a first reference pulse. 6. The first reference signal is synchronized with the first reference signal and is N times (N is 1) of the first reference signal.
A phase lock detection method for detecting whether or not a PLL circuit that generates a clock signal having a frequency of the above (integer) is in a locked state, wherein the first reference signal is generated at a constant period. When an unlock signal output from the PLL circuit maintains a state indicating that the PLL circuit is in a locked state over a period of M or more continuous M periods of the reference pulse (M is an integer of 2 or more), A phase lock detection method for generating a lock detection signal indicating that the PLL circuit is locked. 7. An image processing apparatus for processing an image signal, comprising: synchronizing with the horizontal synchronizing signal from a horizontal synchronizing signal of the image signal and N times the horizontal synchronizing signal (N is an integer of 1 or more) PLL for generating a clock signal having a frequency of
A phase lock detection device for detecting whether or not the PLL circuit is in a locked state. The phase lock detection device comprises: a continuous M of a horizontal synchronization pulse generated at a constant period in the horizontal synchronization signal; When the unlock signal output from the PLL circuit maintains a state indicating that the PLL circuit is in a locked state over a period (M is an integer of 2 or more) or more, the PLL circuit is in a locked state. An image processing device that generates a lock detection signal indicating that