JP2002158301A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce parasitic capacitance in the periphery of a floating gate and improve writing characteristic and charge holding characteristic. SOLUTION: An electrode 13 is formed on a floating gate 10 via an interlayer insulating film 11. By using the above constitution, writing is enabled from above and below the floating gate 10 by applying an electric field to the floating gate 10 via the electrode 13. Consequently, writing amount can be more effectively increased and decreased as compared with the case wherein writing is performed by using only a control gate 4. Furthermore, potential at the periphery of a floating gate can be stabilized, a threshold voltage Vt can be stabilized, and writing operation is enabled without directly applying an electric field to a gate insulating film 8 on the control gate 4, so that deterioration of the gate insulating film 8 can also be restrained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and is suitably applied to, for example, an electrically rewritable nonvolatile memory.

[0002]

2. Description of the Related Art FIG. 14 shows a configuration of a conventional EPROM. FIG. 14A shows a layout configuration of the EPROM, and FIG. 14B shows a cross-sectional configuration of the EPROM. The semiconductor substrate 101 has an n-type well layer 102 and a p-type well layer 103. A control gate 104 composed of a high-concentration diffusion layer is provided on the n-type well layer 102 side, and a source 1 constituting a transistor portion is provided on the p-type well layer 103 side.
05. A drain 106 is formed.

[0005] A LOCOS oxide film 107 is formed on the n-type well layer 102 and the p-type well layer 103, and the LOCOS oxide film 107 provides element isolation. The LOCOS oxide film 107 is open in a region including a part of the control gate 104 in the n-type well layer 102 and a region including the source 105 and the drain 106 in the p-type well layer 103. This L
A gate insulating film 108 of the control gate 104 and a gate insulating film 109 of the transistor portion are formed in portions where the OCOS oxide film 107 is opened.

Further, a floating gate 110 is formed on both gate insulating films 108 and 109 over the LOCOS oxide film 107, and an insulating film 111 is formed so as to cover the floating gate 110. The control gate 104 is connected to the gate electrode 112 via a contact hole formed in the insulating film 111.

In an EPROM having such a configuration,
At the time of writing, a voltage is applied to the drain 106 of the transistor portion to generate hot carriers, and a voltage is applied to the control gate 104 to inject carriers into the floating gate 110 to change the threshold voltage Vt of the transistor. Let it.

What is important at this time is the ratio between the gate capacitance of the transistor portion and the control gate capacitance (hereinafter, referred to as a coupling ratio). The larger the coupling ratio (the larger the control gate side is than the gate side of the transistor portion), the larger the voltage ratio applied to the transistor gate becomes, and the easier it is to inject charges into the floating gate.

[0007]

However, as can be seen from the equivalent circuit of the EPROM having the above structure shown in FIG. 15, parasitic capacitances (C _FP and C _FL shown in FIG. 15) are formed around the floating gate. Therefore, the voltage ratio applied to the gate of the transistor portion decreases, and it becomes difficult to inject charges. However, _CFP is the floating gate 11
The parasitic capacitance in the interlayer insulating film 111 above 0, C _FL is the parasitic capacitance between the floating gate 110 and the n-type well layer 102 and the p-type well layer 103, and C _FG is between the floating gate 110 and the control gate 104. Capacity,
C _FS indicates the capacitance between the floating gate 110 and the source 105 / drain 106.

On the other hand, due to potential interference of the control gate voltage, a state where charges are accumulated in the parasitic capacitance is obtained.
The threshold voltage Vt of the transistor also increases. However, the state of the parasitic capacitance is easily recovered, and is easily recovered by applying a small amount of heat. As a result, the threshold voltage Vt is reduced. The decrease in the threshold voltage Vt depends on the area of the floating gate 104, and decreases as the parasitic capacitance increases.

Further, since the area where the floating gate 110 is in contact with the outside is large, the floating gate 110 is easily affected by the outside. For this reason, there is a problem that the threshold voltage Vt fluctuates due to the potential around the floating gate 110, or the influence of ions from the outside causes the loss of charge to increase.

In view of the foregoing, it is an object of the present invention to reduce the parasitic capacitance around the floating gate and to improve the write characteristics and the charge retention characteristics.

[0011]

In order to achieve the above object, according to the first to seventh aspects of the present invention, a control gate (4) comprising a diffusion layer formed on a surface layer portion of a semiconductor substrate (1); A first gate insulating film (8) formed on the control gate, a transistor portion having a source (5) and a drain (6) formed on a surface layer of the semiconductor substrate; With the second gate insulating film (9) formed and the first and second gate insulating films interposed, the floating gate (1) composed of a conductor layer formed on the control gate and the transistor portion
0), an interlayer insulating film (11) formed on the floating gate, and a conductive film (13) formed on the interlayer insulating film and covering at least a part of the floating gate. It is characterized by having.

As described above, by forming the conductive film so as to cover at least a part of the floating gate, an electric field is applied to the floating gate through the conductive film,
Writing can be performed from above and below the floating gate. As a result, the write amount can be increased and decreased more efficiently than when only the control gate is used. Further, the potential around the semiconductor memory device can be stabilized, the threshold voltage Vt can be stabilized, and the writing operation can be performed without applying an electric field directly to the gate insulating film on the control gate. Therefore, deterioration of the gate insulating film can be suppressed.

For example, as an interlayer insulating film, a single-layer insulating film of an oxide film, a phosphorus glass film of a PSG film, a BPSG film, a SiN film or a TEOS film, or a SIN film-TEOS film -SOG film-TEOS
One of a composite insulating film of a film and a TEOS film-SOG film-TEOS film is used. Also, as shown in claim 4,
As the first and second gate insulating films, one or both of them are an oxide film-nitride film-oxide film, an oxide film-nitride film,
It can be composed of any of a nitride film and an oxide film.

According to the third aspect of the present invention, the semiconductor substrate is provided with a first semiconductor region (2) of the first conductivity type and a second semiconductor region (3) of the second conductivity type. A control gate is formed in the semiconductor region, a transistor portion is formed in the second semiconductor region, and a first trench (20) is formed between the first semiconductor region and the second semiconductor region. In addition, an insulating film (21) is disposed in the first trench, and the control gate and the transistor portion are insulated and separated. As described above, the control gate and the transistor portion can be separated from each other by the trench.

According to the present invention, a step of preparing a semiconductor substrate (1), a step of forming a control gate (4) comprising a diffusion layer of a first conductivity type on the semiconductor substrate, Forming a first conductive type first semiconductor region (2) so as to overlap the control gate, and forming a first gate insulating film (8) on the control gate; Forming a second gate insulating film (9), and a floating gate (1) made of a conductor layer on the control gate and the second semiconductor region via the first and second gate insulating films.
0), a second conductive type second semiconductor region (3), and a transistor portion including a first conductive type source (5) and a drain (6) in the second semiconductor region. Forming an interlayer insulating film (11) on the floating gate; and forming an interlayer insulating film (11) on the floating gate.
Forming a conductive film (13) so as to cover at least a part of the floating gate. The semiconductor memory device according to claim 1 can be manufactured by using such a manufacturing method.

Further, in the invention according to claim 9,
A step of preparing a semiconductor substrate (1); a step of forming a first conductivity type first semiconductor region (2) and a second conductivity type second semiconductor region (3) on the semiconductor substrate; Forming a first gate insulating film (8) in a predetermined region above the first semiconductor region; forming a second gate insulating film (9) on the second semiconductor region; A floating gate made of a conductor layer on the first semiconductor region and the second semiconductor region via a second gate insulating film;
Forming a first conductive type source (5) / drain (6) in the second semiconductor region; and forming the first semiconductor region below the first gate insulating film in the semiconductor substrate. Forming a control gate (4) made of a first conductivity type diffusion layer, forming an interlayer insulating film (11) on the floating gate, and forming at least an interlayer insulating film on the floating gate. And forming a conductive film (13) so as to cover a part of the floating gate. The semiconductor memory device according to claim 1 can be manufactured also by such a manufacturing method.

Further, in the invention according to claim 10, a step of preparing a semiconductor substrate (1), a step of forming a first semiconductor region (2) of a first conductivity type on the semiconductor substrate, and a step of preparing a second conductive region. Forming a second semiconductor region (3) of a mold type, so as to overlap the first semiconductor region of the semiconductor substrate;
Control gate (4) made of a diffusion layer of the first conductivity type
Forming a first gate insulating film (8) on the control gate; forming a second gate insulating film (9) on the second semiconductor region; Forming a floating gate made of a conductive layer on the control gate and the second semiconductor region via the second gate insulating film; and forming a source of the first conductivity type in the second semiconductor region. 5) a step of forming a drain (6) and an interlayer insulating film (1) on the floating gate;
Forming a conductive film (1) on the interlayer insulating film so as to cover at least a part of the floating gate;
Forming step 3). The semiconductor memory device according to claim 1 can be manufactured also by such a manufacturing method.

According to the eleventh aspect of the present invention, the first trench (20) is formed in the semiconductor substrate at a position between the first semiconductor region and the second semiconductor region, and the first trench is formed. By arranging the insulating film (21) inside,
The method is characterized by including a step of insulating and separating the first semiconductor region and the second semiconductor region. Thereby, Claim 3
Can be manufactured.

According to the inventions of claims 12 to 14, the semiconductor memory devices of claims 6 to 8 can be manufactured.

Note that the reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

[0021]

(First Embodiment) FIG. 1 shows an EPR as a semiconductor memory device to which an embodiment of the present invention is applied.
1 shows a basic configuration of an OM. FIG. 1A shows a layout configuration of an EPROM, and FIG.
2 shows a cross-sectional configuration. Hereinafter, the configuration of the EPROM according to the present embodiment will be described with reference to FIG.

As shown in FIG. 1, a semiconductor substrate 1 is provided with an n-type well layer (first semiconductor region) 2 and a p-type well layer (second semiconductor region) 3. A control gate 4 composed of a high-concentration n-type diffusion layer is provided on the n-type well layer 2 side, and a high-concentration n-type diffusion layer is disposed on the p-type well layer 3 side. The source 5 and the drain 6 that constitute the transistor portion thus formed are formed.

The n-type well layer 2 and the p-type well layer 3
A LOCOS oxide film 7 is formed on the
Element isolation is achieved by the COS oxide film 7. The LOCOS oxide film 7 has openings in a region including a part of the control gate 4 in the n-type well layer 2 and a region including the source 5 and the drain 6 in the p-type well layer 3. A gate insulating film 8 of the control gate 4 and a gate insulating film 9 of the transistor portion are formed in each of the portions where the LOCOS oxide film 7 is opened. These gate insulating films 8 and 9 are composed of, for example, an oxide film, an oxide film-nitride film-oxide film (ONO film), an oxide film-nitride film (ON film), and a nitride film-oxide film (NO film). ing.

Further, over the LOCOS oxide film 7,
A floating gate 10 is formed on both gate insulating films 8 and 9, and an insulating film 11 is formed to cover the floating gate 10. The insulating film 11
For example, an oxide film, a PSG film, a BPSG film, a TEOS film,
SIN film-TEOS film-SOG film-TEOS film, TEO
It is composed of an S film-SOG film-TEOS film. The control gate 4 is connected to the gate electrode 12 via a contact hole formed in the insulating film 11.

Further, an electrode 13 is formed on the insulating film 11. The electrode 13 is made of, for example, Al or the like, and is formed so as to partially or entirely cover the floating gate 10. Although not shown here, as shown in FIG. 3 described later, a protective film 14 is ultimately formed on the surface of the semiconductor substrate 1 including the electrodes 13.

In the EPROM configured as described above, when writing is performed, a voltage is applied to the drain 6 of the transistor section to generate hot carriers, and a voltage is applied to the control gate 4 to apply a voltage to the floating gate 10. Is performed to change the threshold voltage Vt of the transistor.

At this time, the potential of the electrode 13 disposed on the floating gate 10 is changed from the same potential as the control gate 4 to an arbitrary potential. Thus, the EPROM having the above configuration is represented by the equivalent circuit shown in FIG. However, _CFP is the floating gate 10 and the electrode 1
3, C _FL is the capacitance between floating gate 10 and n
The capacitance between the well layer 2 and the p-type well layer 3, _CFG is the capacitance between the floating gate 10 and the control gate 4, and _CFS is the floating gate 10 and the source 5
-It shows the capacitance between the drain 6.

Therefore, even if the potential of the control gate 4 remains the same, it is possible to arbitrarily adjust the write voltage by the voltage of the electrode 13 on the floating gate 10. That is, an electric field can be applied from above the floating gate 10 by the electrode 13, and writing can be performed from above and below the floating gate 10. Further, the parasitic capacitance around the floating gate can be reduced.

As a result, the write amount can be increased or decreased more efficiently than in the case where only the control gate 4 is used alone, and the write characteristics can be improved. Further, not only the potential around the EPROM can be stabilized and the threshold voltage Vt can be stabilized, but also the gate insulating film 8 on the control gate 4 can be stabilized.
Since the writing operation can be performed without applying an electric field directly to the gate insulating film 8, the deterioration of the gate insulating film 8 can be suppressed.

Further, since the floating gate 10 is partially or entirely covered by the electrode 13, the electrode 13 serves as a barrier film, so that the charge of the floating gate 10 can be prevented from being released, and the charge retention characteristics can be prevented. Can be improved.

Next, FIGS. 3 and 4 show the steps of manufacturing the EPROM according to the present embodiment.
A method for manufacturing M will be described.

First, a semiconductor substrate 1 is prepared. And
After masking a desired portion of the semiconductor substrate 1 with a photoresist or the like, an n-type impurity is ion-implanted and thermally diffused to form a control gate 4 as shown in FIG. Although the control gate 4 is formed by ion implantation here, solid-phase diffusion,
It may be formed by vapor phase diffusion, liquid phase diffusion, or the like.

Subsequently, the region where the n-type well layer 2 is to be formed and the region where the p-type well layer 3 is to be formed in the semiconductor substrate 1 are alternately masked with a photoresist or the like. By ion implantation, an n-type well layer 2 and a p-type well layer 3 are formed as shown in FIG.

After laminating an oxide film and a nitride film on the surface of the semiconductor substrate 1, a desired portion of the nitride film is opened and
As shown in FIG. 3C, a LOCOS oxide film 7 is formed on a desired portion of the semiconductor substrate 1 by a known LOCOS oxidation method of performing OCOS oxidation.

Next, as shown in FIG. 3D, an insulating film is formed on a portion of the semiconductor substrate 1 where the LOCOS oxide film 7 is opened, so that the p-type well layer 3 serving as a transistor portion is formed. Gate insulating films 8 and 9 are formed on the upper and control gates 4, and then a polysilicon film is formed on the semiconductor substrate 1 and the polysilicon film is patterned to form a floating gate 10. Furthermore, while covering a predetermined area with photoresist,
By performing ion implantation using the photoresist and the floating gate 10 as a mask, the source 5 and the drain 6 are formed in a self-aligned manner with respect to the floating gate 10.

The gate insulating films 8 and 9 may be oxide films formed by thermal oxidation, ONO films, NO
It may be a film or an ON film. Further, the gate insulating film 9 in the transistor portion and the gate insulating film 8 in the control gate 4 may not be the same insulating film, and may be any combination of the above-described insulating films.

Next, as shown in FIG. 4A, an interlayer insulating film 11 is formed on the surface of the semiconductor substrate 1 including over the floating gate 10. Thereafter, as shown in FIG. 4B, after forming a contact hole in the interlayer insulating film 11,
By forming an Al film and patterning the Al film, a gate electrode 12 connected to the control gate 4 is formed, and an electrode 13 is formed on the floating gate 10.

An EPROM is completed by forming a protective film 14 on the surface of the semiconductor substrate 1 including the electrodes 13 and the gate electrodes 12.

(Second Embodiment) FIGS. 5A to 5E show a manufacturing process of an EPROM according to a second embodiment of the present invention. In this embodiment, the EPROM manufacturing method is changed from that of the first embodiment, and the basic configuration of the EPROM is the same. Therefore, only different portions will be described here.

First, a semiconductor substrate 1 is prepared. And
A region where the n-type well layer 2 is to be formed in the semiconductor substrate 1 and p
As shown in FIG. 5A, the region where the formation of the well layer 3 is to be formed is alternately masked with a photoresist or the like, and a p-type impurity and an n-type impurity are ion-implanted, respectively. A p-type well layer 3 is formed.

Subsequently, as shown in FIG. 5B, a LOCOS oxide film 7 is formed on a desired portion of the semiconductor substrate 1 by a known LOCOS oxidation method.

Next, as shown in FIG. 5C, an insulating film is formed on a portion of the semiconductor substrate 1 where the LOCOS oxide film 7 is opened, so that the p-type well layer 3 serving as a transistor portion is formed. Gate insulating films 8 and 9 are formed on the upper and control gates 4, and then a polysilicon film is formed on the semiconductor substrate 1 and the polysilicon film is patterned to form a floating gate 10. Thereafter, the source 5 and the drain 6 are formed by the same method as in FIG.

After masking a desired portion of the semiconductor substrate 1 with a photoresist or the like, an n-type impurity is ion-implanted into the n-type well layer 2 and thermally diffused, so that the semiconductor device shown in FIG.
As shown in (d), the control gate 4 is formed.

Thereafter, FIG. 4A shown in the first embodiment is used.
By performing the same steps as in (c), an EPROM is completed.
As described above, the step of forming the control gate 4 may be performed after the formation of the floating gate 10.

By doing so, the control gate 4
Before the formation of the gate insulating films 8, 9 and the polysilicon film (floating gate 10),
The number of heat treatments performed after forming the control gate 4 is reduced, and the heat diffusion distance of the control gate 4 can be reduced. As a result, the distance between the control gate 4 and the transistor portion, which is set in consideration of the heat diffusion distance of the control gate 4, can be reduced, and the device can be downsized by downsizing the EPROM alone. .

(Third Embodiment) FIG. 6 shows a process of manufacturing an EPROM according to a third embodiment of the present invention. In the present embodiment, the EPROM manufacturing method is changed from that of the second embodiment, and the basic configuration of the EPROM is the same. Therefore, only different portions will be described here.

First, the steps shown in FIGS. 6A and 6B are performed. This step is the same as the step shown in FIGS. 5A and 5B of the second embodiment.

Next, after masking a desired portion of the semiconductor substrate 1 with a photoresist or the like, an n-type impurity is ion-implanted into the n-type well layer 2 and thermally diffused, thereby obtaining a structure shown in FIG.
As shown in (c), the control gate 4 is formed.

Then, as shown in FIG. 6D, an insulating film is formed on a portion of the semiconductor substrate 1 where the LOCOS oxide film is opened, so that the p-type well layer 3 serving as a transistor portion and A floating gate 10 is formed by forming a gate insulating film on the control gate 4 and then forming a polysilicon film on the semiconductor substrate 1 and patterning the polysilicon film.

As described above, the order of the steps of forming the floating gate 10 and the control gate 4 may be interchanged with respect to the second embodiment.

(Fourth Embodiment) FIGS. 7 and 8 show a manufacturing process of an EPROM according to a fourth embodiment of the present invention. In this embodiment, the EPROM manufacturing method is changed from that of the first embodiment, and the basic configuration of the EPROM is the same. Therefore, only different portions will be described here.

First, as shown in FIG. 7A, a trench (first trench) 20 is formed in the semiconductor substrate 1 by photoetching, and then the trench 20 is filled with an insulating film 21 to obtain n. The region where the p-type well layer 3 is to be formed and the region where the p-type well layer 3 is to be formed are
To separate elements. Insulating film 2 in trench 20
The burying of 1 is performed by, for example, forming an oxide film by thermally oxidizing the inner wall of the trench 20 and then filling the trench with a polysilicon layer. continue,
The control gate 4 is formed by performing the same steps as in FIG. 3A in the first embodiment.

Then, the steps shown in FIGS.
8 (a) to 8 (c). These steps are the same as the steps shown in FIGS. 3B to 3D and 4A to 4C in the first embodiment.

As a result, an EPROM in which the n-type well layer 2 side and the p-type well layer 3 side are trench-isolated from the first embodiment is completed. As described above, the n-type well layer 2 side and the p-type well layer 3 side may be separated from each other by the trench 20.

(Fifth Embodiment) FIGS. 9 and 10 show a manufacturing process of an EPROM according to a fifth embodiment of the present invention. In this embodiment, the EPROM manufacturing method is changed from that of the first embodiment, and the basic configuration of the EPROM is the same. Therefore, only different portions will be described here.

First, the step shown in FIG. 9A is performed. This step is the same as the step shown in FIGS. 3A and 3B in the first embodiment. Subsequently, the step shown in FIG. 9B is performed. This step is the same as the step shown in FIG. 3C in the first embodiment.

Then, as shown in FIG. 9C, a trench (second trench) 25 is formed in the control gate 4 by photoetching. After this, FIG.
10D, a gate insulating film is formed up to the inside of the trench 25, and the floating gate 10 is formed so that the inside of the trench 25 is buried.
The step shown in (c) is performed. These FIGS. 10 (a) to 10 (c)
4A to 4C in the first embodiment.
This is the same as the step shown in (c).

As a result, an EPROM in which the gate insulating film and the floating gate 10 extend to the inside of the control gate 4 as compared with the first embodiment is completed. Thus, the floating gate 10 may be extended to the inside of the control gate 4.

(Sixth Embodiment) FIGS. 11 and 12 show a manufacturing process of an EPROM according to a sixth embodiment of the present invention.
This embodiment is different from the third embodiment in that the EPROM
Since the basic method of the EPROM is the same, only different parts will be described here.

First, the steps shown in FIGS. 11A and 11B are performed. These steps correspond to FIG. 6 in the third embodiment.
This is the same as (a) and (b). Subsequently, as shown in FIG. 11C, a trench (second trench) 30 is formed in a region where the control gate 4 is to be formed in the n-type well region by photoetching.

Next, after masking a desired portion of the semiconductor substrate 1 with a photoresist or the like, an n-type impurity is ion-implanted into the n-type well layer 2 and thermally diffused.
As shown in (d), the control gate 4 is formed. Here, the control gate 4 is formed by ion implantation, but may be formed by solid phase diffusion, gas phase diffusion, or liquid phase diffusion as described above.

Then, as shown in FIG. 12A, the gate insulating film 8 is formed up to the trench 30 and the floating gate 10 is formed so that the trench 30 is buried. ) To (d) are performed. The steps in FIGS. 12B to 12D are the same as the steps shown in FIGS. 4A to 4C in the first embodiment.

As a result, an EPROM having the control gate 4 formed by diffusing the n-type diffusion layer by a predetermined width around the trench 30 and having the floating gate 10 extended in the trench 30 is completed. Thus, the control gate 4 may be formed using the trench 30. At this time, the trench 3
Alternatively, the floating gate 10 may be set to extend in the area 0.

(Seventh Embodiment) FIGS. 13A to 13C show the steps of manufacturing an EPROM according to a seventh embodiment of the present invention. In this embodiment, the EPROM manufacturing method is changed from that of the first embodiment, and the basic configuration of the EPROM is the same. Therefore, only different portions will be described here.

First, FIGS. 3A to 3C shown in the first embodiment.
The step shown in (c) is performed. Then, as shown in FIG. 13A, an insulating film 40 is formed on the surface of the floating gate 10.
Is formed, a polysilicon film is further formed on the insulating film 40, and the polysilicon film is patterned to form an electrode layer 41 on the floating gate 10.

Thereafter, as shown in FIG. 13B, an interlayer insulating film 11 is formed on the surface of the semiconductor substrate 1 including the upper part of the floating gate 10, and a contact hole is formed in the interlayer insulating film 11. By forming an Al film on the interlayer insulating film 11 and patterning the Al film, a gate electrode 12 connected to the control gate 4 is formed, and the floating gate 10 is formed.
The electrode 13 connected to the electrode layer 41 on the top is formed.

Then, the step shown in FIG. 13C, that is, the same step as FIG. 4C in the first embodiment is performed. Thus, the EPROM in which the electrode layer 41 is formed on the floating gate 10 via the insulating film and the electrode 13 is formed on the electrode layer 41 via the insulating film is completed. As described above, a configuration in which another electrode layer is formed on the floating gate 10 may be employed.

(Other Embodiments) Although the fourth and seventh embodiments have been described as modified examples of the first embodiment, they can be applied to the second and third embodiments. it can. Although the fifth embodiment has been described as a modification of the first embodiment, the fifth embodiment can be applied to the third embodiment.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of an EPROM according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the EPROM shown in FIG.

FIG. 3 is a view showing a manufacturing process of the EPROM shown in FIG. 1;

FIG. 4 is a view showing a manufacturing process of the EPROM following FIG. 3;

FIG. 5 is a diagram showing a manufacturing process of an EPROM according to a second embodiment of the present invention.

FIG. 6 is a view showing a process of manufacturing an EPROM according to a third embodiment of the present invention.

FIG. 7 is a view showing a manufacturing process of an EPROM according to a fourth embodiment of the present invention.

FIG. 8 is a view showing a manufacturing process of the EPROM following FIG. 7;

FIG. 9 is a diagram showing a manufacturing process of an EPROM according to a fifth embodiment of the present invention.

FIG. 10 is a view showing a manufacturing process of the EPROM following FIG. 9;

FIG. 11 is a view showing a manufacturing process of an EPROM according to a sixth embodiment of the present invention.

FIG. 12 is a view showing a manufacturing process of the EPROM following FIG. 11;

FIG. 13 is a view illustrating a process of manufacturing an EPROM according to a seventh embodiment of the present invention.

FIG. 14 is a diagram showing an overall configuration of a conventional EPROM.

15 is an equivalent circuit diagram of the EPROM shown in FIG.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate, 2 n-type well layer, 3 p-type well layer, 4 control gate, 5 source, 6 drain, 7 LOCOS oxide film, 8, 9 gate insulating film, 1
0: floating gate, 11: correlation insulating film, 12:
Gate electrode, 13 ... electrode.

Claims (14)

[Claims] A control gate formed of a diffusion layer formed on a surface portion of a semiconductor substrate; a first gate insulating film formed on the control gate; A transistor portion having a source (5) and a drain (6) formed on a surface portion of a substrate; a second gate insulating film (9) formed on the portion between the source and the drain; A floating gate (10) made of a conductor layer formed on the control gate and the transistor section via a gate insulating film of (2); and an interlayer insulating film (11) formed on the floating gate. A conductive film (13) formed on the interlayer insulating film and covering at least a part of the floating gate. Storage device. 2. The method according to claim 1, wherein the interlayer insulating film is an oxide film, a PSG film,
Phosphorus glass film of BPSG film, SiN film, or TEO
Single-layer insulating film of S film, or SIN film-TEOS film-S
OG film-TEOS film, TEOS film-SOG film-TEOS
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is one of a composite insulating film. 3. The semiconductor device according to claim 1, wherein the semiconductor substrate has a first conductivity type.
Semiconductor region (2) and second semiconductor region of second conductivity type (3)
Wherein the control gate is formed in the first semiconductor region, and the transistor portion is formed in the second semiconductor region. Further, a portion between the first semiconductor region and the second semiconductor region is provided. Wherein a first trench (20) is formed, an insulating film (21) is disposed in the first trench, and the control gate and the transistor portion are insulated from each other. The semiconductor memory device according to claim 1. 4. The first and second gate insulating films, one or both of which are a single-layer insulating film of an oxide film or a nitride film, an oxide film-nitride film-oxide film, an oxide film-nitride film,
4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed of one of a composite insulating film of a nitride film and an oxide film. 5. A second trench (25, 3) in a region of the semiconductor substrate where the control gate is formed.
0) is formed.
The semiconductor memory device according to any one of the above. 6. The floating gate according to claim 2, wherein:
6. The semiconductor memory device according to claim 5, wherein the semiconductor memory device extends into the trench. 7. The semiconductor memory device according to claim 5, wherein said control gate is formed to have a predetermined width from an end face of said second trench. 8. A step of preparing a semiconductor substrate (1), a step of forming a control gate (4) made of a first conductivity type diffusion layer on the semiconductor substrate, and overlapping the control gate on the semiconductor substrate. Forming a first semiconductor region (2) of the first conductivity type and a second semiconductor region (3) of the second conductivity type as described above; and forming a first gate insulating film ( 8); forming a second gate insulating film (9) on the second semiconductor region; and interposing the control gate and the control gate via the first and second gate insulating films. Forming a floating gate made of a conductive layer on the second semiconductor region; and forming a transistor portion including a source and drain of a first conductivity type in the second semiconductor region. Work Forming an interlayer insulating film (11) on the floating gate; and forming a conductive film (13) on the interlayer insulating film so as to cover at least a part of the floating gate. And a method for manufacturing a semiconductor memory device. 9. A step of preparing a semiconductor substrate (1), wherein a first conductivity type first semiconductor region (2) is provided on the semiconductor substrate.
And a second semiconductor region of the second conductivity type (3).
Forming a first gate insulating film (8) in a predetermined region above the first semiconductor region; and forming a second gate insulating film (9) on the second semiconductor region. Forming a floating gate (10) made of a conductor layer on the first semiconductor region and the second semiconductor region via the first and second gate insulating films; Forming a source (5) and a drain (6) of the first conductivity type in the two semiconductor regions; Forming a control gate (4) comprising a diffusion layer of the first conductivity type; forming an interlayer insulating film (11) on the floating gate; and forming at least the floating film on the interlayer insulating film. Get Forming a conductive film (13) so as to cover a part of the semiconductor memory device. 10. A step of preparing a semiconductor substrate (1), wherein a first conductivity type first semiconductor region (2) is provided on the semiconductor substrate.
And a second semiconductor region of the second conductivity type (3).
Forming a control gate (4) made of a diffusion layer of a first conductivity type so as to overlap with the first semiconductor region in the semiconductor substrate; and forming a first control gate on the control gate. Forming a gate insulating film (8); forming a second gate insulating film (9) on the second semiconductor region; interposing the first and second gate insulating films; Forming a floating gate made of a conductive layer on the control gate and the second semiconductor region; forming a source (5) and a drain (6) of a first conductivity type in the second semiconductor region; Forming an interlayer insulating film (11) on the floating gate; and forming a conductive film (13) on the interlayer insulating film so as to cover at least a part of the floating gate. A method of manufacturing a semiconductor memory device. 11. A first trench (20) is formed in the semiconductor substrate at a position between the first semiconductor region and the second semiconductor region, and an insulating film (20) is formed in the first trench. 11. The semiconductor memory device according to claim 8, further comprising a step of insulating and separating the first semiconductor region and the second semiconductor region by disposing 21). 12. 12. A second trench in a region of the semiconductor substrate where the control gate is formed.
11. The method according to claim 8, further comprising the step of forming (30). 13. The step of forming the second trench is performed before the step of forming the floating gate,
13. The method according to claim 12, wherein in the step of forming the floating gate, the floating gate is extended in the second trench. 14. The step of forming the second trench is performed before the step of forming the control gate. In the step of forming the control gate, a first conductivity type impurity is diffused from the second trench. 14. The method according to claim 12, wherein the control gate is formed.