JP2002158287A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which the cell size is smaller than before by omitting a wasteful region within a standard cell. SOLUTION: The semiconductor integrated circuit comprises an N well 1 and P well 2 formed in a semiconductor substrate, a power supply potential wiring 50 formed on the N well 1, a power supply potential wiring 60 formed on the P well 2, P channel transistors QP1 and QP2 formed in the N well 1, N channel transistors QN1 and QN2 formed in the P well 2, an NAND cell 10 comprising a tap 109 formed in the P well 2, and an NOR cell comprising a tap formed in the N well 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit constituted by standard cells.

[0002]

2. Description of the Related Art Standard cells used in conventional semiconductor integrated circuits include NAND cells and N cells.
This will be described using an OR cell as an example.

FIG. 6 is a circuit diagram of a general two-input NAND circuit. FIG. 7 is a layout diagram of a NAND cell in a conventional semiconductor integrated circuit. NAN of FIG.
The D cells constitute the NAND circuit shown in FIG. Note that the insulating film is omitted in FIG. As shown in FIG. 7, the NAND cell 110 includes P-channel transistors QP1 and QP2 formed in the N well 1,
N-channel transistor QN formed in P well 2
1 and QN2, a power supply potential supply line 50 made of aluminum or the like for supplying a first power supply potential V _DD formed on the N well 1 via an insulation film, and an insulation film on the P well 2 via an insulation film. It includes a power supply potential supply line 60 made of aluminum or the like for supplying a first power supply potential V _SS (here, a ground potential), and two input lines 307 and 308. Here, the input line 307 corresponds to the input IN1 of the NAND circuit shown in FIG. 6, and the input line 308 is the NA shown in FIG.
This corresponds to the input IN2 of the ND circuit.

The transistors QP1 and QP2 are connected in parallel so that the drains are common. The common drain of the transistors QP1 and QP2
3 is connected to a wiring 304 made of aluminum or the like. The source of the transistor QP <b> 1 is connected to the power supply line 50 by a contact 301. Similarly, the source of the transistor QP2 is connected to the power supply potential supply line 50 by a contact 302.

On the other hand, transistors QN1 and QN2 are
The source of the transistor QN1 and the drain of the transistor QN2 are connected in series so as to be common. The drain of the transistor QN1 is connected to the wiring 304 by a contact 305. Also, the transistor QN
The source 2 is connected to the power supply line 60 by a contact 306. The output signal of the NAND cell 110 is supplied to the wiring 304.

The gate electrode of transistor QP1 and the gate electrode of transistor QN1 are connected to each other to form input line 307. The gate electrode of the transistor QP2 and the gate electrode of the transistor QN2 are connected to each other to form an input line 308.

A tap 309 formed in the N well 1 so as to be adjacent to the transistor QP 1 is connected to the power supply potential supply line 50. As a result, the first power supply potential _VDD is supplied to the N-well 1 from the power supply potential supply wiring 50. Further, a tap 310 formed in the P well 2 so as to be adjacent to the transistor QN1 is connected to the power supply potential supply line 60. As a result, the P-well 2 receives the second power supply potential V _SS from the power supply potential supply line 60.
Is supplied.

Here, the transistors QP connected in parallel
1 and QP2 are longer in the X-axis direction by the amount of the contact 303 than the transistors QN1 and QN2 connected in series. Therefore, the NAND cell 11
The size of 0 was determined by the transistors QP1 and QP2 and the tap 309.

FIG. 8 is a circuit diagram of a general two-input NOR circuit. FIG. 9 is a layout diagram of a NOR cell in a conventional semiconductor integrated circuit. The NOR cell of FIG. 9 forms the NOR circuit shown in FIG. Note that FIG.
, The insulating film is omitted. As shown in FIG. 9, the NOR cell 120 includes a P cell formed in the N well 1.
Channel transistors QP3 and QP4 and P-well 2
N-channel transistors QN3 and QN formed in
4, a power supply potential supply line 50 formed on the N-well with an insulating film interposed therebetween to supply a first power supply potential V _DD ,
A power supply potential supply line 60 formed on the P-well with an insulating film interposed therebetween to supply a second power supply potential V _SS (here, a ground potential) and two input lines 407 and 408 are included. I have. Here, the input line 407 is the NOR shown in FIG.
The input line 408 corresponds to the input IN3 of the circuit shown in FIG.
This corresponds to the input IN4 of the OR circuit.

The transistors QP3 and QP4 are connected in series such that the drain of the transistor QP3 and the source of the transistor QP4 are common. The source of the transistor QP3 is connected to the power supply potential supply line 50 by a contact 401. The drain of the transistor QP4 is connected to a wiring 403 of aluminum or the like by a contact 402.

The transistors QN3 and QN4 are connected in parallel so that the drains are common. The common drain of the transistors QN3 and QN4
4 are connected to the wiring 403. Further, the source of the transistor QN3 is connected to the power supply potential supply line 60 by a contact 406. Similarly, the source of the transistor QN4 is connected to the power supply line 60 by a contact 405. NOR cell 12
The output signal of 0 is supplied to the wiring 403.

The gate electrode of transistor QP3 and the gate electrode of transistor QN3 are connected to each other to form input line 407. The gate electrode of transistor QP4 and the gate electrode of transistor QN4 are connected to each other to form input line 408.

A tap 409 formed in the N well 1 so as to be adjacent to the transistor QP4 is connected to the power supply line 50. As a result, the first power supply potential _VDD is supplied to the N-well 1 from the power supply potential supply wiring 50. Further, a tap 410 formed in the P well 2 so as to be adjacent to the transistor QN4 is connected to the power supply potential supply line 60. As a result, the P-well 2 receives the second power supply potential V _SS from the power supply potential supply line 60.
Is supplied.

Here, the transistor QN connected in parallel
3 and QN4 are longer in the X-axis direction by the amount of the contact 404 than the transistors QP3 and QP4 connected in series. Therefore, NOR cell 120
Is determined by the transistors QN3 and QN4 and the tap 410.

[0015]

As described above, in the conventional standard cell, the N-well has the first power supply potential V _DD.
, And a tap for supplying the second ground potential V _SS to the P-well. In addition, the area of the element formed in the N well and the area of the element formed in the P well are determined by the difference in connection state, such as whether the transistors are connected in parallel or in series, or the P-channel transistor and the N-channel transistor. Differences occur due to differences in size between the two, and differences in wiring layout. Therefore, if the cell size is determined by adding the tap region to the well in which the area of the element to be formed is large, there is a problem that a useless region occurs in the standard cell and the cell size becomes unnecessarily large. Was.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a semiconductor integrated circuit having a smaller cell size than conventional ones by eliminating useless areas in a standard cell.

[0017]

In order to solve the above problems, a semiconductor integrated circuit according to the present invention comprises a semiconductor substrate, an N well formed in the semiconductor substrate, and an insulating film formed on the N well via an insulating film. A first power supply potential supply line formed in the longitudinal direction of the N well and a semiconductor substrate or a P well formed in the semiconductor substrate are formed in parallel with the first power supply potential supply line via an insulating film. A first group of cells including a second power supply potential supply line, a P-channel transistor formed in an N-well, and an N-channel transistor formed in a semiconductor substrate or a P-well, wherein the N-well is a first cell. A first group of cells having a first tap connected to the second power supply potential supply line, and not having a second tap connecting the semiconductor substrate or the P-well to the second power supply potential supply line; P channel formed on A second group of cells including a transistor and an N-channel transistor formed in a semiconductor substrate or a P well, the second group of cells having a second tap and not having a first tap. Have.

Further, the semiconductor integrated circuit according to the present invention comprises:
A third group of cells including a P-channel transistor formed in an N-well and an N-channel transistor formed in a semiconductor substrate or a P-well, wherein the third group of cells has neither a first tap nor a second tap. It may include three groups of cells.

In the above, one of the cells of the first group is formed in the N-well in parallel with the first power supply line, and one source and the other drain are common. P-channel transistors connected in series as described above, and a plurality of N-channel transistors formed in the semiconductor substrate or P-well in parallel with the second power supply line and connected in parallel so that the drain is common It may include a transistor and a tap formed in the N well adjacent to one of the plurality of P-channel transistors and connected to the first power supply potential supply line.

Here, one of the cells in the first group is composed of K N-channel transistors whose drains are connected to each other and whose source is connected to the second power supply line (where K is 2 or more). ), K P-channel transistors connected in series between the first power supply potential supply line and the drains of the K N-channel transistors, each having a gate electrode of one N-channel transistor and one It may be a NOR cell including K inputs forming a gate electrode of a P-channel transistor.

Also, one of the cells of the second group is
A plurality of P-channel transistors formed in the N-well in parallel with the first power supply potential supply line and connected in parallel with a common drain, and a second power supply potential supply in the semiconductor substrate or the P-well; A plurality of N-channel transistors formed in parallel with the wiring and connected in series so that one source and the other drain are common; and a semiconductor substrate or one adjacent to one of the plurality of N-channel transistors. And a tap formed in the P-well and connected to the second power supply potential supply line.

Here, one of the cells of the second group is composed of L P-channel transistors whose sources are connected to the first power supply potential supply line and whose drains are connected to each other (where L is 2 or more). ), L N-channel transistors connected in series between the drains of the L P-channel transistors and the second power supply potential supply line, each having a gate electrode of one P-channel transistor and one It may be a NAND cell including L inputs connected to the gate electrode of an N-channel transistor.

Alternatively, one of the cells of the first group includes at least one P-channel transistor having an impurity diffusion region formed in an N well and an impurity diffusion region formed in a semiconductor substrate or a P well. And at least one N-channel transistor having a region, wherein the impurity diffusion region of the at least one P-channel transistor is larger than the impurity diffusion region of the at least one N-channel transistor.

Also, one of the cells of the first group is
At least one n-channel transistor including at least one p-channel transistor having an impurity diffusion region formed in an n-well and at least one n-channel transistor having an impurity diffusion region formed in a semiconductor substrate or a p-well; The area of the wiring connected to the transistor may be larger than the area of the wiring connected to at least one P-channel transistor.

According to the semiconductor integrated circuit of the present invention configured as described above, only the N-well tap is formed in the first group of cells, and only the P-well tap is formed in the second group of cells. By doing so, the useless area in the cell standard cell can be omitted, and the cell size can be made smaller than before.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. The same components are denoted by the same reference numerals, and description thereof will be omitted.

First, a first embodiment of the present invention will be described. The semiconductor integrated circuit according to the first embodiment of the present invention is configured using a plurality of P-channel transistors formed in the same N-well and a plurality of N-channel transistors formed in the same P-well. Including NAND cells and NOR cells. Alternatively, the P-well may be omitted and the N-channel transistor may be formed directly in the semiconductor substrate.

FIG. 1 is a layout diagram of a NAND cell included in the semiconductor integrated circuit according to the present embodiment. 1 constitutes the NAND circuit shown in FIG. In FIG. 1, the insulating film is omitted.
As shown in FIG. 1, an N well 1 and a P well are provided in a semiconductor substrate.
Well 2 is formed. The NAND cell 10 has N
P-channel transistor QP1 formed in well 1
And QP2, N-channel transistors QN1 and QN2 formed in the P well 2, and a power supply potential such as aluminum formed on the N well 1 through an insulating film to supply a first power supply potential V _DD. A second power supply potential V is formed on the supply wiring 50 and the P well 2 via an insulating film.
A power supply potential supply line 60 made of aluminum or the like for supplying _SS (here, ground potential) and two input lines 10
7 and 108. Here, the input line 107 corresponds to the NAND circuit input IN1 shown in FIG.
8 corresponds to the NAND circuit input IN2 shown in FIG.

The transistors QP1 and QP2 are connected in parallel so that the drains are common. The common drain of the transistors QP1 and QP2
3 is connected to a wiring 104 made of aluminum or the like. Further, the source of the transistor QP1 is connected to the power supply potential supply line 50 by a contact 101. Similarly, the source of the transistor QP2 is connected to the power supply line 50 by a contact 102.

The transistors QN1 and QN2 are connected in series such that the source of the transistor QN1 and the drain of the transistor QN2 are common. The drain of the transistor QN1 is connected to the wiring 104 by a contact 105. Further, the source of the transistor QN2 is connected to the power supply line 60 by a contact 106. The output signal of the NAND cell 10 is supplied to the wiring 104.

The gate electrode of transistor QP1 and the gate electrode of transistor QN1 are connected to each other to form input line 107. The gate electrode of the transistor QP2 and the gate electrode of the transistor QN2 are connected to each other to form the input line 108.

A tap 109 formed in the P well 2 so as to be adjacent to the transistor QN1 is connected to the power supply potential supply line 60. As a result, the second power supply potential _VSS is supplied to the P well 2 from the power supply line 60 via the tap 109 of the NAND cell.

Here, when the NAND cell 10 in the present embodiment is compared with the conventional NAND cell 110 (FIG. 7), a tap corresponding to the tap 309 of the conventional NAND cell 110 is included in the NAND cell 10 in the present embodiment. Not provided. Therefore, the length of the NAND cell 10 in the X-axis direction is determined by the transistors 109 and QN2 and the tap 109 connected in series. Therefore, the NAND included in the semiconductor device according to the present embodiment
In the cell 10, the length in the X-axis direction can be reduced by the amount of the contact 303 as compared with the conventional NAND cell 110, and the cell size can be reduced.

FIG. 2 is a layout diagram of a NOR cell included in the semiconductor integrated circuit according to the present embodiment. N in FIG.
The OR cells constitute the NOR circuit shown in FIG. In FIG. 2, the insulating film is omitted. As shown in FIG. 2, an N well 1 and a P well 2 are formed in a semiconductor substrate. NOR cell 20 has N well 1
P-channel transistors QP3 and QP formed in
4, N-channel transistors QN3 and QN4 formed in the P well 2, and a power supply potential such as aluminum formed on the N well 1 via an insulating film to supply a first power supply potential V _DD. A power supply potential supply line 60 made of aluminum or the like for forming a wiring 50, a second power supply potential V _SS (here, a ground potential) formed on the P well 2 via an insulating film, and two inputs; Lines 207 and 208
And Here, the input line 207 is N
The input line 208 corresponds to the input IN4 of the NOR circuit shown in FIG.

The transistors QP3 and QP4 are connected in series such that the drain of the transistor QP3 and the source of the transistor QP4 are common. In addition, the source of the transistor QP3 is connected to the power supply potential supply line 50 by a contact 201. Further, the drain of the transistor QP4 is connected to a wiring 203 of aluminum or the like by a contact 202.

The transistors QN3 and QN4 are connected in parallel so that the drains are common. The common drain of transistors QN3 and QN4 is connected to contact 20
4 are connected to the wiring 203. In addition, the source of the transistor QN3 is connected to the power supply potential supply line 60 by a contact 206. Similarly, the source of the transistor QN4 is connected to the power supply line 60 by a contact 205. NOR cell 20
Is supplied to the wiring 203.

The gate electrode of transistor QP3 and the gate electrode of transistor QN3 are connected to each other to form input line 207. The gate electrodes of the transistor QP4 and the transistor QN4 are connected to each other to form an input line 208.

A tap 209 formed in the N well 1 so as to be adjacent to the transistor QP4 is connected to the power supply line 50. As a result, the first power supply potential _VDD is supplied to the N well 1 from the power supply wiring 50 via the tap 209 of the NOR cell.

Here, the NOR cell 2 in the present embodiment
When 0 is compared with the conventional NOR cell 120 (FIG. 9), a tap corresponding to the tap 410 of the conventional NOR cell 120 is not provided in the NOR cell 20 in the present embodiment. Therefore, the length of the NOR cell 20 in the X-axis direction is determined by the transistors QP3 and QP4 connected in series and the tap 209. Therefore, in the NOR cell 20 according to the present embodiment, the conventional NOR cell
The length in the X-axis direction can be shorter than the cell 120 by the contact 404, and the cell size can be reduced.

The NAND cell 10 alone shown in FIG. 1 cannot supply the first power supply potential to the N well,
In the case of the NOR cell 20 alone shown in FIG.
Power supply potential cannot be supplied. However, in the same N well and the same P well, the N
By forming at least one AND cell and one NOR cell, the first and second power supply potentials are supplied to each well.

Further, in the same N well and the same P well, the tap 109 shown in FIG.
It is also possible to form a standard cell having no 09. By combining these three types of standard cells, at least one cell per predetermined area of each well is obtained.
It is desirable to dispose one tap and cover each well with a tap effective area represented by a circle having a predetermined radius (for example, 15 μm) from the center of the tap.

Next, a second embodiment of the present invention will be described. The semiconductor integrated circuit according to the second embodiment of the present invention is configured using a plurality of P-channel transistors formed in the same N-well and a plurality of N-channel transistors formed in the same P-well. Including a plurality of standard cells. Alternatively, omit the P-well and
The channel transistor may be formed directly in the semiconductor substrate.

FIG. 3 is a circuit diagram showing two inverter circuits included in a semiconductor integrated circuit according to the second embodiment of the present invention. As shown in FIG. 3, the semiconductor integrated circuit according to the present embodiment includes a first inverter circuit including a P-channel transistor QP5 and an N-channel transistor QN5, and a P-channel transistor QP6 and a N-channel transistor NP.
A second inverter circuit constituted by a channel transistor QN6.

[0044] Here, between the drain current I _N of the drain current I _P and N-channel MOS transistor of P-channel MOS transistor, the following relationship. I _P = I _N (1) The drain current I _P of the P-channel transistor is represented by the following equation.

(Equation 1) On the other hand, the drain current I _N of the N-channel transistor is expressed by the following equation.

(Equation 2) In the above, β _P is the gain coefficient of the P-channel transistor, β _N is the gain coefficient of the N-channel transistor, _VL is the input threshold potential (logic level) of the inverter circuit, and V
_TP represents a threshold voltage of a P-channel transistor, and V _TN represents a threshold voltage of an N-channel transistor.

The gain coefficient β _P of the P-channel transistor is expressed by the following equation.

(Equation 3) On the other hand, the gain coefficient β _N of the N-channel transistor is expressed by the following equation.

(Equation 4) Where W _P is the channel width of the P-channel transistor,
L _P represents the channel length of the P-channel transistor, W _N represents the channel width of the N-channel transistor, and L _N represents the channel length of the N-channel transistor. Μ _P is the hole mobility, μ _N is the electron mobility, C _P is the capacitance of the gate insulating film per unit area of the P-channel transistor, and C _N is the gate insulating film per unit area of the N-channel transistor. Represents the capacity of

In general, the electron mobility μ _N is 3 to 4 times the hole mobility μ _P. Therefore, when the capacitance, channel width, and channel length of the gate insulating film per unit area of the P-channel transistor and the N-channel transistor are equal, the gain of the N-channel transistor is obtained from the expressions (4) and (5). The coefficient β _N becomes larger than the gain coefficient β _P of the P-channel transistor. Therefore,
From the equations (2) and (3), the logic level _VL of the inverter circuit is determined as the midpoint potential (V _DD + V _SS ) / two power supply potentials.
2, the drain current I _N of the N-channel transistor is equal to the drain current I _{P of the} P-channel transistor.
It can be seen that the value is larger than.

However, since equation (1) holds, P channel
Drain current I _PAnd N-channel tiger
Transistor drain current I_NMust be equal
You. The logic level V of the inverter circuit at that time
_LIs represented by the following equation.

(Equation 5) According to equation (6), the logic level V of the inverter circuit
_L is closer to the V _SS side than the midpoint potential (V _DD + V _SS ) / 2 of the two power supply potentials.

To solve this problem, in the inverter circuit included in the semiconductor integrated circuit according to the present embodiment, the ratio W between the channel width W and the channel length L between the P-channel transistor and the N-channel transistor is set. By making / L different, the logic level _VL of the inverter circuit approaches the midpoint between the two power supply potentials.

FIG. 4 is a layout diagram of a standard cell included in the semiconductor integrated circuit according to the present embodiment. 4 constitutes the two inverter circuits shown in FIG. Note that the insulating film is omitted in FIG. As shown in FIG. 4, in the semiconductor substrate,
An N well 11 and a P well 12 are formed. The cell 30 includes P-channel transistors QP5 and QP6 formed in the N-well 11, N-channel transistors QN5 and QN6 formed in the P-well 12, and an insulating film formed on the N-well 11, 1 power supply potential V
A power potential supply line 51 of aluminum or the like for supplying _DD, is formed through an insulating film on the P-well 11, a power supply potential supply line 61 of aluminum or the like for supplying a second power supply potential V _SS Two input lines 151 and 152
And two output lines 153 and 154.

The common source of the transistors QP5 and QP6 is connected to the power supply line 51 by a contact. The drain of the transistor QP5 is connected to the output line 153 by a contact. Also,
The drain of the transistor QP6 is connected to the output line 154 by a contact.

The common source of the transistors QN5 and QN6 is connected to the power supply potential supply line 61 by a contact. The drain of the transistor QN5 is connected to the output line 153 by a contact. The drain of the transistor QN6 is
It is connected to the output line 154.

The gate electrode of transistor QP5 and the gate electrode of transistor QN5 are connected to each other to form input line 151 of the first inverter circuit. Also,
The gate electrode of the transistor QP6 and the transistor QN6
Are connected to each other to form an input line 152 of the second inverter circuit. An output signal of the first inverter circuit is supplied to an output line 153. The output signal of the second inverter circuit is supplied to an output line 154.

Here, the channel width of the N-channel transistors QN5 and QN6 formed in the P-well 12 is
P-channel transistor Q formed in N well 11
It is smaller than the channel width of P5 and QP6. For this reason, the extra space in the P well 12
55 can be formed. Transistor QN5
And a tap 155 formed in the P well 12 so as to be adjacent to the power supply potential supply wiring 61. Through the tap 155, the P well 12
A second power supply potential V _SS is supplied from the power supply potential supply wiring 61.

Next, a third embodiment of the present invention will be described. FIG. 5 is a layout diagram of a standard cell included in the semiconductor integrated circuit according to the present embodiment. The standard cell shown in FIG. 5 also has two inverter circuits shown in FIG. 3, similarly to the standard cell shown in FIG. However, in the present embodiment, since many wirings are formed on the P well, taps are not formed in the P well, and conversely, taps are formed in the N well.
Note that the insulating film is omitted in FIG.

As shown in FIG. 5, an N well 11 and a P well 12 are formed in a semiconductor substrate. Cell 40
Are the P-channel transistors QP5 and QP6 formed in the N-well 11 and the N-channel transistors QP5 and QP6 formed in the P-well 12.
Channel transistors QN5 and QN6 and N well 1
And a power supply potential supply line 51 made of aluminum or the like for supplying a first power supply potential _VDD.
A power supply potential supply line 61 made of aluminum or the like for forming a second power supply potential V _SS on the P well 11 with an insulating film interposed therebetween, and two input lines 151 and 152;
And two output lines 153 and 154.

The common source of the transistors QP5 and QP6 is connected to the power supply line 51 by a contact. The drain of the transistor QP5 is connected to the output line 153 by a contact. Also,
The drain of the transistor QP6 is connected to the output line 154 by a contact.

The common source of the transistors QN5 and QN6 is connected to the power supply potential supply line 61 by a contact. The drain of the transistor QN5 is connected to the output line 153 by a contact. The drain of the transistor QN6 is
It is connected to the output line 154.

The gate electrode of transistor QP5 and the gate electrode of transistor QN5 are connected to each other to form input line 151 of the first inverter circuit. Also,
The gate electrode of the transistor QP6 and the transistor QN6
Are connected to each other to form an input line 152 of the second inverter circuit. An output signal of the first inverter circuit is supplied to an output line 153. The output signal of the second inverter circuit is supplied to an output line 154.

Here, the input line 152 is connected to the wiring 156 in the first wiring layer.
The wiring 157 in the second wiring layer is connected to 56. By forming these wirings on the P well 12, an extra space is created in the N well 11, and a tap 158 can be formed there. A tap 158 formed in the N well 11 so as to be adjacent to the transistor QP6 is connected to the power supply potential supply line 51. The first power supply potential V _DD is supplied to the N-well 11 from the power supply potential supply wiring 51 via the tap 158.

[0060]

As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit having a smaller cell size than the conventional one by eliminating useless regions in the standard cell. Since the number of standard cells used in a semiconductor integrated circuit is very large, it is possible to reduce the chip size of a semiconductor integrated circuit by reducing the cell size per standard cell.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a NAND cell included in a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a layout diagram of a NOR cell included in the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating two inverter circuits included in a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a layout diagram of a standard cell included in a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a layout diagram of a standard cell included in a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a general two-input NAND circuit.

FIG. 7 is a layout diagram of a NAND cell in a conventional semiconductor integrated circuit.

FIG. 8 is a circuit diagram of a general two-input NOR circuit.

FIG. 9 is a layout diagram of a NOR cell in a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1, 11 N well 2, 12 P well 10 NAND cell 20 NOR cell 30, 40 cell 50, 51, 60, 61 Power supply potential supply wiring 101, ..., 201, ... Contact 104, 203 Wiring 107, 108 , 207, 208 Input lines 109, 209 Taps 151, 152 Input lines 153, 154 Output lines 155, 158 Taps 156, 157 Wiring QP1-QP6 P-channel transistors QN1-QN6 N-channel transistors

Claims (8)

[Claims] A semiconductor substrate; an N-well formed in the semiconductor substrate; a first power supply potential supply line formed on the N-well via an insulating film in a longitudinal direction of the N-well; A second power supply potential line formed in parallel with the first power supply potential line via an insulating film on the semiconductor substrate or a P well formed in the semiconductor substrate; and formed in the N well. A first group of cells including a P-channel transistor and an N-channel transistor formed in the semiconductor substrate or the P-well, the first group connecting the N-well to the first power supply potential supply line.
The first group of cells without the second tap for connecting the semiconductor substrate or the P well to the second power supply potential supply line, and the P formed in the N well. A second group of cells including a channel transistor and an N-channel transistor formed in the semiconductor substrate or the P-well, wherein the second group of cells includes the second tap and does not include the first tap. A semiconductor integrated circuit comprising: two groups of cells. 2. A third group of cells including a P-channel transistor formed in the N-well and the N-channel transistor formed in the semiconductor substrate or the P-well, wherein the first tap is also provided. 2. The semiconductor integrated circuit according to claim 1, further comprising the third group of cells that does not have the second tap. 3. One of the cells of the first group is formed in the N-well in parallel with the first power supply potential supply line, and one source and the other drain are common. And a plurality of P-channel transistors connected in series so as to be formed in the semiconductor substrate or the P-well in parallel with the second power supply potential supply line, and connected in parallel so that the drain is common. A plurality of N-channel transistors, and a tap formed in the N-well adjacent to one of the plurality of P-channel transistors and connected to the first power supply line. 3. The semiconductor integrated circuit according to 1 or 2. 4. One of the cells of the first group includes K N-channel transistors whose drains are connected to each other and whose sources are connected to the second power supply potential supply line (where K is 2 K number of P-channel transistors connected in series between the first power supply potential supply line and the drains of the K number of N-channel transistors, each having a gate electrode of one N-channel transistor And 1
And a K input connected to the gate electrodes of the two P-channel transistors.
4. The semiconductor integrated circuit according to claim 3. 5. One of the cells of the second group is formed in the N-well in parallel with the first power supply line, and connected in parallel so that the drain is common. And a plurality of P-channel transistors formed in the semiconductor substrate or the P-well in parallel with the second power supply potential supply line, and one source and the other drain are connected in series so as to be common. A plurality of N-channel transistors, and a tap formed in the semiconductor substrate or the P-well adjacent to one of the plurality of N-channel transistors and connected to the second power supply potential wiring. The semiconductor integrated circuit according to claim 1, further comprising: 6. One of the cells in the second group includes L P-channel transistors whose sources are connected to the first power supply potential supply line and whose drains are connected to each other (L is 2 L number of N-channel transistors connected in series between the drains of the L number of P-channel transistors and the second power supply potential supply line, and the gate electrodes of one P-channel transistor each And 1
2. A NAND cell comprising: L inputs connected to the gate electrodes of two N-channel transistors.
6. The semiconductor integrated circuit according to any one of claims 1 to 5. 7. One of the cells of the second group includes at least one P-channel transistor having an impurity diffusion region formed in the N-well, and formed in the semiconductor substrate or the P-well. At least one N-channel transistor having a doped impurity diffusion region, wherein the impurity diffusion region of the at least one P-channel transistor has the at least one N-channel transistor.
3. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is larger than an impurity diffusion region of the channel transistor. 8. One of the cells of the first group includes at least one P-channel transistor having an impurity diffusion region formed in the N well, and formed in the semiconductor substrate or the P well. And at least one N-channel transistor having a doped impurity diffusion region, wherein a region of a wiring connected to the at least one N-channel transistor has the at least one N-channel transistor.
8. The semiconductor integrated circuit according to claim 1, wherein the size of the semiconductor integrated circuit is larger than a region of a wiring connected to one P-channel transistor.