JP2002157896A - Semiconductor memory integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory integrated circuit in which layout of a defective address storing circuit is improved and increment of access time due to wiring delay is suppressed. SOLUTION: A memory cell array 10 is divided into an upper part cell array 10a and a lower part cell array 10b consisting of plural banks respectively. A column of row decoders 20 is arranged at a word line end part of the memory cell array 10 and a column decoder 30 is arranged at a bit line end part. The memory cell array 10 comprises a redundant cell array for replacing a defective cell by a normal cell array. A fuse circuit 40 which stores a defective address and controls replacement of a defective cell by coincidence detection with an address externally supplied is divided into two columns of fuse circuits 40a, 40b, fuse sets of each fuse circuit 40a, 40b are arranged in the direction of word line of the memory cell array 10, and the columns of fuse circuits 40a, 40b are arranged in the direction of bit line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory integrated circuit employing a redundant circuit system for repairing a defective cell.

[0002]

2. Description of the Related Art Generally, in a semiconductor memory such as a DRAM,
A redundant circuit system is employed to remedy a defective cell.
In the redundant circuit method, a redundant cell array is prepared for the normal cell array, and if a defect is found in the normal cell array as a result of the test, this is replaced with the redundant cell array.
For replacement control of a defective cell, a defective address storage circuit is provided which stores a defective address, detects coincidence between an externally supplied address and the defective address, and outputs a replacement control signal. Usually, a fuse circuit is used for the defective address storage circuit, and programming of the fuse circuit is performed based on a result of the test.

FIG. 13 shows such a redundant circuit type DRA.
3 shows a basic configuration of M. The core of the DRAM includes a memory cell array 1, a row decoder 2 for selecting a word line WL, and a column decoder 3 for selecting a bit line BL. The memory cell array 1 is divided into a number of banks (or sub-cell arrays), although not shown in the figure, in the case of a large capacity, and a redundant cell array for replacing defective cells is provided for each bank.

Fuse circuit 4 for storing a defective address
Is composed of an array of a plurality of fuse sets FS. The figure shows the case of row redundancy in which replacement control of a defective word line is performed. However, each fuse set FS of the fuse circuit 4 includes a defective row address in each bank and a redundant cell array in which the defective row is replaced. A fuse is provided for programming information to determine whether to do so. The fuse set FS outputs a signal SWLON for controlling activation and deactivation of the normal cell array and a signal SRDact for controlling activation and deactivation of the redundant row decoder. These signals are transferred to row decoders (including redundant row decoders) 2 via drivers 5 and 6, respectively.

[0005]

When the capacity of the memory cell array 1 is large in such a redundant circuit type DRAM, the fuse circuit 4 occupies a large area accordingly. More specifically, assuming that the memory cell array 1 has a capacity of 1024 word lines and 16 spare word lines per bank, and 2048 pairs of bit lines, 16 banks are prepared. Fuse sets FS <0> to FS <53> are arranged.

When such a large number of fuse sets FS are arranged in a line in the word line direction of the memory cell array 1,
Signals SWLON, SRDa from each fuse set FS
The ct will be transferred a significantly different distance depending on the position. Since each fuse set also receives an address signal for detecting address coincidence, the address line also runs a long distance. As a result, the influence of the wiring delay increases, specifically, it directly affects the rise of the selected word line, and the access time increases.

The present invention has been made in consideration of the above circumstances, and has as its object to provide a semiconductor memory integrated circuit in which the layout of a defective address storage circuit is improved to suppress an increase in access time due to a wiring delay.

[0008]

A semiconductor memory integrated circuit according to the present invention stores a normal cell array, a memory cell array having a redundant cell array for replacing a defective cell of the normal cell array, and a defective address of the normal cell array. A defective address storage circuit comprising a plurality of storage circuit sets for detecting coincidence between an externally supplied address and a defective address and replacing a defective cell in the normal cell array with the redundant cell array; The plurality of storage circuit sets forming the storage circuit are divided into a plurality of storage circuit rows, and the storage circuit sets in each storage circuit row are arranged in the first direction.
The plurality of memory circuit rows are arranged in a second direction orthogonal to the first direction.

According to the present invention, a defective address storage circuit comprising a plurality of storage circuit sets is divided into a plurality of storage circuit rows, and these storage circuit rows are arranged in a direction orthogonal to the arrangement direction of the storage circuit sets. As a result, compared to the conventional case where a plurality of storage circuit sets are arranged in a line,
The wiring delay of the control signal line provided from each storage circuit set to the memory cell array region can be reduced. As a result, it is possible to suppress an increase in access time of the semiconductor memory employing the redundant circuit method.

The memory cell array is, for example, divided into at least two cell array regions, and each cell array region has a normal cell array and a redundant cell array for replacing a defective cell in the normal cell array. At this time, a plurality of stages of storage circuit rows constituting the defective address storage circuit are arranged so as to perform defective cell replacement in each cell array region, for example, corresponding to each cell array region. Further, in this case, a part of the storage circuit sets of the storage circuit rows in a plurality of stages can be adapted to replacement of a defective cell in a plurality of cell array regions.

Each storage circuit set includes a first fuse circuit for storing a defective address, a second fuse circuit for designating whether or not the storage circuit set can be used, and a redundant cell array. A third fuse circuit for selecting one, a comparator for detecting coincidence between an output of the first fuse circuit and an externally supplied address, and an output of the comparator and a second fuse circuit. A logic gate for outputting a replacement control signal by multiplying the output; and a decoder activated by the output of the logic gate for decoding data of the third fuse circuit and outputting a spare selection signal. It is configured with.

Further, a part of the storage circuit set which can be set to correspond to a plurality of cell array areas includes, for example, a first fuse circuit for storing a defective address and a second fuse circuit for specifying a plurality of cell array areas. , A third fuse circuit for selecting one of the redundant cell arrays, a comparator for detecting a match between an output of the first fuse circuit and an address supplied from the outside, A plurality of logic gates for outputting a replacement control signal for a plurality of cell array regions by multiplying the output by the output of each of the second fuse circuits, and being activated by the outputs of these logic gates And a plurality of decoders for decoding the data of the third fuse circuit and outputting each spare selection signal for the corresponding cell array region. .

Alternatively, some of the storage circuit sets set to be able to correspond to a plurality of cell array regions include a first fuse circuit for storing a defective address and a storage circuit set for designating availability of the storage circuit set. A second fuse circuit;
A third fuse circuit for selecting one of the redundant cell arrays, a comparator for detecting a match between an output of the first fuse circuit and an address supplied from the outside, and an output of the comparator and a second A logic gate for outputting a replacement control signal by multiplying the output of the fuse circuit; and a logic gate activated by the output of the logic gate for decoding data of the third fuse circuit and outputting a spare selection signal. A decoder, and the logic gate and the output signal wiring of the decoder may be arranged as a replacement control signal line and a spare selection signal line for any of the plurality of cell array regions by a mask option. it can.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows a main configuration of an embodiment in which the present invention is applied to a semiconductor integrated circuit including a DRAM. In this embodiment, the memory cell array 10 is divided into an upper cell array 10a and a lower cell array 10b, each of which has eight banks BANK <0> to <7.
>. Banks assigned the same number in the upper cell array 10a and the lower cell array 10b are simultaneously activated and precharged. When a set of banks is activated and then precharged,
Another set of banks may be activated before the precharge begins.

FIG. 2 shows a specific configuration focusing on one bank BANK <i> of the upper cell array 10a of FIG. The bank BANK <i> has a normal cell array 11 in a range constituted by a normal word line WL.
And spare word line SW for replacing a defective word line
And a redundant cell array 12 composed of L. Specifically, as shown in FIG. 3, one bank BANK <i> includes 1024 word lines WL and 16 spare word lines SWL, and has 2048 pairs of bits intersecting these. Lines BL and bBL are included. The bit line sense amplifiers are alternately arranged on both sides of the bit lines BL and bBL to form the sense amplifier rows 13 and 14.

A row decoder row 20 for selecting a word line is arranged along one side of the memory cell array 10, and a column decoder 30 for selecting a bit line is arranged along another side. As shown in FIG. 2, the row decoder row 20 includes, for one bank BANK <i>, 256 row decoders RD <0> to <255> and four spare row decoders SRD <0> to <3 >. Each row decoder RD is responsible for four word lines WL, and each spare row decoder SRD is also responsible for four spare word lines SWL.

As shown in FIG. 1, a fuse circuit 40, which is a defective address storage circuit for performing a replacement control of a defective row address, includes two stages of fuse circuit rows 40a and 40b. The upper fuse circuit row 40a stores a defective row address of the upper cell array 10a, and externally supplied row address RA and bank address BA.
, And 27 fuse sets FS <0> T to FS <26> T for detecting coincidence between the set and the defective address. The lower fuse circuit row 40b stores the defective row address of the lower cell array 10b, and detects the coincidence between the externally supplied address and the defective address in the 27 fuse sets FS <0> B to FS <26.
> B.

That is, in this embodiment, a fuse set normally arranged in one row is divided into two and a fuse circuit row including 27 fuse sets FS arranged in the word line direction of the memory cell array 10. 40a, 4
0b are laid out in a state of being overlapped in two stages in the bit line direction.

The fuse sets of the fuse circuit rows 40a and 40b are provided with replacement control signals bSWLONT and bSWLONB based on the address coincidence detection described above, and spare selection signals SRDact <0: 3> T and SRDact <0: 3>.
B is output. Replacement control signals bSWLONT, bSWL
ONB is a signal that deactivates the row decoder RD at the defective address and activates the spare row decoder SRD instead. Therefore, these replacement control signals bSWLON
T and bSWLONB are supplied to complementary signals (NWLONT and SWLONB) by the relay drivers 60a and 60b, respectively.
T), (NWLONB, SWLONB)
It is supplied as an activation signal to the row decoder RD and the spare row decoder SRD of the upper cell array 10a and the lower cell array 10b.

Specifically, the upper cell array 10a will be described. When there is no address match, the replacement control signal bSWLONT is "H". When an address match is detected, the replacement control signal bSWLONT becomes "L", and the relay driver 60a causes the normal cell array 1
Thus, a signal NWLONT = "L" for deactivating 1 and a signal SWLONT = "H" for activating the redundant cell array 12 are obtained. The same applies to the lower cell array 10b.

Spare selection signal SRDact <0: 3>
T, SRDact <0: 3> B corresponds to the upper cell array 10
As specifically shown in FIG. 2 for a, corresponding to the four spare row decoders SRD <0: 3>, they are output as signals for selecting one spare row decoder when an address match is detected. You. This spare selection signal SRD
act <0: 3> T and SRDact <0: 3> B are respectively connected to four spare row decoders SRD in each bank of the upper cell array 10a and the lower cell array 10b via the relay drivers 50a and 50b which perform in-phase re-driving. <0: 3
> Is activated.

Each fuse set of the fuse circuit 40 has the same configuration. Typically, the fuse circuit row 40a
FIG. 4 shows the configuration of the fuse set FS <j> T. Fuse is 1 of f0-f13
There are four. The fuses f0 to f10 form a fuse circuit for storing a defective address of the upper cell array 10a. The fuse f11 is a fuse circuit for designating whether to use this fuse set. The remaining fuses f12 and f13 are
A fuse circuit for determining which of the four spare row decoders SRD in the bank is to be replaced is formed.

Fuse f0-f1 for specifying defective address
0, f0-f7 specify which of the 256 row decoders in the bank is to be deactivated,
The remaining three store address information for selecting one of the eight banks BANK <0>-<7>.

Each fuse is a PM for precharging.
OS transistor QP and NMOS transistor Q for selection
N is connected in series between the power supply VCC and the ground VSS. The fuse data is obtained by precharging by turning on the PMOS transistor QP and turning off the NMOS transistor QN, turning off the PMOS transistor QP, and NM
Reading is performed by turning on the OS transistor QN. If the fuse is blown, “H” is output,
If not disconnected, "L" is output.

Fuse f0-f1 for defective address designation
0 is output by the comparator 401 to the row address RA <
0> -RA <7> and bank address BA <0> -BA
A match with <2> is detected. When a match is detected, the output of the comparator 401 becomes “H”. However, the AND gate 402 sets a control pulse period in which the product of the outputs of all 11 comparators 401 and the output of the enable fuse f11 is present. . Accordingly, only when a match between the input address and the fuse data is detected and the fuse set is enabled, an "H" output is obtained from the AND gate 402.

Similar outputs are output from the other 26 fuse sets, and a total of 27 output signals (all "L" or only one "H") enter the NOR gate 404 and replace it. At the defective address to be replaced, the replacement control signal b
SWONT is obtained. That is, when the upper cell array 10a is accessed, when replacement is necessary, the replacement control signal bSWLONT = "L" is output.

The output of the AND gate 402 is
03 is input as an activation signal. The decoder 403 decodes the data of the fuses f12 and f13 and sets one of the four outputs to "H". This is a signal for selecting one of the four spare decoders SRD. This decoder 4
The four outputs 03 are also in the other 26 fuse sets, and their OR is taken by the OR gate 405 to generate the spare selection signal SRDact <0: 3> T.

Therefore, it is necessary to replace a defective row, and when the replacement control signal bSWLONT becomes "L", one of the spare selection signals SRDact <0: 3> T becomes "1".
H ”to select the spare row decoder SRD.

In this embodiment, as shown in FIG. 1, the fuse circuits 40 are not arranged in a line in the word line direction as in the prior art, but are overlapped in a direction orthogonal to the word lines WL.
The fuse circuits are arranged as stages of fuse circuits 40a and 40b, each of which is responsible for an upper cell array 10a and a lower cell array 10b. By employing such an arrangement, the difference in wiring length between the address line, the replacement control signal line, and the spare selection signal line provided from the fuse circuit 40 to the row decoder row 20 is reduced, and the access time due to the wiring delay is reduced. Can be suppressed from increasing.

[Second Embodiment] FIG. 5 shows a configuration of a DRAM unit according to another embodiment, corresponding to FIG. In the development of semiconductor memories in recent years, derivative products using the same generation of technology are frequently developed. At the same time as developing a DRAM of a certain capacity, DRA of half the capacity
Developing M is also done. The example of FIG.
Upper cell array 10a and lower cell array 1
0b, that is, eight banks BANK <0> to <8
7> is an example in which the memory cell array 10 is configured.

In this case, the fuse circuit 40 should originally have a half capacity, but here, the fuse circuit 40 has the same configuration as that of FIG. This is based on the consideration of minimizing rework as much as possible in order to improve design efficiency when developing derivative products. As in FIG. 1, the fuse circuit 40 includes upper and lower fuse circuit rows 40.
The influence of the wiring delay is reduced as a two-stage configuration of a and b. Both the upper and lower fuse circuit rows 40a and 40b can take charge of defective replacement of the memory cell array 10.

From the fuse sets FS <0> to FS <26> of the upper fuse circuit row 40a, the replacement control signal b
SWLONT and spare selection signal SRDact <0: 3>
T is output, and from the fuse sets FS <27> to FS <53> of the lower fuse circuit row 40b, the replacement control signal bSWLONB and the spare selection signal SRDact <0:
3> B is output. Fig. 4 shows the configuration of each fuse set.
Is the same as that shown in FIG.

Replacement control signals bSWLONT, bSWLO
The NB enters the AND gate 80, is multiplied, and enters the relay driver 60. By the relay driver 60, the normal replacement control signal NWLON and the spare replacement control signal S
WLON is generated. Also, the spare selection signal SRDa
ct <0: 3> T and SRDact <0: 3> B are connected to the four spare row decoders S of each bank of the memory cell array 10 via the OR gate 70 and the relay driver 50.
Enter RD <0: 3>.

As in the previous embodiment, the fuse circuit 4
0 stores a defective address and detects coincidence between an externally supplied address and the defective address. When a match is detected in any of the 54 fuse sets, the replacement control signal bSWLONT or bSWLONB becomes “L”,
Further, spare selection signals SRDact <0: 3> T, SR
Any one of Dact <0: 3> B becomes “H”.
Therefore, when a defective address is accessed, the normal replacement control signal NWLON becomes “L” and the spare replacement control signal SWLON becomes “H”, the row decoder becomes inactive, and the spare selection signals SRDact <0: 3> T , SRD
act <0: 3> B activates one spare row decoder.

Except when a defective address is accessed, the replacement control signals bSWLONT and bSWLONB are set to "
H ”and the normal replacement control signal NWLON is“
H ", the spare replacement control signal SWLON is" L ", and the row decoder of the selected address is activated as it is.

According to this embodiment, similarly to the above-described embodiment, not only the effect of reducing the influence of the wiring delay can be obtained, but also, as a derivative of the above-described embodiment, the capacitance can be reduced by a simple design. A small DRAM can be obtained. Although the capacity of the memory cell array is half that of the previous embodiment, the capacity of the fuse circuit does not change.
Higher relief efficiency can be obtained compared to the previous embodiment.

[Third Embodiment] FIG. 6 shows a configuration of a DRAM according to another embodiment, corresponding to FIG. The basic configuration is the same as that of FIG. 1, and the fuse circuit 40 is also composed of two stages of fuse circuit rows 40a and 40b each having 27 fuse sets. However, a total of four fuse sets FS <0> TB to FS in the fuse circuit rows 40a and 40b, two each.
<3> Unlike other fuse sets, TB can correspond to both the upper cell array 10a and the lower cell array 10b.

That is, the fuse sets FS <0> TB to F
The difference between S <3> TB and other fuse sets is that
And two fuse sets FS of the fuse circuit row 40a.
<0> TB, FS <1> TB are replacement control signals bSW for the upper cell array 10a entering the relay driver 60a.
A replacement control signal bSWL for the lower cell array 10b entering the relay driver 60b, in addition to the terminal for outputting LONT
It has a terminal for outputting ONB. Similarly, the two fuse sets FS <2> TB, FS of the fuse circuit row 40b
<3> TB has a terminal for outputting a replacement control signal bSWLONT for the lower cell array 10b entering the relay driver 60b and a terminal for outputting a replacement control signal bSWLONT for the upper cell array 10a entering the relay driver 60a.

Second, the two fuse sets FS <0> TB and FS <1> TB of the fuse circuit array 40a are provided with spare selection signals SRDact <0: 3> T for the upper cell array 10a entering the relay driver 50a. , A lower cell array 10b that enters the relay driver 50b
For outputting a spare selection signal SRDact <0: 3> T for Similarly, the two fuse sets FS <2> TB and FS <3> TB of the fuse circuit row 40b
Are terminals for outputting a spare selection signal SRDact <0: 3> B for the lower cell array 10b entering the relay driver 50b, and a spare selection signal SRDact <0: 3 for the upper cell array 10a entering the relay driver 50a.
> T. The remaining 25 fuse sets are the same as in FIG.

In recent years, due to difficulties in processing due to miniaturization, there are cases where the uneven distribution of defects is more than expected due to the fact that there are many defects at the upper end of the memory cell array or a mask cannot be created perfectly. In this case, even if the fuse sets corresponding to the upper half and the lower half of the memory cell array are sufficiently provided based on the average defect occurrence probability, a shortage of the fuse sets may occur. This embodiment can cope with such a situation by mixing fuse sets that can cope with any relief area.

When the row address RA and the bank address BA are common to the upper cell array 10a and the lower cell array 10b of the memory cell array 10, the upper cell array 10a and the lower cell array 10b cannot be distinguished from each other. Therefore, the fuse sets FS <0> TB to FS <3> TB
, The upper cell array 10a and the lower cell array 1
Information for identifying 0b is stored as fuse data.

When set for the upper cell array 10a, the replacement control signal bSWLONT is set to "L" and b when the input address matches the defective address.
SWLONB is kept at “H”, and one of the upper spare selection signals SRDact <0: 3> T is set at “H”.
At this time, the lower spare selection signal SRDact <0:
3> B remains "L". Also, the lower cell array 10
b, the replacement control signal bSWLONB is set when the input address matches the defective address.
At "L" and bSWLONT at "H", and set one of the lower spare selection signals SRDact <0: 3> B to "L".
H ”. At this time, the upper spare selection signal SRD
act <0: 3> T remains “L”.

FIG. 7 specifically shows one configuration of the fuse sets FS <0> TB to FS <3> TB in FIG.
This is shown corresponding to FIG. 4 of the previous embodiment. The fuses f0 to f14 are one more than those in FIG. Of these, the fuses f0 to f10 are for defective address designation as in the case of FIG. The fuse f11 is for designating the fuse set for the upper cell array 10a, and the fuse f12 is for designating the fuse set for the lower cell array 10b. Fuse f13, f1
Reference numeral 4 stores information for selecting one of the four spare row decoders.

As an AND gate for outputting a replacement control signal upon detection of a defective address match, A which takes the product of the output of the comparator 401 and data of the fuse f11 is used.
An ND gate 402-1 and an AND gate 402-2 for calculating the product of the output of the comparator 401 and the data of the fuse f12 are provided. These AND gates 402-1,
The outputs of 402-2, along with the corresponding outputs of the other fuse sets, respectively, are NOR gates 404-1 and 404-.
2, the upper cell array 10a and the lower cell array 10
The replacement control signals bSWLONT and bSWLONB for b are output.

The decoder 403-1 activated by the output of the AND gate 402-1 to decode the data of the fuses f13 and f14, and the AND gate 40
Activated by the output of 2-2, fuses f13, f
And a decoder 403-2 for decoding 14 data. These decoders 403-1 and 403-
2 together with the corresponding decoder outputs of the other fuse sets, respectively, are OR gates 405-1 and 405-2.
And a spare selection signal SR for the upper cell array 10a.
Dact <0: 3> T, and a spare selection signal SRDact <0: 3> B for the lower cell array 10b is output.

Therefore, when the fuse f11 is cut and this fuse set is set for the upper cell array 10a, when a defective address is accessed, the replacement control signal bSWLONT is set to "L" and the upper spare is selected. One of the signals SRDact <0: 3> T becomes “H”. As a result, replacement control of the defective row is performed. When the fuse f12 is cut and set for the lower cell array 10b, when a defective address is accessed, the replacement control signal bSWLONB becomes "L" and the lower spare selection signal SRDact <0: 3> B One becomes "H" and the replacement control of the defective row is performed.

According to this embodiment, the same effects as those of the first embodiment can be obtained, and as a result, the defect repair range of the fuse circuit is widened, so that even if the memory cell array has a large uneven distribution of defects, it is possible to perform the relief. Thus, the relief efficiency is improved.

[Embodiment 4] FIG. 8 shows an embodiment in which the same function as the fuse set of FIG. 7 is realized by reducing one fuse. That is, in FIG.
11 and f12 correspond to the upper cell array 10a and the lower cell array 10b, respectively. On the other hand, in the configuration of FIG. 8, one fuse f11 can correspond to the upper cell array 10a and the lower cell array 10b.

For this purpose, the connection wiring of one AND gate 402 to the NOR gates 404-1 and 404-2 is
Switching between the wiring shown by the solid line and the wiring shown by the broken line can be switched by a mask option. Similarly, one decoder 403 activated by the output of the AND gate 402
Is connected to the OR gates 405-1 and 405-2 by a mask option between a wiring shown by a solid line and a wiring shown by a broken line. Fuse f12
And f13 store information for selecting one of the four spare row decoders.
to go into.

As described above, the assignment of one fuse set to different relief areas can be changed by changing a part of the wiring connection by a mask option without using the fuse. That is, the same function as the fuse set of FIG. 7 can be realized by reducing the number of fuses, AND gates, and decoders one by one.

[Fifth Embodiment] FIG. 9 shows a structure according to another embodiment corresponding to FIG. In the embodiment of FIG. 1, the fuse circuit 40 has two stages of fuse circuit rows 40a and 40b stacked in the bit line direction of the memory cell array 10, and the fuse sets in each stage are arranged in the word line direction. On the other hand, in FIG. 9, the arrangement of the fuse circuit 40 is rotated by 90 degrees with respect to the case of FIG. That is, the two-stage fuse circuit rows 40a and 40b of the fuse circuit 40 are connected to the memory cell array 1
The fuse sets of the respective stages are arranged in the bit line direction. Other configurations are shown in FIG.
Is the same as

The layout of the actual fuse circuit is optimally determined on the integrated circuit chip as a peripheral circuit for the core circuit including the memory cell array 10 and its decode circuit section. Therefore, the layout of FIG. 9 in which the direction of the fuse circuit row is orthogonal to that of FIG. 1 is also possible. Also in this case, the delay of the wiring from the fuse circuit 40 to the row decoder RD can be reduced by forming the fuse circuit row not in one row but in a two-stage configuration, and the same effect as in the previous embodiment can be obtained. Can be The layout of the fuse circuit 40 shown in FIG. 9 is similarly applicable to the fuse circuit 40 having the configuration described in the embodiment of FIG.

[Embodiment 6] FIG. 10 shows a configuration according to still another embodiment corresponding to FIG. 1 and FIG. In the case of this embodiment, a fuse circuit 40 is arranged on the memory cell array 10 on the side opposite to the row decoder row 20. The configuration of the fuse circuit 40 and the arrangement direction in relation to the memory cell array 10 are the same as those in FIG. A signal line from the fuse circuit 40 passes between the upper cell array 10a and the lower cell array 10b and is led to the row decoder column 20. Also in this case, the delay of the wiring from the fuse circuit 40 to the row decoder RD can be reduced by forming the fuse circuit row not in one row but in a two-stage configuration, and the same effect as in the previous embodiment can be obtained. Can be The layout of the fuse circuit 40 shown in FIG. 10 corresponds to the fuse circuit 4 having the configuration described in the embodiment of FIG.
The same applies to the case where 0 is used.

[Embodiment 7] FIG. 11 shows a structure of still another embodiment corresponding to FIG. In the case of this embodiment, the memory cell array 10 is composed of, for example, an upper cell array 1 composed of eight banks.
0a, intermediate cell array 10b and lower cell array 10c
In a three-stage configuration. Correspondingly, the fuse circuit 40 has a three-stage configuration including an upper fuse circuit array 40a, an intermediate fuse circuit array 40b, and a lower fuse circuit array 40c.

Each of the fuse circuit rows 40a, 40b, 40c
Is a set of 27 fuse sets FS <0> T
ＦFS <26> T, FS <0> M to FS <26> M, F
S <0> B to FS <26> B. Then, replacement control signals bSWLONT, bSWLONM, and bSWLONT obtained from the respective fuse circuit rows 40a, 40b, and 40c
bSWLONB is the relay driver 60a, 60
b and 60c, the signals are converted into complementary signals, and the upper cell array 10a, the intermediate cell array 10b, and the lower cell array 1
0c is sent to the row decoder section.

Similarly, each fuse circuit row 40a, 40a
b, 40c, the spare selection signal SRDact <
0: 3> T, SRDact <0: 3> M, SRDact
<0: 3> B represents the relay drivers 50a and 50, respectively.
The data are sent to the row decoder sections of the upper cell array 10a, the intermediate cell array 10b, and the lower cell array 10c via the lines b and 50c.

As described above, when the capacity of the memory cell array 10 is increased and the number of fuse sets is accordingly increased, the fuse circuit 40 is not limited to the two-stage configuration, but can be configured to have the three-stage configuration. Can be more effectively reduced. Further, it is also possible to configure a fuse circuit row of four or more stages.

[Eighth Embodiment] FIG. 12 shows a configuration of still another embodiment corresponding to FIG. In the case of this embodiment, the memory cell array 10 is composed of an upper cell array 10a and a lower cell array 10b as in FIG. 1, but the fuse circuit 40 is composed of three stages of fuse circuit rows 40a, 40b and 40c. I have.

The three stages of fuse circuit rows 40a, 40b, 4
0c is, for example, constituted by 24 fuse sets. 2 of the upper fuse circuit row 40a
Four fuse sets FS <0> T to FS <23> T
And the middle half fuse set FS <24> T to FS
<35> T is for repairing a defect in the upper cell array 10a. The other half fuse set FS <0> B in the middle stage
The FS <11> B and the 24 fuse sets FS <12> T to FS <35> T of the lower fuse circuit row 40c are for relieving a defect of the lower cell array 10b.

That is, in the above-described embodiments, when the fuse circuit 40 is constituted by a plurality of fuse circuit rows, one fuse circuit row corresponds to the same relief area of the memory cell array. In this embodiment,
One row of fuse circuit rows is made to correspond to different relief areas of the memory cell array. Otherwise, it is the same as the embodiment of FIG. According to this embodiment,
An effect similar to that of the above embodiment can be obtained.

In the above, the DRAM has been exclusively described. However, the present invention is not limited to this.
The present invention can be similarly applied to an integrated circuit including various other semiconductor memories such as M and EEPROM.

[0062]

As described above, according to the present invention, a defective address storage circuit composed of a plurality of storage circuit sets is divided into a plurality of storage circuit columns and overlapped with each other, so that a plurality of storage circuits as in the prior art are provided. Compared with the case where the sets are arranged in a line, the wiring delay of the control signal line connected from each storage circuit set to the decode circuit can be reduced.
As a result, it is possible to suppress an increase in access time of the semiconductor memory employing the redundant circuit method.

[Brief description of the drawings]

FIG. 1 is a diagram showing a main configuration of a DRAM according to an embodiment of the present invention;

FIG. 2 is a diagram showing a specific configuration focusing on one bank and one fuse circuit row of the embodiment.

FIG. 3 is a diagram showing an internal configuration of one bank of the embodiment.

FIG. 4 is a diagram showing a configuration of one fuse set of the embodiment.

FIG. 5 is a diagram showing a main configuration of a DRAM according to another embodiment.

FIG. 6 is a diagram showing a main configuration of a DRAM according to another embodiment.

FIG. 7 is a diagram showing a configuration of a fuse circuit corresponding to a plurality of relief areas in the embodiment of FIG. 6;

8 is a diagram showing an embodiment in which the configuration of FIG. 7 is modified.

FIG. 9 is a diagram showing a main configuration of a DRAM according to another embodiment.

FIG. 10 is a diagram showing a main configuration of a DRAM according to another embodiment.

FIG. 11 is a diagram showing a main configuration of a DRAM according to another embodiment.

FIG. 12 is a diagram showing a main configuration of a DRAM according to another embodiment.

FIG. 13 shows a relationship between a memory cell array of a conventional DRAM and a fuse circuit.

[Explanation of symbols]

10: memory cell array, 20: row decoder row, 30
... column decoder, 40 ... fuse circuit, 40a, 40
b: fuse circuit row, FS <0> T to FS <26> T,
FS <0> B to FS <26> B: fuse set, 50
a, 50b, 60a, 60b ... relay driver, 401 ...
Comparator, 402: AND gate, 403: decoder, 4
04: NOR gate, 405: OR gate.

Claims (8)

[Claims] 1. A memory cell array having a normal cell array and a redundant cell array for replacing a defective cell of the normal cell array, and detecting coincidence between a defective address stored in the normal cell array and an externally supplied address. A defective address storage circuit configured by a plurality of storage circuit sets for replacing defective cells of the normal cell array with the redundant cell array, wherein the plurality of storage circuit sets configuring the defective address storage circuit have a plurality of stages. Storage circuit sets in each storage circuit row are arranged in a first direction, and the storage circuit rows of the plurality of stages are arranged in a second direction orthogonal to the first direction. A semiconductor memory integrated circuit characterized by the above-mentioned. 2. The memory cell array is divided into at least two cell array regions, each cell array region having a normal cell array and a redundant cell array for replacing a defective cell of the normal cell array, and the defective address storage circuit. Is a multi-stage memory circuit sequence,
2. The semiconductor memory integrated circuit according to claim 1, wherein said semiconductor memory integrated circuit is arranged so as to perform defective cell replacement in each of said cell array regions. 3. The semiconductor memory integrated circuit according to claim 2, wherein a part of the storage circuit sets of the plurality of storage circuit rows is capable of coping with defective cell replacement in a plurality of cell array regions. . 4. The semiconductor memory according to claim 1, wherein said first direction is a word line direction of said memory cell array, and said second direction is a bit line direction of said memory cell array. Integrated circuit. 5. The semiconductor memory according to claim 1, wherein said first direction is a bit line direction of said memory cell array, and said second direction is a word line direction of said memory cell array. Integrated circuit. 6. The memory circuit set includes: a first fuse circuit for storing a defective address; a second fuse circuit for designating whether the memory circuit set can be used; and one of the redundant cell arrays. A third fuse circuit for selecting one of the first and second fuse circuits; a comparator for detecting a match between an output of the first fuse circuit and an externally supplied address; and an output of the comparator and the second fuse circuit. And a logic gate for outputting a replacement control signal by taking the product of the outputs of the logic circuits, and a decoder activated by the output of the logic gate to decode data of the third fuse circuit and output a spare selection signal 2. The semiconductor memory integrated circuit according to claim 1, comprising: 7. The partial memory circuit set includes: a first fuse circuit for storing a defective address; a second fuse circuit for designating the plurality of cell array regions; A third fuse circuit for selecting one of the first and second fuse circuits; a comparator for detecting a match between an output of the first fuse circuit and an externally supplied address; and an output of the comparator and the second fuse circuit. A plurality of logic gates for outputting the respective replacement control signals for the plurality of cell array regions by taking the product of each one of the outputs of the respective logic arrays; and the third logic gates being activated by the outputs of these logic gates, respectively. 4. A decoder according to claim 3, further comprising a plurality of decoders for decoding data of the fuse circuit and outputting respective spare selection signals for a corresponding cell array region. Semiconductor memory integrated circuit. 8. The partial memory circuit set includes: a first fuse circuit for storing a defective address; a second fuse circuit for designating whether the memory circuit set can be used; and the redundant cell array. A third fuse circuit for selecting one of the following: a comparator for detecting a match between an output of the first fuse circuit and an externally supplied address; and an output of the comparator and a second fuse. A logic gate for outputting a replacement control signal by taking the product of the outputs of the circuit; and a logic gate activated by the output of the logic gate for decoding data of the third fuse circuit and outputting a spare selection signal. And a logic gate and an output signal line of the decoder, as a replacement control signal line and a spare selection signal line for any of the plurality of cell array regions. The semiconductor memory integrated circuit according to claim 3, characterized in that it is provided by the option.