JP2002150792A - Memory test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory test device which can perform a test by an interleaving system between banks and distinguishing correctly a charge 1 region and a charge 0 region. SOLUTION: This device is provided with a pattern-select section taking out selectively plural pattern signals outputted for each same time slot by a pattern generating section in accordance with an input pin of a memory to be tested, plural cycle delaying sections giving time difference for arranging in the direction of time series to each of pattern signals selected by this plural pattern-select sections, and a multiplxer multiplexing a pattern signal delayed by this plural cycle delaying section.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test apparatus for testing a memory composed of semiconductor integrated circuit elements, and more particularly to a method of inverting the logic of data in accordance with an address condition in a bank-to-bank interleave system. It is an object of the present invention to provide a memory test device capable of performing the above.

[0002]

2. Description of the Related Art Conventionally, in a large-capacity memory such as a DRAM or an SDRAM, a region where a charge is stored by an address and a logic "1" (a charge 1 region) and a logic "1" when a charge is stored. There is a region which is divided into a region of “0” (charge 0 region) and is devised so that the potential of the entire semiconductor chip is averaged to almost zero potential even during practical use. When testing such a memory, an address of one of the areas, for example, the charge 0 area is registered in the test apparatus in advance, so that a test pattern is written to the address of the charge 0 area and the address is tested. In such a case, a data inversion function of performing writing by inverting the logic of the pattern data is added. As a result, the logic value at the time of pattern generation is considered to be charge accumulation, and pattern generation in a test focusing on whether or not charge is accumulated in the address cell can be easily performed.

[0003] Further, as the capacity of the semiconductor memory increases, the number of pins led out tends to increase. For this reason, as a method of reducing the number of pins, for example, a Row address signal and a Column address signal are applied to a common address pin in a time-division manner, and further, as for the Column address, several addresses starting from the applied Column address are stored in the memory. A memory that is internally generated and attempts to reduce the transfer time of an address signal has been put to practical use. Further, some semiconductor devices include a row address signal,
Some types of input data such as a column address signal and write data are input at a certain interval (pattern generation cycle). Typical products include general-purpose DRAM, SDRAM, and Direct Rambus.
DRAM and the like.

FIG. 5 shows an example of write timing specified in such a semiconductor memory. FIG. 5A shows the bank designation signal (the upper few bits of the address signal are assigned). FIG. 5B shows the timing of the address signal applied to the address pin. In the example in the figure, the Row address and C
FIG. 5 shows a situation in which a time difference is given to the same address pin as that of the same address pin. In the example shown in FIG. 5, the column address signal is COL ₀₀ or CO
L ₁₀ only is applied, the internal memory the Y address C
COL ₀₀ , COL ₁₀ , COL ₀₁ , COL ₀₂ , COL
₀₃ and COL ₁₁ , COL ₁₂ , and COL ₁₃ (see FIG. 5D) are shown.

FIG. 5C shows the timing of a control signal applied to a control signal input pin of a semiconductor memory. The illustrated control signal ACT is an active command, and a write command Write or a read command R
This command is used to specify a Row address when performing an ead. Pre indicates a command for extinguishing the charge of the row address line when accessing different row addresses in the same bank. FIG. 5D shows a data string to be written. In FIG. 5, the Row address Row
0, data WD ₀₀ to WD ₀₃ are written to Column addresses COL _{00 to} COL ₀₃ , and at the next write timing, data WD ₁₀ to WD ₁₃ are written to Row address Row 1 and Column addresses COL _{10 to} COL _13. I have.

[0006] Here, Row address Row0, Colu
When mn address COL ₀₃ is assumed to be charged 0 region, it is necessary to write in the memory as data WD ₀₃ is inversion / WD ₀₃ to be written to this address when performing a test as a charge storage to a logical value during pattern generation.
FIG. 6 generates an address signal, a control signal, and pattern data to be written at the write timing shown in FIG.
The configuration of a conventional memory test apparatus for testing a semiconductor memory having the above-described functions is described below.

The pattern generating section 10 includes an address generating section 11
, A data generation unit 12, a control data generation unit 13, a data inversion control unit 14, and a data inversion unit 15. The address generator 11 outputs an X address signal and a Y address signal to be applied to the memory under test 50. The data generator 12 outputs test pattern data TPDAT to be written to the address output by the address generator 11. Further, the control data generator 13 outputs a control signal MUTSiG such as a write command and a read command applied to the memory under test 50 and a pattern select signal patsel for controlling the multiplexing circuit 30.

The data inversion control unit 14 previously stores, for example, an address specified in the charge 0 area. When the X address and the Y address output from the address generation unit 11 correspond to the charge 0 area, the data inversion control unit 14 stores the address. Reference numeral 14 denotes a data inversion control signal to the data inversion unit 15, and test pattern data TPD output from the data generation unit 12.
The logical value of AT is inverted, and the inverted data P
The DAT is sent to the selection unit 20. The selection unit 20 includes two pin data selection units 21A, 21A and 2B.
1B. These pin data selection units 21A and 21B execute an operation of selecting and extracting pattern data to be allocated to each pin of the memory under test 50 for a channel corresponding to each pin.

The pattern signals associated with each channel extracted from both of the pin data selection units 21A and 21B are input to the multiplexing circuit 30 as PAT-A and PAT-B. The multiplexing circuit 30 can be composed of a number of multiplexer groups 31 corresponding to the number of input pins of the memory under test 50, for example. Accordingly, the multiplexing circuit 30 has two input terminal groups A and B, and both of the two input terminal groups A and B have the input terminal group A.
And B are supplied with respective pattern signals (address signals, control signals, pattern data to be written, etc.) from the pin data select units 21A and 21B as PAT-A and PAT-B, and input to both input terminal groups A and B. The respective pattern signals PAT-A and PAT-B are time-division multiplexed and output by the switching operation of the multiplexer group 31.

Each of the pattern signals time-division multiplexed by the multiplexing circuit 30 is output to a channel corresponding to each pin of the memory under test 50, and a cycle delay unit 4 is provided for each channel.
0, the memory under test 5 receives the required cycle delay (delay in units of pattern generation cycle) for each channel.
0 is applied to each input terminal. The expected value data is also input to the logical comparison unit 60 after receiving the necessary cycle delay in the cycle delay unit 40. Here, the cycle delay to be delayed by the cycle delay unit 40 is the cycle delay given to the pattern signal applied to the memory under test 50.
This is a cycle delay for giving a phase difference between the pattern signals so as to match the specifications of each input of 0. The cycle delay given to the expected value data is the read data supplied from the memory under test 50 to the logical comparison unit 60. Corresponds to the delay time until

The read data read from the memory under test 50 and the expected value data output from the cycle delay unit 40 are input to a logical comparison unit 60, and the logical comparison unit 6
At 0, it is compared whether the read data matches the expected value, and the occurrence of mismatch is detected to detect the presence of a defective memory cell. FIG. 7 shows an example of the timing of each pattern signal generated by the pattern generator 10. The pattern signals shown here are a bank designating signal, an X address signal, a Y address signal, test pattern data TPDAT, a control signal M
UTSiG and the pattern select signal patsel. FIG. 7A shows the bank designation signal. This bank designation signal can be constituted by using, for example, the upper two bits of the X address signal. The example shown in FIG. 7 shows a case where the same bank # 0 is designated in any time slot.

FIG. 7B shows the X address signal. This X address signal generates the same X address over the entire area of each time slot in any of the time slots T1, T2,. In the example shown in FIG. 7B, in time slot T1, Row0 is generated as an X address signal,
In the time slot T2, Row1 is used as the X address signal.
Is shown. FIG. 7C shows the Y address signal. This Y address signal is later time-division multiplexed on the same address line together with the X address signal in the multiplexing circuit 30 and applied to the memory under test 50. Therefore, the Y address signals COL ₀₀ , COL ₀₁ ,
COL ₀₂ and COL ₀₃ are generated in each of the time slots T1, T2... With a delay of two cycles of the pattern generation cycle from the initial phase position of each of the time slots T1, T2. An X address signal is output to the address line during two cycles, and Y address is output on the same address line during the next two cycles.
A case where an address signal is output and time division multiplexing is performed will be described.

FIG. 7D shows the timing of the test pattern data TPDAT output from the data generator 12. This test pattern data TPDAT is also generated with a delay of two cycles in phase with the Y address signal in the same manner as the Y address signal, and is applied to the data input pin of the memory under test 50 in synchronization with the Y address signal. FIG. 7E shows pattern data PDA obtained by inverting the logical value of the data to be written in the designated charge 0 area by the data inverting unit 15.
The state of T is shown. That is, in the X address in the example shown in FIG. 7E is Row 0, indicating the case where Y address is set to the data inversion control unit 14 to determine a charge 0 region when the COL _03. Therefore, when the X address signal is Row0
In, a case where Y address signal detects that the COL ₀₃ occurs in the data inversion control unit 14, by inverting the logic of the data WD ₀₃ output by the data generating section 12 by the detection signal. Shows data WD ₀₃ obtained by inverting the logical value / WD ₀₃ in Figure 7E.

FIG. 7F shows a case where the control data generator 13 generates the control data.
4 shows an example of a control signal. The control signals ACT, P shown here
re and Write are commands that operate with the same functions as above.
Is. These control signals ACT, Pre, Writ
e applies the memory under test 50 to the data input terminal.
Data WD₀₀, WD₀₁, WD₀₂, WD₀₃… Is specified
Write to the specified address. In other words, in this example, the time slot
In T1, the X address is Row0 and the Y address is CO
L₀₀, COL₀₁, COL₀₂, COL₀₃A determined by ...
Data WD on dress₀₀, WD₀₁, WD₀₂, WD₀₃…
In the time slot T2, the X address Row1 and the Y address
Dress COL₀₀~ COL₁₃Data WD _Ten~ WD₁₃Write
This shows the case where it is inserted.

FIG. 7G shows a pattern select signal patsel for controlling the switching of the multiplexing circuit 30. The SELA shown in FIG.
A control signal for selecting the output PAT-A of A, SELB is supplied to the multiplexing circuit 30 by the output P of the pin data selection unit 21B.
7 shows a control signal for selecting AT-B. FIG. 8A shows a bank designation signal input to the pin data selection unit 21A and X
3 shows an address signal. FIG. 8B shows a bank designation signal and a Y address signal input to the pin data selection section 21B. That is, in this example, the pin data selection unit 21
A shows a case where an X address signal is allocated to a channel corresponding to an address line on the memory under test 50 side, and a Y address is allocated to a channel corresponding to an address line of the memory under test 50 in the pin data select section 21B.

The data WD _{00 to} WD ₁₃ and the control signal MUTSiG shown in FIG.
1B, and are assigned to the same channel and taken out. Therefore, the multiplexing circuit 30
No matter which of the pin select sections 21A and 21B is selected, the data WD _{00 to} WD ₁₃ and the control signal MUTSiG are set to C in FIG.
And D, the pin data select units 21A and 21B
Are extracted at the same timing as the input-side timing. FIG. 9 shows the timing of signals applied to each input pin of the memory under test 50 after time division multiplexing by the multiplexing circuit 30. FIG. 9A shows a bank designation signal applied to the bank designation signal input pin of the memory under test 50. This bank designation signal is taken out to the same channel (the channel corresponding to the bank designation signal input pin) regardless of whether the multiplexing circuit 30 selects PAT-A or PAT-B.

[0017] In contrast, X address signals Row0 is taken only to the channel corresponding to the address pins of the memory under test 50 from the output PAT-A side of the pin data selector unit 21A, Y address signal COL _00, COL _01, C
OL ₀₂ and COL ₀₃ are taken out to the channel corresponding to the address pin of the memory under test 50 only from the output PAT-B side of the pin data select section 21B. As a result, regarding the address signal, when the multiplexing circuit 30 selects PAT-A, the X address signal Row0 is extracted from the multiplexing circuit 30, and when the multiplexing circuit 30 selects PAT-B, the Y address signal COL is obtained. ₀₀ is extracted and time-division multiplexed in the time slot T1.

Note that the pattern generator 10 outputs a Y address
COL as signal₀₀~ COL₀₃Or COL_Ten~ COL₁₃
All output up to this point, but here, as explained earlier
To the memory under test 50 is given the initial value of the Y address.
As a result, the following three cycles of addresses are
Memory generated inside the test memory 50
Because it has been described, the Y address is
Is COL₀₀, COL _TenSupply only the initial address of
I just need. However, on the memory test device side, for example, logical comparison
The failure analysis memory (not particularly shown) attached to the unit 60
To store bad data in
Generated inside the memory under test 50 in the pattern generator 10
Is also generated.

[0019]

As described above,
Conventionally, the inside of the memory under test 50 is composed of only one bank. For this reason, when successively accessing different X addresses in the same bank, the precharge command Pre shown in FIG. The need for processing to eliminate the charge on the line, for example, limits the operating speed of the memory and hinders high-speed operation. One of the methods for solving this drawback is to provide a memory in which a plurality of banks are provided inside the memory, and a high-speed operation is enabled by alternately accessing different banks among the plurality of banks. This method is called an inter-bank interleaving method. According to this interbank interleave method, it is possible to activate a plurality of banks at the same time, and when accessing a different bank, a control signal Pre for extinguishing the charge on the address line to the previously accessed bank is used. Need not be applied, and therefore
Since the time slot can be shortened by the timing of applying the control signal Pre, high-speed operation becomes possible.

FIG. 10 shows the write timing of the memory operating in the interleave system between banks. FIG.
A indicates a bank designation signal. In the time slot T1, the bank # 0 is accessed, but in the next time slot T2, the bank # 3 is specified, and a different bank is specified for each time slot. FIG. 10B shows the application timing of the address signal. In this figure, each time slot T1, T2.
X address Row0 or Row in the first two cycles of
1 to the address input pin, and the Y address CO in the latter two cycles of each time slot T1, T2.
The case where L ₀₀ to COL ₀₃ and COL ₁₀ to COL ₁₃ are applied to the address input pin is shown.

As a control signal, an ACT command is applied at an initial phase position of each of the time slots T1, T2,..., And a write command Write is applied at a center timing of each of the time slots T1, T2,. Data WD ₀₀ , WD ₀₁ , W
D _02, WD ₀₃ ... applies the data _{WD 00 ~WD 03, WD 10,} WD 13 in synchronization with the write command Write.
In this case as well, the X address Row0 and the Y address COL are used.
_{The case} where the address determined by ₀₃ is defined as the charge 0 area and the data WD ₀₃ to be written to this address is / WD ₀₃ whose polarity is inverted is shown. The memory operating at the write timing shown in FIG. 10 can operate at high speed.

By the way, if the memory operating at the write timing shown in FIG. 10 is tested by the conventional memory test device shown in FIG. 6, the detection of the charge 0 area becomes impossible, and the correct test cannot be performed. Inconvenience occurs. This will be described with reference to FIG. In the conventional memory test apparatus, the cycle delay unit 40 is
Therefore, the cycle delay unit 40 cannot independently give a time difference to both the X address signal and the Y address signal before time division multiplexing. Therefore, the Y address signals COL _{01 to} COL ₁₃ and the data WD ₀₀
～WD ₁₃ should be generated with a delay from the already X address signal in the pattern generating section 10.

In FIG. 11, the Y addresses COL _{00 to} COL ₁₃
And data WD _{00 to} WD ₁₃ correspond to X address signals Row0 and R
This shows a situation where the output from the pattern generator 10 is delayed by two cycles from the initial phase of ow1. When a delay time of two cycles is given to the Y address signals COL _{00 to} COL ₁₃ and output from the pattern generation unit 10, the X address is Row 0 and the Y address is COL ₀₃ as the charge 0 area.
Is specified, the Y address COL ₀₃ becomes the time slot T
1 and is output from the pattern generator 10 at the time of the next time slot T2.

[0024] As a result, the data inversion control unit 14 shown in FIG. 6 will not be able to detect the X address Row0 and Y addresses COL ₀₃ within the same time slot T1, the detection of the charge 0 region correctly You can't. An object of the present invention is to enable high-speed operation by an interleave method between banks, operate by designating a charge 1 area and a charge 0 area, and furthermore, an X address signal and a Y address signal are applied to the same input pin with a time difference. It is an object of the present invention to propose a memory test apparatus capable of correctly testing a memory of a type of holding and applying.

[0025]

According to a first aspect of the present invention, a plurality of pattern signals output by a pattern generating section for each same time slot are selected and extracted for a channel corresponding to an input pin of a memory under test. A pin data select unit, a plurality of cycle delay units that provide a time difference for arranging each of the pattern signals selected by the plurality of pin data select units in the time series direction, and the plurality of cycle delay units. A multiplexing circuit for time-division multiplexing a pattern signal is proposed.

According to a second aspect of the present invention, in the memory test apparatus according to the first aspect, a predetermined specific address is determined from an address signal among a plurality of pattern signals output to the same time slot by a pattern generator. We propose a memory test device having a configuration provided with a data inverting unit for detecting and inverting a logical value of pattern data to be written to a specific address. In claim 3 of the present invention,
3. The memory test apparatus according to claim 1, wherein
A memory test apparatus is proposed in which a pattern signal output for each time slot is a pattern signal capable of executing an interleave test between banks for writing and reading by designating different banks of a memory under test.

[0027]

According to the memory test apparatus proposed in claim 1 of the present invention, since a cycle delay section is provided in the preceding stage of the multiplexing circuit, multiplexing is performed on each of a plurality of pattern signals output from the pattern generating section. Any time before can be independently delayed. As a result, different pattern signals can be time-division multiplexed in the multiplexing circuit according to the delay time, so that it is not necessary for the pattern generation section to provide each pattern signal with a delay time for time division multiplexing.

Therefore, even if an arbitrary address is designated as a charge area in the same time slot, the pattern generator can detect the designated address in the same time slot. . As a result, an arbitrary address can be designated as the charge 0 area and a normal operation can be performed. Further, as proposed in claim 3, even when testing a memory operating at high speed by an inter-bank interleave method in which a different bank is accessed for each time slot, an address specified in the same time slot is detected. be able to. Therefore, there is obtained an advantage that a memory test apparatus capable of accurately testing a memory operating in the interleave system between banks can be provided.

[0029]

FIG. 1 shows an embodiment of a memory test apparatus according to the present invention. In FIG. 1, portions corresponding to those in FIG. 6 are denoted by the same reference numerals, and description of overlapping portions will be omitted. The characteristic feature of the present invention is that a cycle delay unit 40 is provided at a stage preceding the multiplexing circuit 30. The cycle delay unit 40 is provided before the multiplexing circuit 30.
, It is necessary to separately provide a cycle delay unit separately for the pattern signal applied to the memory under test 50 and for the expected value data.

The embodiment shown in FIG. 1 shows an example in which cycle delay circuit groups 41A and 41B are provided for pattern signals, and cycle delay circuit groups 41C and 41D are provided for expected value data. In the multiplexing circuit 30, a multiplexer group 31A is provided as a multiplexing circuit for pattern signals, and the multiplexer group 31A is provided as a multiplexing circuit for expected value data.
B is provided. Furthermore, these multiplexer groups 31A,
31B, the pattern select signals SELA, SLLB and S
Cycle delay circuit group 4 for applying ELA 'and SELB'
This shows a case in which 1E and 41F are provided.

According to the configuration of the present invention, the multiplexing circuit 30
, A cycle delay unit 40 is provided at the preceding stage, and the cycle delay unit 40 can give a time difference for time division multiplexing to each pattern signal. Therefore, it is not necessary for the pattern generator 10 to generate the signal by giving a time difference between the X address signal and the Y address signal, for example. Therefore, the Y address does not shift to another time slot, and the data inversion control unit 14 can detect the charge 0 area regardless of which Y address is set in the charge 0 area.

The operation of the memory test apparatus according to the present invention shown in FIG. 1 will be described with reference to timing charts shown in FIGS. In the memory test apparatus according to the present invention, each of the pattern signals selected and taken out by the pin data select units 21A and 21B for the channel corresponding to each input pin of the memory under test 50 is independently and arbitrarily given an arbitrary delay time. The configuration is characterized by providing the parts 41A to 41D. By providing the cycle delay units 41A to 41D, the pattern generation unit 10 allows the bank designation signal, the X address signal, the Y address signal,
All of test pattern data TPDAT, pattern data output PDAT, control signal MUTSiG, and pattern select signal patsel can be generated in the same phase.

In the example shown in FIGS. 2 to 4, the memory under test 5
0 is the Y address COL applied internally₀₀Following
Three Y addresses (COL₀₁, COL₀₂, COL₀₃)
Is generated in the case of a 4-burst length. Therefore 4
The number of Y address generation cycles is one time slot.
Can be set to the shortest cycle. In addition, each time
Designate a different bank for each lot T1, T2, T3 ...
Operate the memory under test 50 by the interleave method between banks.
This shows the situation for testing. In the pattern generator 10
Is the generated Y address signal COL₀₀, COL₀₁, COL
₀₂, COL₀₃Address signal without delay time
No.COL₀₀, COL₀₁, COL₀₂, COL₀₃Output
Therefore, the data inversion control unit 14 shown in FIG.
Signal Row0 and Y address signal COL₀₃The same tie
In the time slot T1.

[0034] As a result even when the X address signal Row0 and Y address signal COL ₀₃ specified charge 0 region, the data inversion control unit 14 and the X address signal Row0, a Y address signal COL ₀₃ in the same time slot T1 The data inverting unit 15 can detect X by this detection signal.
An address signal Row 0, Y address COL inverts the logic of the data WD ₀₃ to be written to the determined address _03, / WD ₀₃ which is logically inverted from the pattern generator 10
(See FIG. 2E). The X address signal and the Y address signal output from the pattern generation unit 10, the pattern data PDAT, the control signal MUTSiG
Are input to the pin data select units 21A and 21B, respectively.

FIG. 3 shows the operation of the multiplexing circuit 30.
As shown in FIG. 3A, the pin data select unit 21A is set so that a channel corresponding to the bank designating pin of the memory under test 50 and a bank designating signal and an X address signal are selected and taken out for the channel corresponding to the address input pin. Show the case. The bank designation signal extracted by the pin data selection unit 21A and the X address signals Row0, R
ow1, Row0,... are passed through the cycle delay unit 23A without giving a delay time. On the other hand, the pin data select unit 21B sets a state where the bank designation signal and the Y address signal are selected and taken out as shown in FIG. 3B. The bank designation signal extracted by the pin data selection unit 21B and the Y address signal are
B, and the cycle delay unit 23B delays the address generation cycle by two cycles as shown in FIG. Accordingly, the multiplexer 31A constituting the multiplexing circuit 30 converts the undelayed bank switching signal and the X address signal output from the cycle delay unit 23A, the bank designation signal delayed by two cycles and the Y address signal into the time slot cycle. By switching with
As shown in FIG. 4B, the address signal is applied to the address input terminal of the memory under test 50 after the X address and the Y address are time division multiplexed.

The data WD _{00 to} WD ₁₃ shown in FIG. 2C and the control signals ACT, Write, and Read shown in FIG. 2E are taken out from both the pin data select units 21A and 21B, and the multiplexing circuit 30 is used by the pin data select unit. 21
No matter which of A and 21B is selected, it is taken out to the output side of the multiplexing circuit 30. In this case, the write data WD _{00 to} W
Cycle delay unit 41A and 41B of the channel taken out D ₁₃ gives both data WD ₀₀ ~WD 2 cycle of latency relative to _13. Control signals ACT, Writ
For e and Read, the cycle delay circuit groups 41A and 41A
1B shows a case where the light is passed without giving a delay time.

FIGS. 2 to 4 show a case where the read command Read is executed in the time slot T3. Therefore, in this case, in the time slot T3, the expected value data EX ₀₀ ,
EX ₀₁ , EX ₀₂ , and EX ₀₃ are output. The expected value data EX _{00 to} EX ₀₃ are input from the pin data select section 21A to the cycle delay circuit group 41C for the expected value signal, and the cycle delay circuit group 41C gives a delay of four cycles as shown in FIG. 3D. The read data RD ₀₀ , RD ₀₁ , RD of the memory under test 50 input from the multiplexing circuit 30 to the logical comparison unit 60 and input to the logical comparison unit 60
₀₂ and RD ₀₃ .

The read data RD _{00 to} RD ₀₃ read from the memory under test 50 are the pattern data WD ₀₀ to RD _03.
/ WD ₀₃ , and output to the same data bus as the transmission paths of WD _{10 to} WD ₁₃ . Therefore, as shown in FIG. 4D, the pattern data WD ₀₀ to / WD ₀₃ and WD _{10 to} WD ₁₃ are written on the same data line. Further, the read data RD _{00 to} R
_D03 indicates a case where the data is output at a timing delayed by two cycles from the write timing in this example. Therefore,
The delay time of 4 cycles of delay in consideration of the time expected value data EX ₀₀ ~EX ₀₃ is set, the expected value data EX ₀₀ ~
The timing of EX ₀₃ and the read data RD _{00 to} RD ₀₃ are matched.

[0039]

As described above, according to the present invention, when data is written in the charge 0 area even in a memory operated by the inter-bank interleave method, the data to be written is inverted and applied to the memory under test. be able to. As a result, an effect is obtained that a memory operating in the interleave interleave method can be correctly tested.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a memory test apparatus according to the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a timing chart similar to FIG. 2;

FIG. 4 is a timing chart similar to FIG. 2;

FIG. 5 is a timing chart for explaining a write timing of a conventional memory.

FIG. 6 is a block diagram for explaining a conventional memory test device.

FIG. 7 is a timing chart for explaining the operation of the conventional memory test device shown in FIG.

FIG. 8 is a timing chart similar to FIG. 7;

FIG. 9 is a timing chart similar to FIG. 7;

FIG. 10 is a timing chart for explaining a write timing of a memory that operates in an interleave method between banks.

FIG. 11 is a timing chart for explaining inconvenience when the write timing shown in FIG. 10 is executed by the memory test apparatus shown in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Pattern generation part 11 Address generation part 12 Data generation part 13 Control data generation part 14 Data inversion control part 15 Data inversion part 20 Select part 21A, 21B Pin data select part 30 Multiplexing circuit 31A, 31B Multiplexer group 40 Cycle delay part 41A ~ 41F Cycle delay circuit group 50 Memory under test 60 Logic comparison unit

Claims (3)

[Claims] 1. A plurality of pin data selectors for selecting and extracting a plurality of pattern signals output from a pattern generator for each same time slot to a channel corresponding to an input pin of a memory under test, and B. A plurality of cycle delay units for providing a time difference for arranging in the time series direction each of the pattern signals selected by the pin data selection unit, and C. the pattern signals delayed by the plurality of cycle delay units are time-division multiplexed. And a multiplexing circuit. 2. The memory test apparatus according to claim 1, wherein
Data inversion for detecting a predetermined specific address from address signals among a plurality of pattern signals which the pattern generator outputs to the same time slot, and inverting a logical value of pattern data to be written to the specific address. A memory test device characterized by comprising a unit. 3. A memory test apparatus according to claim 1, wherein the pattern signal output for each time slot designates a different bank of the memory under test and writes and reads between the banks. A memory test device, which is a pattern signal capable of executing the following.