JP2002149282A - Power supply controlling means and information processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption from a battery by maintaining a power- off operation without contradiction even though the operation of a microcomputer 13 is stopped or falls into an insufficient state. SOLUTION: A power supplying means such as a battery and a load is connected by a MOSFET switch which has a few leakage current and a little of forward voltage drop, interruption is controlled, and the connection and interruption control state is controlled while being held by using a latch composed of a CMOS circuit driven by the battery. The MOSFET switch is continuously interrupted and a stable operation can be obtained because the state can be held by resetting the latch even though a signal of a controlling part becomes unstable. Since the latch is a CMOS and the leakage current is extremely small, power consumption from the battery can be reduced when the power is turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reducing the power consumption of a power supply means such as a battery when a power supply is turned off in an information processing apparatus driven by a battery or the like.

[0002]

2. Description of the Related Art In recent years, portable information processing apparatuses such as notebook personal computers have been assumed to be used outdoors, and can be operated with a secondary battery. Increasing the capacity of the secondary battery increases the size and weight of the battery, and thus it is important to reduce the power consumption of the battery.

Further, in the operation of turning on and off the power, especially when the power is turned off, it is necessary to perform an internal termination process of the information processing apparatus, so that the power supply cannot be forcibly shut off by a mechanical power switch. 2. Description of the Related Art A signal is transmitted only when a push-type power switch is operated, a termination process is performed by software after receiving an operation, and power supply is cut off. The push-type power switch also detects the power-on instruction, so even when the information processing device is not in operation, the power control microcomputer always keeps on monitoring, and the current consumed by the power control microcomputer when not in operation Was about several mA and could not be ignored.

A conventional method of monitoring a power switch will be described with reference to FIG. 5, and a specific operation timing will be described with reference to FIG.

FIG. 5 shows a circuit configuration of a conventional information processing apparatus. 51 is a battery for supplying power to the information equipment,
52 is a voltage converter (hereinafter referred to as DC / DC converter) for using the supplied power in the system, 53 is a power control microcomputer (hereinafter referred to as microcomputer), and 55 is for turning on / off the power of the information equipment. A power switch 56, a MOSFET for a power supply switch from a battery to a DC / DC converter, and 57 a load in the system. The load is an information processing device including, for example, a CPU and a memory, and is the same as a general information processing device. Q51 and Q52 are transistors controlled by the microcomputer 53. D50 is located between the power switch 55 and the microcomputer 53, monitors the state of the power switch 55, notifies the microcomputer 53,
This is a diode inserted in order to prevent a current from flowing backward from the microcomputer to the microcomputer 53.

When the power switch 55 is turned on, the MOSF
The gate of ET56 is turned on at low level, and DC /
The voltage converted by the DC converter 52 is
And the microcomputer 53 are started, the microcomputer 53 is activated, and the transistor Q51 is always on.
OSFET 56 also remains on. Even if the power switch 55 is released in this state, the MOSFET 56 is kept on by the transistor Q51.

When the power is turned off, for example, Windows
When the termination processing for the load 57 is completed by performing the termination processing of the OS such as ws, the microcomputer 53 outputs the control signal #P
The WRGOOD signal is set to High, and the transistor Q52
Is turned on and Q51 is turned off, so that the #Gate signal becomes High, the MOSFET 56 is turned off, and the power supply from the battery 51 is stopped.

FIG. 6 shows the timing of the power on / off operation.

First, the case where the user turns on the power will be described.

At time t60, the power supply is off immediately after the battery 51 is connected. Since the power switch 55 and the #Gate signal are pulled up to the battery 51, they are in a High (battery voltage) state.
The WRGOOD signal is low because it is grounded,
51 is off, MOSFET 56 is off, and D
Power supply to the C / DC converter 52 is stopped.
Then, the output voltage Vdd is not output.

When the power switch 55 is turned on at time t61, the #Gate signal goes low. At this time, the #PWRGOOD signal is undefined. MOSFET56
Turns on. Power is supplied to the DC / DC converter 52, and at time t62, Vdd is output.
3 starts. At time t63, the microcomputer 53 monitors the state of the power switch 55 via the diode D50, and determines that the state is at the low level, that is, the power switch 5
Check that 5 is operated. At time t64, the #PWRGOOD signal is fixed to Low, and the transistor Q52 is turned off. Therefore, the output voltage Vdd of the DC / DC converter 52 causes the transistor Q51 to be turned off.
Turns on. The microcomputer 53 holds this state.

Next, a case where the user turns off the power will be described.

At time t65, when the user operates the power switch 55, the microcomputer 53 switches the diode D50.
The state of the power switch 55 is monitored via the
Is subjected to system termination processing by software processing. At the time t66, when the end processing by the software processing is completed, the microcomputer 53 sends #PWRGOO
The D signal is driven high, and the transistor Q51 is turned off to turn on the transistor Q52. At time t67, since the #Gate signal changes from low to high, the MOSFET 56 is turned off. Time t68
Output voltage Vd from DC / DC converter 52 at
d is turned off, and the supply of Vdd to the microcomputer 53 is stopped.

Since Vdd is off after time t69,
Since the input of the transistor Q51 is grounded to Low, the MOSFET 5 is kept in a state where the #Gate signal is High.
6 maintains the off state. In this way, unless the power switch 55 is operated, no power is consumed from the battery 51 when the battery 51 is connected.

[0015]

In the conventional method, after Vdd becomes 0 V after time t69, the transistor Q is turned off.
The #Gate signal is maintained at a high level because the input of the microcomputer 51 is grounded.
3 cannot hold the #PWRGOOD signal High (the power is not supplied to the microcomputer 53 itself, so the operation is undefined, or the power reset is activated by detecting the voltage of the microcomputer or an external circuit). Since the transistor Q52 cannot be completely turned on, there is a possibility that the Vdd voltage that has not completely reached 0 V turns on the Q51. Therefore, depending on circuit constants, the #Gate signal is switched to Low immediately after the power is turned off, and the DC / DC converter 52 outputs Vdd again and returns to the power-on state.

An object of the present invention is to enable the microcomputer 53 to stop its operation or fall into an indeterminate state, maintain the power-off operation without inconsistency, and reduce the power consumption from the battery.

[0017]

In order to solve this problem, the present invention provides an MO having a small leakage current and a small forward voltage drop between a power supply means such as a battery and a load.
A connection and disconnection control is performed by an SFET switch, and the connection and disconnection control state is controlled by a battery driven CMOS.
It controls while holding using a latch consisting of a circuit, sets the latch by a mechanical switch operation, and resets the off control signal latch to hold the power on / off control state, thereby connecting the MOSFET switch. Control. When the power is turned off, the state can be held by resetting the latch with a signal from a control unit such as a microcomputer, so that even if the signal of the control unit becomes unstable, the MOSFET
Stable operation can be obtained because the switch is kept off.
Further, since the latch is a CMOS and the leakage current is extremely small, power consumption from the battery when the power is turned off can be reduced.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention according to claim 1 of the present invention provides a power supply means such as a battery, a load which operates by receiving power supply, and an instruction for on / off control of power supply to the load. Power switch means, a semiconductor switch means for connecting and disconnecting a current flowing from the power supply means to the load, a latch means for holding a control state of the semiconductor switch means, and a control means for resetting the latch means. The latch means operates by receiving power supply from the power supply means, is set by operating the power switch means, and is reset by the control means. A power supply control means for an information processing device, which maintains a reset state even when a signal is interrupted, and a current control device when the device is not operating. Costs can requires extremely reduced, yet it has an effect of reliably can maintain the state of the relationship without power-off to the operating state of the control means.

According to a second aspect of the present invention, there is provided a power supply means such as a battery, a load operated by receiving power supply, a power supply switch means for instructing on / off control of power supply to the load, and Semiconductor switch means for connecting and disconnecting a current flowing from the power supply means to the load, latch means for holding a control state to the semiconductor switch,
Control means for resetting the latch means, wherein the latch means is set by operating the power switch means, and is reset by the control means;
Once in the reset state, even if the signal from the control means is interrupted, the reset state is maintained, the operation of the power switch means is notified to the control means, and when the power switch means is operated in the power-on state, the control is performed. Power supply control means for detecting that there is a power-off request, and turning on / off the power supply by turning off the semiconductor switch by enabling the reset signal of the latch means. Means that the semiconductor switch can be reliably turned off even in a device that shuts off the power after performing appropriate software processing at the end of the load by operating only one power switch. Have.

According to a third aspect of the present invention, the semiconductor switch means is a MOSFET and the latch means is a CM.
The power supply control means according to claim 1 or 2, wherein the power supply control means has an operation of reducing power consumption.

According to a fourth aspect of the present invention, the load is DC
3. The power supply means according to claim 1, wherein the power supply means is driven via a DC / DC converter, and the power switch means and the control means are connected via a backflow prevention diode. It can be used even when the voltage supplied from the controller and the voltage used in the load and the control unit are different.

According to a fifth aspect of the present invention, there is provided a first power supply means such as a battery, a second power supply means, a load which operates by receiving power supply, and an on / off control of power supply to the load. Power switch means for instructing off control; first semiconductor switch means for connecting and disconnecting a current flowing from the first power supply means to the load; and a control state for the first semiconductor switch means. First latch means, second semiconductor switch means for connecting and disconnecting a current flowing from the second power supply means to the load,
A second latch unit that holds a control state of the second semiconductor switch unit; and a control unit that resets the first latch unit and the second latch unit. When the switch is operated, the first latch is set, the first semiconductor switch is turned on, power is supplied from the first power supply to the load, and the second power is supplied to the load. The latch is set, the second semiconductor switch is turned on, and power is supplied from the second power supply to the load.

The control means also includes means for resetting the first latch means or the second latch means, and the control means resets the first latch means to reset the first latch means or the second latch means. Power supply control means for supplying power to the load from the second power supply means by stopping power supply to the load, or resetting the second latch means; Even in the case where there is a supply unit, there is an effect that power consumption when the power is turned off can be reduced.

According to a sixth aspect of the present invention, there is provided a first power supply means such as a battery, a second power supply means, a load which operates by receiving power supply, and a power supply to the load. Power switch means for instructing off control; first semiconductor switch means for connecting and disconnecting a current flowing from the first power supply means to the load; and a control state for the first semiconductor switch means. First latch means, second semiconductor switch means for connecting and disconnecting a current flowing from the second power supply means to the load,
A second latch means for holding a control state of the second semiconductor switch means, and a control means for resetting the first latch means and the second latch means, wherein the first semiconductor switch means It is in a conductive state, and operates by receiving power supply from the first power supply means,
Alternatively, when the second semiconductor switch is in a conductive state and the power switch is operated in a state where the second semiconductor switch is operated by receiving power supply from the second power supply, the controller controls the switch of the switch. After detecting an operation and performing termination processing on the load, the first power supply unit and the second power supply are reset by resetting the first latch circuit or the second latch circuit. Power supply control means for controlling power supply from the means to be stopped, and has an effect that a microcomputer switching operation can be programmably performed by a microcomputer.

According to a seventh aspect of the present invention, the first and second semiconductor switch means are MOSFETs, and the first and second latch means have a CMOS configuration. The power supply control means according to claim 6, which has an effect of reducing power consumption.

According to the present invention, the load is a DC load.
7. The power supply control means according to claim 5, wherein the power supply control means is driven via a DC / DC converter, and the power supply switch means and the control means are connected via a backflow prevention diode. When the voltage supplied from the power supply and the voltage used in the load and the control unit are different, especially when the voltage in the load is low, it can be used.

According to the ninth aspect of the present invention, there are provided the first to eighth aspects.
An information processing apparatus provided with a power supply control unit according to the above, wherein the battery consumes less even when left in a non-operation state for a long time,
This has the effect of realizing an information processing device with excellent storage characteristics.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

(Embodiment 1) FIG. 1 shows Embodiment 1 of the present invention.
1 shows a circuit configuration of an information processing apparatus that realizes the power control method of FIG. Reference numeral 11 denotes a battery, such as a secondary battery, which is a power supply unit when an electronic device such as an information device is mainly carried and used. Reference numeral 12 denotes a DC / DC converter.
The voltage supplied from 1 is converted to the voltage used in the load. Reference numeral 13 denotes a control unit called a power microcomputer of the information processing apparatus, which is a microcomputer that displays a remaining amount of a battery and controls power cutoff based on a user's power-off operation. 1
Reference numeral 4 denotes a latch having a set terminal (#S) and a reset terminal (#R) as inputs and a state output terminal (#
Q). In this embodiment, the input and output relating to the latch are set to negative logic for the sake of explanation. Power supply terminal (VC
C) is supplied with power from the battery 11 and operates.
The set terminal #S is pulled up to the battery voltage by the resistor R11. Similarly, the reset terminal #R is connected to the resistor R12
Is pulled up to the battery voltage. Reference numeral 15 denotes a power switch having mechanical contacts. 16 is MOSFET
, Which supplies and cuts off current to the information processing device. 17 is a load. D11, D1
Reference numeral 0 denotes a diode, which is connected between the input to the #S terminal of the latch 14 and the power switch 15 so that the input to the microcomputer 13 does not collide. FIG. 2 shows operation timings for realizing the power supply control method according to the first embodiment of the present invention.

Embodiment 1 of the present invention using FIGS. 1 and 2
Will be described in detail.

First, a case where the user turns on the power will be described.

At time t20 in FIG.
Indicates the state immediately after the connection. The input #S and the input #R to the latch 14 are High, the output #Q becomes High from the reset operation of the latch 14 itself after the power is turned on, and the MOSFE because the #Gate signal is High.
T16 is turned off, and power is not supplied to the DC / DC converter 12 and the load 17.

At time t21, the power switch 15 is turned on by the user. At time t22, the input #S of the latch 14 becomes Lo via the diode D11.
w, the output #Q of the latch 14 at time t23.
Becomes Low. #Gat by the output #Q of the latch 14
The e signal turns on the MOSFET 16.

When the MOSFET 16 is turned on, DC / D
Power is supplied to the C converter 12, Vdd is output at time t24, power is supplied to the load 17, and the microcomputer 13 is started.

At time t25, the microcomputer 13 monitors the state in which the power switch 15 is pressed (Low) via the diode D10, detects that the power switch 15 is correctly pressed by the user, Start a system. The microcomputer 13 is #BATO
The FF signal is held High, and the latch 14 is kept in the set state. Then, the set state of the latch 14 is maintained, and D
Voltage supply from the C / DC converter 12 to the load 17 is maintained. Note that the #BATOFF signal is assumed to be open drain. For example, in the case of a low-voltage output such as a TTL level, a circuit can be easily configured by adding an external transistor switch (in this case, the signal is BATOF).
When F is High, the input #R of the latch 14 can be driven Low. ).

Next, a case where the user turns off the power will be described.

At time t26, when the user operates the power switch 15, the microcomputer 13
And detects that the power switch 15 has been pressed, and performs a system termination process on the load 17 by software processing.

At time t27, when the end processing by the software processing is completed, the microcomputer 13 sends #BATO
The FF signal is output, and the input #R of the latch 14 becomes Low. The output #Q and #Gate signals of the latch 14 are H
becomes high, and the MOSFET 16 is cut off at time t28. At time t29, DC / DC converter 12
Of the load 17 and the microcomputer 13
Power supply to the power supply is lost.

At time t30, the operation of the microcomputer 13 becomes unstable due to an internal power reset operation or the like.
It is also conceivable that the ATOFF signal becomes High. However, since the output #Q of the latch 14 is held at High, the output Vdd of the DC / DC converter 12 is discharged to 0 V with the passage of time while the MOSFET 16 is kept shut off. The power supply to the load 17 is stopped and the load 17 is turned off.

In the off state, the power consumption is about several μA. For example, if the capacity of a fully charged battery is 1000 mAh and the power consumption for holding the state output of the latch is 10 μA, then theoretically 100
000 hours, which is more than 4000 days in terms of days, so that the remaining amount does not become 0% even if left for 10 years or more.

(Embodiment 2) FIG. 3 shows a circuit configuration of an information processing apparatus for realizing a power control method according to Embodiment 2 of the present invention. Reference numerals 31 and 41 denote batteries such as secondary batteries, which are power supply means when an electronic device such as an information device is mainly carried and used. Reference numeral 32 denotes a DC / DC converter, which converts a voltage supplied from the battery 31 or the battery 41 into a voltage used in a load. Reference numeral 33 denotes a control unit called a power microcomputer of the information processing apparatus, which performs a display of a remaining battery level and a power cutoff control based on a user's power-off operation. Latches 34 and 44 have a set terminal (#SA or #SB) and a reset terminal (#RA or #RB) as inputs and a status output terminal (#QA or #QB) as output. The power supply (VCC) of each of the latches 34 and 44 is supplied with power from the battery 31 or the battery 41 and operates. The set terminal #SA of the latch 34 is pulled up to the battery voltage by the resistor R31. Similarly, reset terminal #R
A is pulled up to the battery voltage by the resistor R32. The set terminal #SB of the latch 44 is pulled up to the battery voltage by the resistor R41. Similarly, the reset terminal #RB is pulled up to the battery voltage by the resistor R42.

Reference numeral 35 denotes a power switch having mechanical contacts, which is turned on only while the user presses the switch by hand. Reference numerals 36 and 46 denote semiconductor switches composed of MOSFETs, which supply and cut off current from the battery 31 or the battery 41 to the information processing device as the load 37, respectively. D31 and D41 are diodes which are inserted into the microcomputer 33 so that the inputs to the #SA terminal or #SB terminal of the latch 34 and the latch 44 do not collide with the microcomputer 33, respectively. Similarly, a diode D30 is inserted so that the high voltage of the battery 31 or 41 is not applied to the power switch detection input of the microcomputer 33.

D32 and D42 are diodes which connect the currents from the batteries 31 and 41 in common and
/ DC converter 32 to be input.
When the MOSFET 36 and the MOSFET 46 are turned on at the same time, power can be supplied to the DC / DC converter 32 from a higher voltage, and the power supply can be switched without a voltage drop when switching.

Q31 and Q41 are switches using transistors and resistors, and Q31 is an input terminal # of the latch 34.
The SA is controlled from the microcomputer 33. Similarly, Q41 controls the input terminal #SB of the latch 44 from the microcomputer 33.

When the output terminal of the microcomputer is an open drain, it is possible to omit Q31 and Q41 and directly connect to #SA and #SB, respectively.

FIG. 4 shows operation timings for realizing the power supply control method according to the second embodiment of the present invention. At a time t40, the state of the information processing apparatus immediately after the connection of the battery 31 and the battery 41 is shown. Input #SA and input # to latch 34
RA is High, the output #QA becomes High from the reset operation of the latch 34 itself after the power is turned on, and #G
Since the ateA signal is High, the MOSFET 36 is turned off, and power is not supplied from the battery 31 to the load 37. Similarly, the input #SB and the input #RB to the latch 44 are also High, and the output #QB becomes High due to the reset operation of the latch 44 itself after the power is turned on.
h, and since the #GateB signal is High, MO
Since the SFET 46 is turned off, power is not supplied to the load 37 from the battery 41.

At time t41, the power switch 35 is turned on by the user.

At time t42, the input #SA of the latch 34 becomes low via the diode D31. Similarly, the input terminal #SB of the latch 44 becomes Low via the diode D41.

At time t43, output #Q of latch 34
A becomes Low. Therefore, the #GateA signal is
The SFET 36 is turned on. Similarly, the output #QB of the latch 44 becomes Low. Therefore, the #GateB signal turns on the MOSFET 46. The line of the battery 31 passes through the diode D32, and the line of the battery 41 passes through the diode D42. Since the lines are connected by the diode OR, the DC / DC converter 3
2 is supplied with current and both outputs do not collide.

At time t44, voltage Vdd is output from DC / DC converter 32, and microcomputer 33 is started.

At time t45, the microcomputer 33 monitors that the user keeps pressing down the power switch 35 via the diode D30 (Low).
In the ow state, since the user has correctly operated the power switch 35, the system of the information processing apparatus as the load 37 is started. If the power switch 35 has changed to the high state, the operation of the power switch is not correct, so that the power-off process described later is performed without starting the system of the information processing apparatus.

When the power is released from the power switch, the signal goes high. At time t46, the inputs #SA and #SB are set to Hi.
gh. When priority is given to the power supply from the battery 31, the microcomputer 33 holds the #BATOFFA signal at High, and at time t47, turns the #BATOFFB signal to Low.
, The input #RB of the latch 44 becomes L
ow.

At time t48, output # of latch 44
QB becomes High, that is, #GateB signal becomes H
Since it becomes high, the MOSFET 46 is cut off from the battery 41. Therefore, in this case, power is supplied to the DC / DC converter 32 only from the battery 31.

Note that the #BATOFFA signal and the #BAT
The OFFB signal assumes an open drain. A low-voltage output (TTL level or the like) can be handled by adding an external transistor switch (in this case, the signal is BATOFFA or BATOFFB (positive logic), and the input terminal #RA of the latch 34 or the latch is high. 44 input terminal #RB can be driven low.)

When the power supply from the battery 31 is switched to the power supply from the battery 41, the following procedure can be used.

At time t49, the microcomputer 33
The BATOFFB signal is set to High. Therefore, the input #RB of the latch 44 also becomes High,
The state of QB does not change. At time t50, the microcomputer 33 turns on the transistor Q41, thereby driving the input #SB of the latch 44 to Low. At time t51, the output #QB of the latch 44 is Low (that is, #G
Since the ateB signal becomes Low), the MOSFET 46
Turns on, and the battery 41 passes through the diode D42.
To the DC / DC converter 32. Time t5
In step 2, the microcomputer 33 drives the #BATOFFA signal low, and the input #RA goes low. At time t53, the output #QA of the latch 34 becomes High (that is, #Gate).
Since the signal A becomes High), the MOSFET 36 is cut off. In this way, the power supply from the battery 31 can be switched to the power supply from the battery 41.

Next, a case will be described in which an instruction to turn off the battery 41 is issued after the end operation of the software processing is completed.

After performing a system termination process of the information processing apparatus which is the load 37 in response to a request such as a termination process of Windows or the like, the microcomputer 33 performs #BATOF at a time t54.
The FB signal is output low and input to the #RB terminal of the latch 44. At time t55, since the output #QB of the latch 44 becomes High (that is, the #GateB signal becomes High), the MOSFET 46 is cut off. At time t56, DC / DC converter 32
Is turned off, and the power supply to the microcomputer 33 is stopped. At time t57, the operation of the microcomputer 33 becomes unstable due to an internal power reset operation or the like.
TOFFA signal or #BATOFFB signal is High
h. However, the output of latch 34 is #
Since QA and the output #QB of the latch 44 are held High, the MOSFET 36 and the MOSFET 46
Is the output V of the DC / DC converter 32 while being shut off.
dd is discharged with time and becomes 0V. That is, the power supply to the load 37 is stopped and the load 37 is turned off.

When the user operates the power switch 35 to turn off the information processing device during operation, both #SA and #SB are once low, but the MO
Although the SFET 36 and the MOSFET 46 are connected at the same time, the microcomputer 33 monitors the state of the power switch 35 via the diode D30 and starts an end operation by software processing. The subsequent operation is the same as that described from time t54.

In this off state, the power is stopped by the MOSFET and only the leakage current of the latch circuit composed of CMOS is consumed, so that the power consumption is about several μA. For example, if it is assumed that a battery with a capacity of 1000 mAh when fully charged and the power consumption for holding the state output of the latch is 10 μA, then theoretically 100000
Since the time is converted into days, which exceeds 4000 days, the remaining amount does not become 0% even if left for more than 10 years.

In the above description, the battery 31 and the battery 4
Although the procedure for shutting down the battery 41 after the connection of the battery 1 at the same time has been described, it is also possible to shut off the battery 31 in the same manner. That is, the microcomputer 33 can perform the power switching operation of the battery 31 and the battery 41 in a programmable manner.

[0062]

As described above, according to the power supply control method of the present invention, the user operates one power switch in the same manner as the conventional information processing apparatus, so that the on / off control of the information processing apparatus can be performed. In addition to this, it is possible to significantly reduce the power consumption of the battery when the information processing apparatus is not operating and the power is off. Alternatively, in a system using a plurality of power supplies, a power supply switching operation can be performed programmably with a similar circuit configuration.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an information processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a timing chart of an operation according to the first embodiment of the present invention;

FIG. 3 is a circuit configuration diagram of an information processing apparatus according to a second embodiment of the present invention;

FIG. 4 is a timing chart of an operation according to the second embodiment of the present invention;

FIG. 5 is a circuit configuration diagram of an information processing apparatus in a conventional example.

FIG. 6 is a timing chart of the operation of the information processing apparatus in the conventional example.

[Explanation of symbols]

 11, 31, 41, 51 Battery 12, 32, 52 DC / DC converter 13, 33, 53 Microcomputer 14, 34, 44 Latch 15, 35, 55 Power switch 16, 36, 46, 56 MOSFET 17, 37, 57 Load

Claims (9)

[Claims] 1. A power supply unit such as a battery, a load that operates upon receiving power supply, a power switch unit that instructs on / off control of power supply to the load, and a power supply unit that supplies power to the load from the power supply unit. Semiconductor switching means for connecting and disconnecting a flowing current; latch means for holding a control state of the semiconductor switching means; and control means for resetting the latch means. The latch means supplies power from the power supply means. Operates in response to the signal, is set by operating the power switch means, and is reset by the control means,
Once in a reset state, the power control means of the information processing apparatus maintains the reset state even if a signal from the control means is cut off. 2. A power supply means such as a battery, a load which operates by receiving power supply, a power switch means for instructing on / off control of power supply to the load, and a power supply means for supplying power to the load from the power supply means. Semiconductor switch means for connecting and disconnecting a flowing current; latch means for holding a control state of the semiconductor switch; and control means for resetting the latch means, wherein the latch means operates the power switch means. And is reset by the control means, once in the reset state, holds the reset state even if the signal from the control means is interrupted, notifies the control means of the operation of the power switch means,
When the power switch is operated in the power-on state, the control means detects that there is a power-off request, and the reset signal of the latch means is enabled to turn off the semiconductor switch, thereby turning off the power. Power supply control means for controlling on / off of the power supply. 3. The method according to claim 2, wherein said semiconductor switch means is a MOSFET.
3. The power supply control means according to claim 1, wherein said latch means comprises a CMOS. 4. The power supply according to claim 1, wherein said load is driven via a DC / DC converter, and said power switch means and said control means are connected via a backflow prevention diode. Power control means. 5. A first power supply means such as a battery;
A second power supply unit, a load that operates by receiving power supply, a power switch unit that instructs on / off control of power supply to the load, and a current flowing from the first power supply unit to the load. A first semiconductor switch means for connecting and disconnecting, a first latch means for holding a control state to the first semiconductor switch means, and connecting a current flowing from the second power supply means to the load. A second semiconductor switch for shutting off, a second latch for holding a control state of the second semiconductor switch, a control for resetting the first latch and the second latch; When the power switch means is operated in a power off state,
The first latch means is set, the first semiconductor switch means is turned on, power is supplied from the first power supply means to the load, and the second latch means is set, The second semiconductor switch is turned on, and power is supplied from the second power supply to the load. The control unit also includes a unit that resets the first latch unit or the second latch unit, and resets the first latch unit by the control unit so that the first power supply unit supplies the load to the load. Power supply control means for supplying power from the second power supply means to the load by stopping power supply or resetting the second latch means. 6. A first power supply means such as a battery;
A second power supply unit, a load that operates by receiving power supply, a power switch unit that instructs on / off control of power supply to the load, and a current flowing from the first power supply unit to the load. A first semiconductor switch means for connecting and disconnecting, a first latch means for holding a control state to the first semiconductor switch means, and connecting a current flowing from the second power supply means to the load. A second semiconductor switch for shutting off, a second latch for holding a control state of the second semiconductor switch, and a control for resetting the first latch and the second latch. The first semiconductor switch means is in a conductive state, and operates by receiving power supply from the first power supply means, or the second semiconductor switch means When the power switch is operated in a conductive state and is operated by receiving power supply from the second power supply unit, the control unit detects the operation of the switch unit, and detects the operation of the switch unit. Resetting the first latch circuit or the second latch circuit to stop the power supply from the first power supply unit and the second power supply unit. A power supply control means for controlling. 7. The power supply control means according to claim 5, wherein said first and second semiconductor switch means are MOSFETs, and said first and second latch means have a CMOS configuration. . 8. The power supply according to claim 5, wherein said load is driven via a DC / DC converter, and said power switch means and said control means are connected via a backflow prevention diode. Power control means. 9. An information processing apparatus comprising the power supply control means according to claim 1.