JP2002141383A - Manufacturing method for semiconductor device and semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device and a semiconductor wafer for realizing an efficient probe inspection while reducing an integrated circuit chip. SOLUTION: Pads 4c and 4d for tests are provided on a division line 2 dividing a plurality of the integrated circuit chips 1. Switching circuits 6a-6d for turning ON/OFF the connection of a test circuit 3 inside the plurality of the integrated circuit chips 1, and the pads 4c and 4d for the tests arranged on the division line and switching pads 7a-7d for inputting switching signals for switching the switching circuits, are formed on the division line 2. Since the pads 4c and 4d for the tests, the switching circuits 6a-6d, and the switching pads 7a-7d on the division line are cut off at the time of division; a chip size is miniaturized without increasing the area of the semiconductor circuit chip 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a circuit inspection pad in a division line and a semiconductor wafer.

[0002]

2. Description of the Related Art FIG. 5, which is a first conventional example, shows a part of a semiconductor wafer, in which a plurality of integrated circuit chips 1 are divided and arranged by dividing lines 2 individually. In order to check whether the plurality of integrated circuit chips 1 are non-defective or defective, a probe is provided for pads 4 and 5 connected to the test circuit section 3 and arranged inside the integrated circuit chip 1. Each card is individually probed. The pad 4 is a test pad used only at the time of inspection, and the pad 5 is a bonding pad used even after being divided along the division line.

After that, the integrated circuit chip judged to be good by the inspection is divided along the division line 2, and the input / output operation of a desired signal is realized by the bonding pad 5.

In the configuration of the first conventional example, since the test pads 4 are arranged inside the integrated circuit chip 1, there is a problem that the chip size of the integrated circuit chip 1 increases by the area of the test pads. Had. Therefore, by arranging the test pads 4a on the dividing lines as shown in FIG. 6, which is a second conventional example, it was possible to form the integrated circuit chip 1 having a reduced area.

Further, as shown in FIG. 7, which is a third conventional example, a test pad 4b is connected and shared by a plurality of integrated circuit chips 1 to form a small area integrated circuit chip 1 with a reduced number of pads. It has been realized.

[0006]

However, in the above-described conventional configuration, when the test pads 4b are arranged on, for example, the right side of the integrated circuit chip 1, when a plurality of identical integrated chips 1 are arranged on a wafer, the integrated circuit is not integrated. Circuit chip 1
The test pads 4b are also arranged on the left side of the integrated circuit chip 1.
Is arranged. The same applies to the upper and lower parts. When the number of test pads 4b is large, the division line 2
Is embedded in the test pad 4b, and other devices,
For example, it has been difficult to arrange alignment marks and the like for an exposure machine, which are required when separating a semiconductor chip, on the division line 2.

When the test pads 4b are used as test signal output terminals of a plurality of integrated circuit chips 1,
Since the test signals are simultaneously output from the plurality of integrated circuit chips 1 to be connected, they cannot be shared as the plurality of test output terminals due to the collision of the test output signals.

Further, at least one of the plurality of integrated circuit chips 1 connected to the test pad 4b becomes defective, and the connection point to the test pad 4b is fixed at the signal level "1" or "0". In this case, even if any of the plurality of integrated circuit chips 1 connected to the same test pad 4b is a non-defective product, there is a problem that all of the integrated circuit chips 1 are determined to be defective products.

A test pad 4 is provided on the division line 2.
The test circuit unit 3 and the integrated circuit chip 1
The wiring length connecting the test circuit section 3 and the test pads 4b on the division line 2 is larger than the wiring length connecting the test pads 4b existing inside, and the integrated circuit chip 1
Of the integrated circuit chip 1, which increases the area of the integrated circuit chip 1.

[0010] Therefore, the present invention provides an alignment mark for exposure necessary for separating another device, for example, a semiconductor chip by forming a test pad on every other division line among a plurality of division lines. Can be easily arranged on a divided line having no test pad among a plurality of divided lines, and even if the test pad is used as a test signal output terminal of a plurality of integrated circuit chips, a collision of test output signals occurs. Test chips can be shared as test output terminals of multiple integrated circuit chips, and multiple integrated circuit chips can be individually judged to be good or defective, and the amount of wiring occupied by integrated circuit chips Semiconductor device manufacturing method and semiconductor wafer capable of reducing the area of an integrated circuit chip by reducing An object of the present invention is to provide a.

[0011]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a plurality of integrated circuit chips and a plurality of division lines on a semiconductor wafer; and connecting to a test circuit inside the integrated circuit chip. Forming a test pad on every other split line of the plurality of split lines, connecting the test pad to a test circuit in an integrated circuit chip on both sides of the test pad by shared wiring, and Testing the integrated circuit chip using the pads; and separating the plurality of integrated circuit chips by dividing the semiconductor wafer along the dividing lines.

According to the method of manufacturing a semiconductor device of the present invention, the test pads are formed on every other one of the plurality of divided lines, thereby isolating other devices, for example, a semiconductor chip. A plurality of semiconductor devices can be manufactured while facilitating disposing alignment marks and the like for an exposure machine necessary for the above operation on a division line on which a test pad is not formed among a plurality of division lines.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
A plurality of integrated circuit chips and a plurality of division lines are formed on a semiconductor wafer, test pads connected to a test circuit inside the integrated circuit chip are formed on the plurality of division lines, and the test pads are used as both test pads. A step of connecting a shared wiring to a test circuit in an adjacent integrated circuit chip;
A switching circuit for turning on and off a connection between a test circuit inside a plurality of integrated circuit chips and a test pad arranged on a division line is formed on a shared wiring,
Forming a switching pad for inputting a switching signal for switching the switching circuit on the divided line, inputting the switching signal to the switching circuit using the switching pad, and testing pads and a test circuit inside the integrated circuit chip A step of individually testing integrated circuit chips on both sides of a division line by electrically connecting and disconnecting the circuit, and a step of separating a plurality of integrated circuit chips by dividing a semiconductor wafer along the division line And a step of performing.

According to the semiconductor device manufacturing method of the present invention, even if the test pads are used as test signal output terminals of a plurality of integrated circuit chips, the plurality of test pads can be integrated without collision of test output signals. A plurality of integrated circuit chips can be shared as test output terminals of circuit chips, and a plurality of semiconductor devices can be manufactured while individually determining a plurality of integrated circuit chips as non-defective or defective.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
In addition to the manufacturing method of the first aspect, the connection points of the plurality of integrated circuit chips connected to the test pads use the same function input / output connection points.

According to the method of manufacturing a semiconductor device according to the third aspect, the same effect as that of the method of manufacturing a semiconductor device according to the second aspect can be obtained, and a plurality of test functions having the same function can be provided on one test pad. Even if output connection points are connected, each integrated circuit chip can be tested without collision of input / output signals.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
2. The method according to claim 1, wherein a plurality of integrated circuit chips are formed on the semiconductor wafer such that test circuits inside the plurality of integrated circuit chips are arranged line-symmetrically with respect to the division line. I do.

According to the method of manufacturing a semiconductor device of the fourth aspect, the same effects as those of the first aspect are exhibited, and the area per integrated circuit chip is reduced by reducing the amount of wiring occupying the integrated circuit chip. A plurality of semiconductor devices can be manufactured while reducing the number.

According to a fifth aspect of the present invention, there is provided a semiconductor wafer comprising a plurality of integrated circuit chips and a plurality of division lines for dividing the plurality of integrated circuit chips, and a plurality of test pads connected to a test circuit inside the integrated circuit chip. And the test pad is connected to a test circuit in an integrated circuit chip on both sides of the test pad by shared wiring.

According to the semiconductor wafer of the fifth aspect, by providing the test pad on every other division line among the plurality of division lines, another device, for example,
Exposure alignment marks and the like required for separating a semiconductor chip can be easily arranged on a division line having no test pad among a plurality of division lines.

According to a sixth aspect of the present invention, there is provided a semiconductor wafer comprising a plurality of integrated circuit chips and a dividing line for dividing the plurality of integrated circuit chips, wherein a test pad connected to a test circuit inside the integrated circuit chip is provided on the dividing line. And the test pads are connected to the test circuits inside the integrated circuit chip adjacent to the test pads by shared wiring, and the connection between the test circuits inside the plurality of integrated circuit chips and the test pads is turned on / off. Switching circuit to be provided on the shared wiring,
A switching pad for inputting a switching signal for switching a switching circuit is formed on a divided line.

According to the semiconductor wafer of the present invention, even if the test pads are used as the test signal output terminals of the plurality of integrated circuit chips, the test pads can be formed on the plurality of integrated circuit chips without collision of test output signals. Can be shared as a test output terminal.

According to a seventh aspect of the present invention, there is provided a semiconductor wafer according to the sixth aspect.
In addition to the configuration of the semiconductor wafer described above, the connection points of the plurality of integrated circuit chips connected to the test pads are the same function input / output connection points.

According to the semiconductor wafer of the present invention, the same effects as those of the sixth embodiment can be exhibited, and the test pad can be used as a test signal input / output terminal of a plurality of integrated circuit chips. The test pads can be shared as test input / output terminals of a plurality of integrated circuit chips without collision.

The semiconductor wafer according to the eighth aspect is the fifth aspect.
In addition to the configuration of the described semiconductor wafer, the test circuits inside the plurality of integrated circuit chips are arranged line-symmetrically with respect to the division line where the test pads shared with the plurality of integrated circuit chips are arranged. It is characterized by the following.

According to the semiconductor wafer of the eighth aspect, in addition to the same effect as that of the fifth aspect, the area of the integrated circuit chip can be reduced by reducing the amount of wiring occupying the integrated circuit chip.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a part of a semiconductor wafer according to a first embodiment of the present invention.

In FIG. 1, reference numerals 1 and 1a to 1d denote integrated circuit chips, 2 denotes a dividing line for dividing a plurality of integrated circuit chips 1 after inspection, 3 denotes a test circuit inside the integrated circuit chip 1, and 4c and 4d denote test circuits. Input / output test pads 5 for testing using a test circuit are used during testing and actual use. 7a and 7b are switching circuits 6a and 6b for switching on / off the connection between the test pad 4c and the test circuit 3.
7c and 7d input signals for controlling the switching circuits 6c and 6d for switching on and off the connection between the test pad 4d and the test circuit 3. It is a switching pad.

As shown in FIG. 1, a semiconductor wafer according to this embodiment has a plurality of integrated circuit chips 1 divided by dividing lines 2 on a wafer, and the integrated circuit chip 1 is a non-defective or defective product. Is provided inside the integrated circuit chip 1, and test pads 4c and 4 arranged in the division line 2 are provided.
d and the probe are brought into contact with the pad 5 to make the integrated circuit chip 1
Carry out inspections.

The integrated circuit chips 1a and 1b are arranged vertically adjacent to each other in FIG.
Test pad 4c on division line 2 dividing
Are arranged, and the test pads 4c are connected to the test circuit 3 inside the integrated circuit chips 1a and 1b, respectively.

A switching circuit 6a is provided on a connection line on the division line 2 for connecting the test pad 4c and the test circuit 3 inside the integrated circuit chip 1a, and a control for controlling on / off of the switching circuit 6a. A switching pad 7a for inputting a signal is provided on the division line 2.

By inputting a signal to the switching pad 7a and turning on / off the switching circuit 6a, the connection between the test pad 4c and the test circuit 3 inside the integrated circuit chip 1a can be turned on / off. . Similarly, a switching circuit 6b is provided on a connection line on the division line 2 connecting the test pad 4c and the test circuit 3 inside the integrated circuit chip 1b, and a control signal for controlling ON / OFF of the switching circuit 6b is input. The switching pad 7b is provided on the division line 2.

For example, by inputting a signal to the switching pads 7a and 7b so as to turn on the switching circuit 6a and turn off the switching circuit 6b, the test pad 4c and the test circuit 3 inside the integrated circuit chip 1a are electrically connected. And the test pad 4c and the test circuit 3 inside the integrated circuit chip 1b are electrically disconnected.

Therefore, even when a probe test is performed on the integrated circuit chips 1a and 1b at the same time, the test result output to the test pad 4c is that of the integrated circuit chip 1a without collision of test signals. Thereafter, by changing the input signals of the switching pads 7a and 7b to turn off the switching circuit 6a and turn on the switching circuit 6b, the test result output to the test pad 4c becomes that of the integrated circuit chip 1b, and is the same as that in the test. Measurement becomes easy.

Further, the test pad 4d and the integrated circuit chip 1 are similarly placed on the division line 2 for dividing the integrated circuit chips 1a and 1c arranged right and left side by side in FIG.
By arranging the switching circuits 6c and 6d and the switching pads 7c and 7d for controlling the connection with the test circuit 3 inside each of the circuits a and 1c, it is possible to individually test.

As described above, according to this embodiment, even when the test signals are simultaneously output from the plurality of integrated circuit chips 1 to the test pads 4 arranged on the division lines 2, the test output signals are output. Test can be performed without collision, and the number of test pads 4 arranged on the division line can be reduced by sharing the test pads 4.

Further, one of the integrated circuit chips connected in common, for example, the integrated circuit chip 1b is defective,
Even when the test output result of the test circuit 3 inside the integrated circuit chip 1b is fixed to the high level output or the low level output, the test output of the test pad 4c is fixed by turning off the switching circuit 6b. Without this, the test of the other integrated circuit chip 1a can be performed normally.

Since the test pads 4c and 4d are commonly connected as input / output terminals of the same function, the test pads 4c are arranged on the upper side of the integrated circuit chip 1a and the test pads 4d are arranged on the left side as shown in FIG. All integrated circuit chips can be tested without placing test pads on the lower and right sides. Therefore, since there is a division line 2 in which a test pad is not arranged for every other division line 2 in which a plurality of lines exist, another device, for example, a semiconductor chip is separated even when the number of test pads increases. It is possible to easily arrange an exposure alignment mark or the like that is sometimes required.

The switching circuits 6a to 6d
Further, since the switching pads 7a to 7d are arranged on the dividing line and cut off when divided into individual integrated circuit chips, the chip can be downsized without increasing the area of the integrated circuit chip.

FIG. 2 is a plan view showing a part of a semiconductor wafer according to a second embodiment of the present invention. Reference numerals 1e to 1h denote integrated circuit chips, in which test circuits inside the integrated circuit chip are arranged symmetrically with respect to the divided lines 2, respectively. On the division line 2, test pads 4e
4h, switching circuits 6e to 6l, and switching pads 7e to 7l are arranged.

The test circuits inside the integrated circuit chips 1e and 1f are arranged symmetrically with respect to the division line 2 where the test pads 4e are arranged, and the switching circuits 6e,
Test pad 4e and integrated circuit chip 1e, which are controlled to be switched by 6f and switching pads 7e, 7f.
The internal test circuit 3 and the test circuit 3 inside the integrated circuit chip 1f are commonly connected.

By arranging the test circuit 3 inside the integrated circuit chip 1e above the integrated circuit chip 1e, the connection wiring connecting the test pad 4e and the test circuit 3 inside the integrated circuit chip 1e can be shortened. In addition, it is possible to suppress an increase in chip size due to connection wiring inside the integrated circuit chip 1e.

At this time, the test circuit inside the integrated circuit chip 1f is arranged symmetrically with respect to the division line 2 with respect to the test circuit inside the integrated circuit chip 1e. As a result, the connection wiring for connecting the test pad 4e and the test circuit 3 inside the integrated circuit chip 1f can be similarly shortened.

The test circuit inside the integrated circuit chip 1e and the test circuit inside the integrated circuit chip 1g are arranged in line symmetry with respect to the division line 2 where the test pad 4f is arranged, and the test circuit 3 inside the integrated circuit chip 1e is arranged. Is arranged at the upper left, the test circuit 3 inside the integrated circuit chip 1g is arranged at the upper right, and the connection wiring connecting the test pad 4f and the test circuit 3 can be shortened.

At this time, the test circuit 3 inside the integrated circuit chip 1h is also arranged at the lower right of the integrated circuit chip 1h, and similarly the test pads 4g and 4h and the test circuit 3
Can be shortened. As described above, by reducing the amount of connection wiring in all the integrated circuit chips, the size of the integrated circuit chip can be reduced.

The integrated circuit chip 1g and the integrated circuit chip 1h may be arranged symmetrically with respect to the division line 2. Similarly, the integrated circuit chip 1e and the integrated circuit chip 1f may be arranged with respect to the division line 2. May be arranged line-symmetrically.

FIG. 3 is a plan view showing a part of a semiconductor wafer according to a third embodiment of the present invention. An integrated circuit chip having four shapes of integrated circuit chips 1i to 11l is formed by performing line symmetric arrangement with respect to up, down, left and right.

In the case where the integrated circuit chip as shown in the figure is applied to, for example, a non-contact IC card chip, the pad used after the integrated circuit chip is divided is the corresponding one of the antenna coil pads 8a to 8h. Only pads are required. Since the antenna coil pads are respectively arranged in line symmetry, the pads 8a to 8d have the same function, and similarly the pads 8e to 8h have the same function.

FIG. 4 is a mounting diagram using a semiconductor device showing a third embodiment of the present invention, and is an embodiment in which the integrated circuit chip of FIG. 3 is cut out along a dividing line and used. The integrated circuit chip 1i is mounted on the sheet coil antenna 9, and the antenna coil pads 8a and 8e are connected to the antenna.

At this time, an integrated circuit chip 1j having another shape
When the antenna coil pads 11a to 11l are mounted on the sheet coil antenna 9, the antenna coil pads 8a to 8d and the antenna coil pads 8e to 8h are pads having the same function, respectively. No. 4 antenna coil pads 8a and 8
Since e may be connected in reverse, the four integrated circuit chips 1i to 1l must be mounted on the same sheet coil antenna 9 without considering the arrangement position due to the difference in the shape of the integrated circuit chip. Becomes possible.

Further, the test pads 4c to 4h may be connected not only to the left and right but also to a plurality of adjacent integrated circuit chips such as vertically and obliquely, and the switching pads 7a to 7l may be connected by a single switching pad. May be able to control the on-off of the switching circuit.

Note that the arrangement of the test circuits inside the plurality of integrated circuit chips may be line-symmetric only up and down with respect to the division line, or may be line-symmetric only with the left and right.

[0053]

According to the method of manufacturing a semiconductor device according to the first aspect of the present invention, a test pad is formed on every other division line among a plurality of division lines, so that another device such as a semiconductor chip is formed. It is possible to manufacture a plurality of semiconductor devices while facilitating disposing alignment marks and the like for an exposure machine necessary for separating the semiconductor device on a division line on which a test pad is not formed among a plurality of division lines. .

According to the method of manufacturing a semiconductor device of the present invention, even if the test pads are used as test signal output terminals of a plurality of integrated circuit chips, the plurality of test pads can be integrated without collision of test output signals. A plurality of integrated circuit chips can be shared as test output terminals of circuit chips, and a plurality of semiconductor devices can be manufactured while individually determining a plurality of integrated circuit chips as non-defective or defective.

According to the method of manufacturing a semiconductor device according to the third aspect, the same effect as that of the method of manufacturing a semiconductor device according to the second aspect is exhibited, and a plurality of input / output connection points of the same function are connected to one test pad. Connected, without collision of input / output signals,
Each integrated circuit chip can be tested.

According to the method of manufacturing a semiconductor device of the fourth aspect, the same effects as those of the first aspect are exhibited, and the area per integrated circuit chip is reduced by reducing the amount of wiring occupying the integrated circuit chip. A plurality of semiconductor devices can be manufactured while reducing the number.

According to the semiconductor wafer of the fifth aspect, by providing the test pad on every other division line among the plurality of division lines, another device, for example,
It is possible to easily arrange alignment marks and the like for an exposing machine necessary for separating a semiconductor chip on a division line having no test pad among a plurality of division lines.

According to the semiconductor wafer of the present invention, even if the test pad is used as a test signal output terminal of a plurality of integrated circuit chips, the test pad can be connected to the plurality of integrated circuit chips without collision of test output signals. Can be shared as a test output terminal.

According to the semiconductor wafer of the seventh aspect, in addition to the same effects as those of the sixth aspect, the test input / output signal can be obtained by using the test pad as a test signal input / output terminal of a plurality of integrated circuit chips. The test pads can be shared as test input / output terminals of a plurality of integrated circuit chips without collision.

According to the semiconductor wafer of the eighth aspect, the same effect as that of the fifth aspect is exhibited, and the area of the integrated circuit chip can be reduced by reducing the amount of wiring occupying the integrated circuit chip.

[Brief description of the drawings]

FIG. 1 is a plan view of a part of a semiconductor wafer according to a first embodiment of the present invention.

FIG. 2 is a plan view of a part of a semiconductor wafer according to a second embodiment of the present invention.

FIG. 3 is a plan view of a part of a semiconductor wafer according to a third embodiment of the present invention.

FIG. 4 is a mounting diagram using a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a plan view of a part of a semiconductor wafer showing a first conventional example.

FIG. 6 is a plan view of a part of a semiconductor wafer showing a second conventional example.

FIG. 7 is a plan view of a part of a semiconductor wafer showing a third conventional example.

DESCRIPTION OF SYMBOLS 1, 1a-1l Integrated circuit chip 2 Split line 3 Test circuit 4, 4a-4h Test pad 5 Pad 6a-6l Switching circuit 7a-7l Switching pad 8a-8h Antenna coil pad 9 Sheet coil antenna

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Tatsumi Kado 1006 Kazuma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. F-term (reference) 4M106 AA01 AA08 AC02 AC04 AC08 AD02 AD07 AD23 BA01 CA02 5F038 BE02 CA06 CA13 CD16 DT03 DT04 DT15 EZ20

Claims (8)

[Claims] 1. A semiconductor wafer comprising a plurality of integrated circuit chips and a plurality of division lines formed on a semiconductor wafer, and a test pad connected to a test circuit inside the integrated circuit chip is divided every other of the plurality of division lines. Forming a test pad on a line, connecting the test pad to a test circuit in an integrated circuit chip on both sides of the test pad by shared wiring, and testing the integrated circuit chip using the test pad A method of manufacturing a semiconductor device, comprising: separating the plurality of integrated circuit chips by dividing the semiconductor wafer along the division line. 2. The method according to claim 1, wherein a plurality of integrated circuit chips and a plurality of division lines are formed on a semiconductor wafer, and test pads connected to a test circuit inside the integrated circuit chip are formed on the plurality of division lines. Connecting common pads to test circuits inside an integrated circuit chip on both sides of the test pad, and test pads arranged on the divided circuits and the test circuits inside the plurality of integrated circuit chips Turn on connection with
Forming a switching circuit to be turned off on the shared wiring, and forming a switching pad for inputting a switching signal for switching the switching circuit on the divided line; and using the switching pad to switch the switching circuit. A test signal is input to the test pad and a test circuit in the integrated circuit chip is electrically connected and disconnected to individually test the integrated circuit chips adjacent to the divided line on both sides. And a step of separating the plurality of integrated circuit chips by dividing the semiconductor wafer along the division line. 3. The method according to claim 2, wherein the connection points of the plurality of integrated circuit chips connected to the test pads use the same function input / output connection points. 4. The semiconductor device according to claim 1, wherein said plurality of integrated circuit chips are formed on a semiconductor wafer such that test circuits inside said plurality of integrated circuit chips are arranged line-symmetrically with respect to said division lines. 2. The method for manufacturing a semiconductor device according to claim 1. 5. A semiconductor device comprising: a plurality of integrated circuit chips; and a plurality of division lines for dividing the plurality of integrated circuit chips, wherein a test pad connected to a test circuit inside the integrated circuit chip is provided for each of the plurality of division lines. A semiconductor wafer, which is provided on every other division line, wherein the test pad is connected to a test circuit in an integrated circuit chip on both sides of the test pad by shared wiring. 6. A semiconductor device comprising: a plurality of integrated circuit chips; a dividing line for dividing the plurality of integrated circuit chips; and a test pad connected to a test circuit inside the integrated circuit chip on the dividing line; The test pad is connected to a test circuit in an integrated circuit chip adjacent to the test pad by shared wiring, and connection between the test circuit in the plurality of integrated circuit chips and the test pad is turned on / off. A semiconductor wafer, wherein a switching circuit for causing switching is provided on the shared wiring, and a switching pad for inputting a switching signal for switching the switching circuit is formed on the division line. 7. The semiconductor wafer according to claim 6, wherein connection points of the plurality of integrated circuit chips connected to the test pads are input / output connection points of the same function. 8. A test circuit inside the plurality of integrated circuit chips is arranged line-symmetrically with respect to the plurality of divided lines on which test pads shared with the plurality of integrated circuit chips are arranged. 6. The semiconductor wafer according to claim 5, wherein: