JP2002140874A - Digital information encoding device and digital information decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital information encoding device and a digital information decoder having suitable error ability while effectively utilizing a recording region on a recording medium. SOLUTION: The digital information encoding device is provided with a memory for storing the data block of two-dimensionally arrayed digital data, a CN coder 150 for adding a CN parity for the unit of sub-block comprising the data block, a switch 152 for selectively outputting either digital data read out of the memory or digital data added with the CN parity on the basis of the value of a control signal, CO coder 154 and CI coder 156 for coding and RS product in respect of the data block outputted by the switch 152. The decoder corresponding to this encoding device is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information recording apparatus for recording data on a digital information storage medium such as a magnetic tape, a magnetic disk, an optical disk, a magneto-optical disk, and reproducing the data, and a digital information reproducing apparatus. More particularly, the present invention relates to a digital information encoding device and a digital information decoding device for recording and reproducing data using an error correction code such as a Reed-Solomon code.

[0002]

2. Description of the Related Art In recent years, magnetic disks, optical disks, magneto-optical disks and the like have been used as recording media for computers. Since data used in a computer is less likely to have an error, data recorded on such a recording medium is recorded using an error correction code, and error correction is performed during reproduction using the error correction code.

[0003] In the following, a typical error correcting code RS
(Reed-Solomon) An example of a digital information recording / reproducing apparatus using a product code will be described.

Referring to FIG. 15, a recently popularized DV
1 shows a configuration of an RS product code used in D (Digital Video Disc). As shown in FIG. 15, one data block 350 of the RS product code includes about 32 k (kilo) bytes of user data usable by the user, CI, and CO parity. This one data block is called one cluster. One data block includes 16 sectors (sub-blocks). Each sector has 172 bytes of user data and 1
0 byte CI parity 356. 1 sector is 1
Contains two rows of data. And one data block 3
50 further includes a vertical user data amount 192 (= 16
X 12 rows) 16 bytes of CO parity 3 for bytes
54.

FIG. 16 shows a data block 350 of FIG.
Is calculated and added to the data block 350, stored in a recording medium such as a DVD, and the digital data to which the error correction code is added is read from such a recording medium to perform error correction processing. 1 shows a conventional example of a digital information recording / reproducing apparatus for performing the operation.
Referring to FIG. 16, this digital information recording / reproducing device 37
0 indicates a memory 130 for storing user data as shown in FIG. 15 in a two-dimensional array, a memory interface circuit 132 for inputting / outputting data between the memory 130, and a memory interface circuit 132. An error correction encoder 372 for adding an error correction code (parity) to the output user data, and digital data to which parity is output from the error correction encoder 372 are rearranged to generate a burst error. Interleave circuit 138 for improving the error correction capability
And a recording / reproducing system circuit 140 for recording and reproducing digital data provided from the interleave circuit 138 on a recording medium (not shown) such as a disk or tape by light or magnetism.

The digital information recording / reproducing device 370 further performs a reordering process reverse to the reordering by the interleaving circuit 138 on the data read from the recording medium by the recording / reproducing system circuit 140, thereby returning the data to the original order. A deinterleave circuit 142 for returning the data, and an error correction decoder 374 for performing an error correction process on the digital data output from the deinterleave circuit 142 using the parity added by the error correction encoder 372. including.

The memory 130 is an SDRAM (Static
Random Access Memory) and other high-speed and large-capacity storage devices. The recording / reproducing system circuit 140 processes (modulates) the data in order to make the data easier to detect when recording on a recording medium, and demodulates the data processed in this way when reading. And a modulation / demodulation circuit for outputting digital data.

Referring to FIG. 17, error correction encoder 372
Is a CO encoder 15 for adding an error correction parity CO to each column of a 32 kbyte data block per cluster.
4 and C for adding an error correction parity CI for each row.
And an I encoder 156.

Referring to FIG. 18, error correction decoder 374
Is a CO decoder 166 that performs error correction in the column direction of user data using an error correction parity CO added to each column of a data block of 32 kbytes per cluster.
And a CI decoder 164 that performs error correction of user data in the row direction by using an error correction parity CI added to each row.

FIG. 19 shows the configuration of a sector 380 in this conventional device. Referring to FIG. 19, one sector 38
0 includes 172 bytes of user data 382 and 10 bytes of CI parity 384.

Referring to FIGS. 15 and 19, one data block 3 recorded on the disk by the error correction circuit is shown.
The 50 constituent units are fixed. For example, in a computer recording medium that handles a relatively small amount of data such as a document file, one data block 350 often consists of 512 bytes or 1 kbytes, and in a computer recording medium that handles moving image data such as a DVD, one data block. 350 is often 32 kbytes. In each of the standards, the sizes of the CO parity and the CI parity are fixed, and therefore, the error correction capability is also fixed.

[0012]

However, when the error correction capability is fixed as described above, the following inconvenience occurs. In a document file or the like, high reliability is required so as not to cause inconvenience such as garbled characters. On the other hand, in the case of image data, even if the error cannot be completely corrected, the error can be made inconspicuous by interpolation processing using peripheral pixels or the like. Therefore, image data does not require such high reliability.

Therefore, when the image data and the document file are recorded on the same recording medium using the circuits having the same error correction capability, there are the following problems.

(1) If the error correction capability is adjusted to data requiring high reliability, an extra error correction code (parity) is added even when recording image data or the like which may have low reliability. There is a need. Therefore, the amount of medium and the amount of data processing of the circuit required to record the same user data are unnecessarily increased, and the useless processing must be performed.

(2) When the error correction capability is adjusted to image data or the like which may have low reliability, the amount of parity and the amount of medium required to record the same user data and the amount of data processing of the circuit are small because parity is small. Is less. But,
When recording data that requires high reliability, the correction capability is insufficient, and the reliability of the data itself is reduced.

It is therefore an object of the present invention to provide an error correction encoding device and an error correction decoding device capable of exhibiting an optimum correction capability for user data as required.

[0017]

According to a first aspect of the present invention, there is provided a digital information encoding apparatus comprising a first direction and a first direction.
Storage means for storing a data block of digital data logically two-dimensionally arranged in a second direction intersecting the direction of A sub-block unit error correction code adding unit for adding an error correction code in units, first and second inputs respectively connected to the storage unit and an output of the sub-block unit error correction code adding unit, and a control signal are provided. And selecting either digital data input to the first input or digital data input to the second input based on a value of a control signal applied to the third input. Means for selecting and outputting the data block which is connected to the output of the selection means and which is a logically two-dimensionally arranged digital data output from the selection means. Te, and an error correction code adding means for adding the first and second error correction codes are calculated along the first direction and the second direction.

Preferably, the sub-block unit error correcting code adding means includes means for adding an error correcting code to digital data selected along a direction different from both the first direction and the second direction. Including.

[0019] More preferably, the means for adding an error correction code includes means for adding an error correction code to digital data whose two-dimensional array is selected along a diagonal direction.

[0020] The digital information encoding apparatus may further include means for generating a control signal according to a predetermined condition and providing the control signal to the third input of the selecting means in subblock units.

[0021] More preferably, the sub-block unit error correction code adding means calculates an error correction code for digital data selected along a direction different from both the first direction and the second direction. And an error correction code variance adding means for adding the calculated error correction code distributed to a plurality of locations within the error correction code.

The digital signal includes a synchronization signal having a predetermined length, which is required at the time of signal reproduction, and the error correction code dispersion adding means has a function of setting the interval between the error correction codes distributed and arranged in the sub-block. The error correction code may be arranged so as to have a predetermined relationship with a predetermined length of the synchronization signal.

An error correction code decoding apparatus according to another aspect of the present invention includes a first direction and a second direction intersecting with the first direction.
And a storage unit for storing a data block of digital data which is logically two-dimensionally arranged in the direction of, and to which an error correction code calculated along the first direction and the second direction is added. Each of the data blocks includes a plurality of sub-blocks, and at least a part of the sub-blocks may have an error correction code calculated for each sub-block. The digital information decoding apparatus is further connected to a storage means, and performs sub-block-based error correction means for performing error correction processing in sub-block units using an error correction code added to the sub-block; It has first and second inputs respectively connected to the output of the block unit error correction means, and a third input to which a control signal is applied, and based on a value of the control signal applied to the third input, Selection means for selecting and outputting either the digital data input to the first input or the digital data input to the second input, and logic connected to the output of the selection means and output by the selection means A data block is formed using first and second error correction codes in a first direction and a second direction added to a data block of digital data arranged two-dimensionally. Comprising an error correction means for performing error correction of the click.

Preferably, the sub-block unit error correction means uses an error correction code added to the sub-block for digital data selected along a direction different from both the first direction and the second direction. Means for performing error correction on a sub-block basis. More preferably, the means for performing error correction is provided for digital data in which a two-dimensional array is selected along an oblique direction.
Means for performing error correction using the error correction code added to the sub-block is included.

[0025] More preferably, the digital information decoding apparatus includes means for generating a control signal in accordance with a predetermined condition for each sub-block and providing the control signal to a third input of the selecting means.

The error correction code added to the sub-block may be distributed and arranged at a plurality of positions in the sub-block. Error correction is performed on digital data selected along a direction different from any of the second direction and the second direction by using error correction codes arranged in units of sub-blocks and distributed at a plurality of locations in the sub-block. For error correction by means of a distributed error code.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of a digital information encoding apparatus and a decoding apparatus according to the present invention will be described, but prior to that, a basic technical idea which forms the background of the present invention will be described.

As an example, one data block (RS product code) recorded on the disk is composed of one cluster 3
Consider a case where 2 kbytes are assumed and one subblock (one sector) is further defined by 2 kbytes. In the present invention, when recording user data requiring high reliability, a part of the user data of about 2 kbytes in one sector is replaced with a CN parity which is obliquely scanned as described later. Thereby, the error correction capability is enhanced by performing a double parity check of the CI parity and the CN parity, which are the parities in the row direction.

In order to further improve the reliability, in the present invention, the reliability of user data is increased by increasing the number of CN parities or recording the CN parities dispersedly in the sector. By increasing the number of CN parities or recording the CN parities in a distributed manner, a burst pattern or a synchronous pattern of a predetermined length (91 bytes in this example) required for reproducing data (hereinafter referred to as 91 bytes) is required. Data cannot be read in units called "sinks")
It becomes stronger against so-called sink loss.

According to the present invention, the error correction capability can be enhanced in units of one sector. Therefore, even when recording data such as a document file in which the total amount of user data is less than one sector, it is not necessary to add CN parity to the entire cluster. Therefore, user data is not wasted. Furthermore, a file with a different data length according to the required reliability can be recorded on the disc manually (user) or automatically (microcomputer control). Also, when there are many errors in the system, the error correction capability can be enhanced. Further, since the error correction capability can be enhanced in units of one sector, unnecessary parity need not be added even when a large amount of small data is recorded, and a storage area can be saved. As described above, according to the present invention, various effects can be achieved.

Referring to FIG. 1, an RS product code configuration used by a digital information recording / reproducing apparatus as an example of a digital information encoding apparatus and a decoding apparatus according to an embodiment of the present invention will be described. As shown in FIG. 1, one data block is defined as one cluster (32 kbytes) composed of 16 sectors and one subblock is defined as one sector (2 kbytes). Data amount 17 of user data 100 in the horizontal direction
A 10-byte CI parity 104 is added to 2 bytes, and a 16-byte CO parity 102 is added to 192 (12 × 16) bytes of user data in the vertical direction. The data configuration up to this point is the same as the conventional one shown in FIG.

Further, according to the present invention, as shown in, for example, the sectors No. 2 to No. 4 in FIG.
The number of bytes is reduced, and the CN parity created by scanning the user data in an oblique direction is added as described later.

FIG. 2 shows, as an example, when the horizontal size of user data of one sector is 154 bytes and the vertical size is 12 bytes, the CN parity created by the above-described oblique scanning method is used. A method for adding only 18 bytes × 12 is illustrated. Conventionally, first, a 16-byte CO parity is added to 192 bytes of vertical user data, and then 1 byte is added to 172 bytes of horizontal user data.
0 byte CI parity is added. On the other hand, in the RS product code configuration of the present embodiment, prior to the addition of the CO parity, first, the CN parity created by the oblique scanning method is added as described below. For example, as shown in FIG. 2, for the number 2 to number 4 sectors shown in FIG. 1, for the user data of 154 bytes in the horizontal direction × 12 bytes in the vertical direction, the CN code ( CN calculated by RS (172, 154, 19)
Add parity.

[0034]

(Equation 1)

However, i ', i and j change in the following combinations.

[0036]

[Table 1]

Next, as in the conventional case, the data amount 192 in the vertical direction
A 16-byte CO parity 102 is added to the byte. Finally, a 10-byte CI parity 104 is added to the horizontal data amount of 172 bytes.

As an order, a parity is added in the order of CN → CO → CI parity. However, the order is not limited to this. If CN parity is first, CO parity and C
The coding procedure with I parity may be reversed. CN → C
Even if parity is added in the order of I → CO parity, C
The shaded area where the I and CO parities overlap (the area 10 in FIG. 1)
This is because the contents of 6) are the same.

The CN and C added as described above
As a procedure for performing error correction on user data based on I and CO parity, there are a method of CN → CI → CO parity (or CN → CO → CI parity) and a method of CI → CO → CN parity. (Or CO → CI → C
N parity).

In the above-described first correction method, a burst error or a so-called sync loss in which the sync is out of sync can be corrected first before correcting an error with the CI parity as described later. Also, as in the second method, C
When error correction is performed using N parity at the end, CI,
There is an effect that an error that cannot be completely corrected by the CO parity can be finally corrected.

FIG. 3 shows a configuration of a digital information recording / reproducing apparatus 120 according to one embodiment of the present invention. Here, it is assumed that the encoding procedure is CN → CO → CI parity and the decoding procedure is CN → CI → CO parity.

The digital information recording / reproducing apparatus 120 of the present embodiment shown in FIG. 3 is different from the apparatus 370 shown in FIG. 16 in that the error correction encoders 372 and 374 shown in FIG.
Including an error correction encoder 134 and an error correction decoder 144 capable of performing error correction encoding and decoding using CN parity, and adding CN parity and
It further includes a microcomputer (abbreviated as a microcomputer) 136 for providing a control signal indicating whether or not to perform error correction using N parity to the error correction encoder 134 and the error correction decoder 1444 in sector units. It is a point that is. 3, the same components as those in FIG. 16 are denoted by the same reference numerals and names. Their functions are the same. Therefore, detailed description thereof will not be repeated here.

Referring to FIG. 4, error correction encoder 134
Are a CO encoder 154 for adding an error correction parity CO for each column of a data block (RS product code) of 32 kbytes per cluster, and an error correction parity for each row with respect to the output of the CO encoder 154. For a CI encoder 156 for adding CI and digital data given from the memory interface circuit 132 shown in FIG.
CN encoder 150 for performing processing for adding parity CN for oblique error correction in units of 2 kbytes per sector
A first input for receiving an output of the memory interface circuit 132, a second input for receiving an output of the CN encoder 150, and a control signal terminal for receiving a control signal from the microcomputer 136. It is switched whether to use the CN encoder 150 for selecting either digital data input from the first input or digital data input from the second input and supplying the digital data to the input of the CO encoder 154. And a switch 152 for

Referring to FIG. 5, error correction decoder 144
Is a parity CO for error correction added to each column of a data block (RS product code) of 32 kbytes per cluster.
Thus, a CO decoder 166 for performing error correction in the column direction of user data, and an error correction parity CI added for each row to perform error correction in the row direction of user data and provide the same to the CO decoder 166. And a CN decoder 160 for performing error correction of user data in units of one sector by an error correcting parity CN added diagonally in units of 2 kbytes in one sector.
A first input for receiving digital data supplied from the deinterleave circuit 142, a second input for receiving digital data output from the CN decoder 160, and a control signal for receiving a control signal from the microcomputer 136. And
Using the CN decoder 160 to select either digital data input from the first input or digital data input from the second input and provide the input to the CI decoder 164 according to the control signal And a switch 162 for switching whether or not to do so.

The general operation of the digital information recording / reproducing apparatus 120 having the configuration shown in FIGS. 3 to 5 is as follows. The user data recorded in the memory 130 is sent to the error correction encoder 1 via the memory interface circuit 132.
34. The microcomputer 136 controls the switch 152 in sector units so that the switch 152 selects the second input when the CN code is added, and otherwise, the switch 152 selects the first input. Give control signal. When using the CN parity, the CN encoder 150 adds the CN parity to the input user data and provides the user data to the CO encoder 154. When the CN parity is not used, the user data from the memory interface circuit 132 is directly input to the CO encoder 154.
Given to.

The CO encoder 154 provides an error correcting parity C for each column of a data block of 32 kbytes per cluster.
O is added and given to CI encoder 156. CI encoder 15
6 adds an error correction parity CI to each row and gives the result to an interleave circuit 138.

The interleave circuit 138 interleaves the data block of the user data to which the parity for error correction has been added as described above.
Give to. The recording / reproducing system circuit 140 modulates the given data so as to have a signal form suitable for magnetic or optical recording / reproduction, and records the data on a recording medium (not shown).

At the time of reproduction, the recording / reproducing system circuit 140 reads the recorded information from a recording medium (not shown), performs demodulation corresponding to the modulation performed at the time of recording, and supplies this data to the deinterleave circuit 142. The deinterleave circuit 142 rearranges the data in the reverse order of the interleave performed by the interleave circuit 138 and supplies the rearranged data to the error correction decoder 144.

Referring to FIG. 5, the microcomputer 136 selects the second input when CN parity is added to the reproduced data, and otherwise selects the first input.
Switch 162 in sector units so as to select the input of
Is given. Therefore, for the sector to which the CN parity is added, error correction using the CN parity is performed by the CN decoder 160, and the resultant is provided to the CI decoder 164. For the sector to which the CN parity is not added, the output provided from the deinterleave circuit 142 is provided to the CI decoder 164 as it is.

The CI decoder 164 performs error correction in the row direction of the user data using the error correction parity CI added for each row, and provides the result to the CO decoder 166. CO
The decoder 166 performs error correction in the column direction of the user data using the error correction parity CO added for each column of the data block, and supplies the result to the memory interface circuit 132.

The memory interface circuit 132 outputs the error-corrected user data memory 130
Write to.

The operation of error correction encoder 134 and error correction decoder 144 shown in FIGS. 4 and 5 will be described below with reference to the flowcharts shown in FIGS.

First, the error correction encoder 13 at the time of recording
4 and the operation of the microcomputer 136 will be described. In the following description, it is assumed that CN parity is added to all sectors in one data block (one cluster) (= 16 sectors, 32 kbytes). C for each sector
A person skilled in the art can easily realize a method of selecting whether or not to add N parity.

Although not particularly shown in FIGS. 3 and 16 for simplicity, the memory interface circuit 132 includes an interleave circuit 138, a deinterleave circuit 142, a CO encoder 154, a CI decoder 164,
It is also connected to the CN decoder 160, and the output of each circuit is once written into the memory 130 and then applied to the input of the next circuit.

Referring to FIG. 6, first, a determination is made as to whether or not data to be recorded is data such as a document file which requires high reliability (17).
0). This determination may be made according to the specification by the user, or may be made by automatically determining the type of data. If high reliability is not required, user data consisting of a two-dimensional array of 192 rows × 172 columns is recorded in the memory 130, and the process proceeds to step 176. In the case of data requiring high reliability, the user data (192 rows × 154 columns) is stored in the memory 130, and the CN parity is calculated and added (17).
2). Details of the CN parity processing will be described later with reference to FIG.

For the user data to which the CN parity is added in step 172 or the data stored in the memory 130 in step 174, the CO parity and C
An I parity addition process and a recording process on a recording medium (not shown) are performed (176). The contents of this processing are shown in FIG.
6 is the same as that of the conventional digital information recording / reproducing apparatus described with reference to FIG. Therefore, the details thereof will not be repeated here.

Referring to FIG. 7, the details of the CN parity adding process performed in step 172 of FIG. 6 will be described. First, the sector number to which the CN parity is added is stored in the memory as management information (180). Subsequently, user data (line 1 to line 192, column 1 to line 1) instructed from another circuit (for example, a file management microcomputer) not shown.
(54 columns) is stored in the memory 130 (182). Subsequently, the variable A is set to the initial value 0 (18
4). The following is the repetition processing for A = 0 to 15.

Subsequently, a variable L = 12 × A + 1 is calculated.
Further, according to the formula (1), as shown in FIG. 2, the calculation of the CN parity of 18 bytes is performed 12 times on the data of 154 bytes in total with 12 rows × 12 columns as one unit in the oblique direction. (188). The calculated CN parity is stored in the memory 130 at the positions of 155th column to 172th column and Lth row to L + 12th row via the memory interface circuit 132. Subsequently, it is determined whether or not A = 15, and if A = 15, the CN parity processing ends, and
If not = 1, 1 is added to A (194), and the process returns to step 188.

In this way, the CN parity is calculated for all the sectors. Referring to FIG. 8, C in FIG.
The processing of adding the O parity and the CI parity is performed as follows. First, 1 is set to a variable N as an initial value (200). Subsequently, of the data in the 1st to 172th columns and the 1st to 192th rows including the user data and the CN parity, the data of one column (192 bytes) corresponding to the Nth is transmitted via the memory interface circuit 132. The data is read from the memory 130 and the CO parity is calculated as specified in the DVD standard (202). The CO parity calculated in this way is written into the position of the 193rd to 208th rows in the Nth column of the memory 130 via the memory interface circuit 132 (206). Then N is 1
It is determined whether it is 72 or not (208). If N is not 172, 1 is added to N (204), and the control is performed again at step 20.
Return to 2. If N is 172, the control proceeds to the next step 21.
Go to 0.

Subsequently, the initial value 1 is substituted for the variable M (210). The data of the Mth one row (for 172 bytes) of the data of the first column to the 172th column and the first row to the 192th row of the memory 130 is read out from the memory 130 via the memory interface circuit 132 and is defined by the DVD standard. The CI parity is calculated as if (21)
2). The CI parity calculated in this manner is stored in the M row of the memory 130 in columns 173 to 182 via the memory interface circuit 132 (21).
4). Subsequently, it is determined whether or not the value of the variable M is 208 (216). If the value is not 208, 1 is added to M (222), and the control returns to step 212. M is 2
If 08, control proceeds to step 218.

Subsequently, while reading data from the memory 130 through the memory interface circuit 132 in units of one row (182 bytes), one row of CO parity is inserted (interleaved) every 12 rows (218). ). Recording is performed on a recording medium (not shown) via the recording / reproducing system circuit 140 while adding a synchronization signal in units of 91 bytes, which is half of one line of data (182 bytes) (220).
When all data has been recorded, this process ends. In addition,
Information on which sector the CN parity is added to is recorded as separate management information in another area of a recording medium (not shown).

The operation of the digital information recording / reproducing apparatus 120 at the time of reproducing the digital information thus recorded will be described. Referring to FIG. 9, first, management information is read from a recording medium via recording / reproducing system circuit 140 (23).
0). According to the read management information, it is determined whether or not the sector to be processed is a sector to which CN parity is added (232). If the CN parity has not been added, the control proceeds to step 236. In the case of a sector to which CN parity is added, step 234 described below is used.
Is performed.

The error correction of the sector using the CN parity performed in step 234 will be described with reference to FIG. When the CN parity processing ends, the control proceeds to step 236.

In step 236, error correction processing using CI parity and error correction processing using CO parity are performed. As a result, the error-corrected user data is written into the memory 130. Subsequently, in step 238, a process of transferring the user data stored in the memory 130 to another circuit (for example, a file management microcomputer) is performed, and the reproduction operation ends.

The CN parity processing performed in step 234 of FIG. 9 will be described with reference to FIG. First, at step 240, data recorded on a recording medium (not shown) in units of 91 bytes, which is half of one line of data (182 bytes), is reproduced via the recording / reproducing system circuit 140 while deleting the synchronization signal. , A process to be stored in the memory 130 is performed. Subsequently, while reading data from the memory 130 via the memory interface circuit 132 in units of one row (182 bytes), the process of returning the CO parity added to one row every 12 rows to the original position (deinterleaving) is performed. Perform (242). The user data and the parity (1) thus deinterleaved
Row to 208 rows, 1 column to 182 columns)
Is performed (244).

Subsequently, an initial value 0 is set to the variable A (24).
6). The variable L = 12 × A + 1 is calculated (248).

Further, the user data of the data read from the memory 130 in accordance with the equation (1) is scanned diagonally as indicated by arrows 110 and 112 in FIG. 2 to obtain a total of 154 bytes in units of 12 rows and 12 columns. The process of performing error correction with CN parity added to data by 18 bytes is repeated 12 times. The result is 12 × 15
Error correction is performed on 4 = 1848 bytes of user data (252). The data on which the error correction using the CN parity is completed is stored in the memory 130 at the positions of the 1st to 154th columns and the Lth to L + 12th rows via the memory interface circuit 132 (25).
4). Subsequently, it is determined whether or not the value of the variable A is 15, and if it is not 15, the process of adding 1 to A (250) is performed, and the control returns to step 248. If A = 15, this process ends.

Thus, step A 248 from A = 0 to 15
By repeating the processing of ~ 256, the error correction processing using CN parity is completed for all sectors.

Referring to FIG. 11, CI and CO shown in FIG.
The details of the parity decoding process will be described. First, the variable M
Is set to the initial value 1 (260). Subsequently, the memory 130
Of the data of the 1st column to 182 columns and the data of the 1st row to 208 stored in the M-th row (182 bytes), and performs an error correction process using CI parity (264). This error correction processing is performed according to a conventionally used method.

The data after the error correction using the CI parity is stored in the memory 130 at the position of M row, column 1 to column 172 via the memory interface circuit 132 (2
66). Subsequently, it is determined whether the value of M is 208 (26).
8). If M is not 208, 1 is added to M (26
2), control returns to step 264. If M is equal to 208, control proceeds to step 270.

In step 270, an initial value of 1 is set to a variable N (270). Subsequently, of the data in columns 1 to 182 and rows 1 to 208 of the memory 130, the data for the Nth column (208 bytes) is read out via the memory interface circuit 132, and error correction using CO parity is performed. Is performed (270). The data after the error correction is stored in the memory 130 at the position of N column, 1st row to 192th row via the memory interface circuit 132 (27).
6). The error correction processing using the CO parity can use the method conventionally performed as it is.

Subsequently, it is determined whether or not the value of N is equal to 182 (278).
Is added (272), and the control returns to step 274. If the value of N is equal to 182, processing for transferring the user data stored in the memory 130 to another circuit (not shown) (for example, a file management microcomputer) is performed (280). When the transfer is completed, this process is completed.

In the above description of the operation, a case has been described in which CN parity is added to all sectors. However, as described above, by appropriately changing the value of the control signal output from the microcomputer 136 for each sector, a process of adding CN parity to only a desired sector is performed, and CN parity is added to other sectors. Needless to say, it can be encoded.

As described above, according to the present invention, error correction processing using CN parity is performed for data requiring high reliability, and CN is performed when high reliability is not required.
An encoding process without adding a parity can be performed. Therefore, error correction can be performed with an appropriate amount of calculation and an appropriate level of error correction capability in accordance with the nature of the data. Since a CN parity can be added for each sector, even data with a small data amount, such as document data, can be recorded with high reliability by efficiently using the area of the storage medium.

In the apparatus according to the above-described embodiment, the magnitude of the CN parity is fixed, and is stored in a predetermined location. However, the present invention is not limited to such an embodiment. As in the case of the first embodiment, by increasing the CN parity and / or dispersing the recording location of the CN parity while obtaining the diagonal CN parity in each sector first for each sector, burst errors and synchronization can be prevented. It is possible to perform an error correction process that is strong against omission.

FIG. 12 shows the configuration of sector 290 in the first embodiment described above. The sector 290 has 154 bytes of user data 292 and 18 bytes.
It includes a byte CN parity 294 and a 10 byte CI parity 296. In order to further enhance the reliability of the user data as compared with the method shown in FIG. 12, the following method can be considered.

(A) The size of the CN parity 294 is set to 1
Increase from 8 bytes to, for example, 32 bytes. By doing so, the error correction capability of the user data is enhanced,
In the case of the example described here, the error correction capability is improved from 9 bytes at the maximum to 16 bytes.

(B) The CN parity of the user data is set to 1
After being increased from 8 bytes to 32 bytes, the data is distributed to two places 304 and 308 in the sector 300 as shown in FIG. With reference to FIG.
First user data 302 consisting of bytes, first CN parity 304 consisting of 16 bytes, second user data 306 consisting of 70 bytes, second CN parity 308 consisting of 16 bytes, and 10 bytes Become C
I parity 310. With such a configuration, it is possible to perform error correction that is strong against burst errors and loss of sync. For example, even if 91 bytes, which is one sync in this example, cannot be reproduced from the storage medium, the error location is 7 in the horizontal direction as shown by the circle in FIG.
It only crosses the calculation path of the CN parity in several places. Therefore, if only one sync is missing, all errors can be corrected using CN parity. For the same reason, it becomes stronger against burst errors.

(C) Further, as shown in FIG.
Parities can be recorded in two places on the recording medium in a distributed manner. In the example shown in FIG.
Is first user data 322 consisting of 70 bytes,
A first CN parity 324 of 16 bytes, a first CI parity 326 of 5 bytes, a second user data 328 of 70 bytes, a second CN parity 330 of 16 bytes, and 5 bytes And a second CI parity 332 comprising

By adopting the configuration shown in FIG. 14, even if the CI parity becomes partially useless due to loss of sync or the like, erasure correction can be performed. Therefore, the data structure is more resistant to the loss of sync than that described above. When the CI parity is recorded on the recording medium, the format shown in FIG. 14 is used. However, it is necessary to return to the configuration shown in FIG. 13 until the CI parity is stored in the memory 130 and the preparation for error correction is completed. .

As described above, according to the embodiment of the present invention, by adding an error correction code of an oblique scanning method different from CI parity and CO parity to each sector, data requiring high reliability can be obtained. The data can be recorded by efficiently using the data on the area of the recording medium in a mixed manner. In the above embodiment, since the oblique scanning method is used as the CN parity, it is resistant to missing syncs and burst errors. C of diagonal scanning type error correction circuit
If the number of N parities is the same as the CI or CO parity, the circuit can be used in common. Therefore, the error correction capability can be enhanced only by adding a simple circuit such as a switch.

In the above configuration, it is possible to select whether or not to add CN parity to each sector by operating a control signal for the switch. Therefore, even when the user wants to increase the reliability of moving image and audio data in addition to the document data, it is possible to perform processing for enhancing the error correction capability. Further, even for a device or a recording medium having a high error rate, it is possible to perform a process for increasing the error correction capability.

In the apparatus of the embodiment described above, an optical disk is assumed as a digital information storage medium. However, other types of disk-like recording media, such as a portable hard disk, a flexible disk, and a magneto-optical disk, are used. The present invention can also be applied to such cases. Furthermore, even in the case of a magnetic tape or the like which is not a disk-shaped recording medium,
The present invention can be applied as long as data is recorded digitally.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[Brief description of the drawings]

FIG. 1 is a diagram showing a data block configuration according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a method of adding CN parity.

FIG. 3 is a block diagram showing a configuration of a digital information recording / reproducing apparatus according to one embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of an error correction encoder in the device according to the embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of an error correction decoder of the device according to one embodiment of the present invention.

FIG. 6 is a flowchart showing an operation flow when user data is recorded in the digital information recording / reproducing apparatus according to one embodiment of the present invention.

FIG. 7 is a flowchart of a CN parity addition process.

FIG. 8 is a flowchart of CO, CI parity addition processing according to an embodiment of the present invention.

FIG. 9 is a flowchart showing an operation flow when reproducing user data in the digital information recording / reproducing apparatus according to one embodiment of the present invention.

FIG. 10 is a flowchart of a CN parity error correction process.

FIG. 11 is a flowchart of a CI and CO parity error correction process.

FIG. 12 is a diagram showing a configuration of a sector in one embodiment of the present invention.

FIG. 13 is a diagram showing a sector configuration according to another embodiment of the present invention.

FIG. 14 is a diagram showing a sector configuration according to still another embodiment of the present invention.

FIG. 15 is a diagram showing a configuration of a data block in a conventional digital information recording / reproducing device.

FIG. 16 is a block diagram showing a configuration of a conventional digital information recording / reproducing device.

FIG. 17 is a block diagram showing a configuration of an error correction encoder of a conventional digital information recording / reproducing device.

FIG. 18 is a block diagram showing a configuration of an error correction decoder of a conventional digital information recording / reproducing device.

FIG. 19 is a diagram showing a data configuration of a sector in a conventional digital information recording / reproducing apparatus.

[Explanation of symbols]

100 CN parity, 102 CO parity, 104
CI parity, 120 digital information recording / reproducing device,
130 memory, 132 memory interface circuit,
134 error correction encoder, 136 microcomputer, 138
Interleave circuit, 140 Recording / reproduction system circuit, 142
Deinterleave circuit, 144 error correction decoder, 150
CN encoder, 152 switch, 154 CO encoder, 156CI encoder, 160 CN decoder, 162
Switch, 164 CI decoder, 166 CO decoder.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) G11B 20/18 542 G11B 20/18 542C 570 570G 20/10 20/10 H H03M 13/05 H03M 13/05 13/27 13/27 F term (reference) 5D044 AB05 AB07 BC02 CC06 DE61 DE69 DE83 DE86 EF05 FG18 GK12 5J065 AA03 AA06 AB03 AB04 AB05 AC03 AC04 AD02 AE06 AF02 AG06 AH01 AH06 AH07 AH09

Claims (11)

[Claims] 1. A storage unit for storing data blocks of digital data logically two-dimensionally arranged in a first direction and a second direction intersecting the first direction, and connected to the storage unit. A sub-block unit for adding an error correction code to each of the sub-blocks constituting the data block, and a sub-block unit for adding an error correction code; and a storage unit and an output of the sub-block unit error correction code adding unit. And a third input to which a control signal is applied, and a digital input to the first input based on a value of the control signal applied to the third input. Selecting means for selecting and outputting either data or digital data input to the second input; connected to an output of the selecting means; Adding first and second error correction codes calculated along the first direction and the second direction to the logically two-dimensionally arranged digital data block to be output; Error correction code adding means,
Digital information encoding device. 2. The sub-block unit error correction code adding means for adding an error correction code to digital data selected along a direction different from both the first direction and the second direction. 2. The method of claim 1, comprising means.
A digital information encoding device according to claim 1. 3. The means for adding the error correction code includes means for adding an error correction code to digital data selected in the diagonal direction in the two-dimensional array. A digital information encoding device according to claim 1. 4. The apparatus according to claim 1, further comprising: means for generating said control signal in accordance with a predetermined condition in units of sub-blocks and applying said control signal to said third input of said selecting means. A digital information encoding device according to claim 1. 5. The sub-block unit error correction code adding means calculates an error correction code for digital data selected along a direction different from both the first direction and the second direction. 2. The digital information encoding apparatus according to claim 1, further comprising an error correction code variance adding unit for adding the calculated error correction code distributed to a plurality of locations in the sub-block. 6. The digital signal includes a synchronization signal of a predetermined length, which is required at the time of signal reproduction, and the error correction code variance adding means is configured to disperse the error correction code arranged in a sub-block. 6. The digital information encoding apparatus according to claim 5, wherein the error correction code is arranged such that an interval between the error correction codes has a predetermined relationship with the predetermined length of the synchronization signal. 7. An error correction logically arranged two-dimensionally in a first direction and a second direction intersecting the first direction and calculated along the first direction and the second direction. Storage means for storing a data block of digital data to which a sign is added, each of the data blocks includes a plurality of sub-blocks, and at least a part of the sub-blocks is calculated in sub-block units An error correction code may be added, connected to the storage means, and a sub-block unit error correction means for performing error correction processing in sub-block units using the error correction code added to the sub-block; First and second inputs respectively connected to the output of the storage means and the sub-block unit error correction means;
A third input to which a control signal is applied, and a digital data input to the first input or a digital data input to the second input based on a value of the control signal applied to the third input. Selecting means for selecting and outputting any one of the digital data to be output, and being connected to the output of the selecting means, and being added to a data block of the logically two-dimensionally arranged digital data output from the selecting means. An error correction unit for performing error correction of the data block using the first and second error correction codes in the first direction and the second direction. 8. The sub-block unit error correction means,
And performing error correction in units of sub-blocks on digital data selected along a direction different from any of the first direction and the second direction using the error correction code added to the sub-block. The digital information decoding device according to claim 7, comprising means. 9. The method according to claim 1, wherein the means for performing the error correction is a sub-block using the error correction code added to the sub-block with respect to the digital data having the two-dimensional array selected along a diagonal direction. 9. The digital information decoding apparatus according to claim 8, further comprising means for performing error correction in units. 10. The apparatus according to claim 7, further comprising: means for generating said control signal in accordance with a predetermined condition in units of sub-blocks and applying said control signal to said third input of said selecting means. 2. The digital information decoding device according to item 1. 11. The error correction code added to the sub-block is scattered and arranged at a plurality of positions in the sub-block, and the sub-block unit error correction means is configured to execute the first direction and the For digital data selected along a direction different from any of the second directions,
The digital information according to claim 7, further comprising: an error correction unit using a distributed error code for performing error correction using the error correction code arranged in a unit of the sub-block and distributed in a plurality of locations in the sub-block. Decryption device.