JP2002134925A - Multilayer circuit board and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer circuit board which is excellent in low dielectric characteristic with small dielectric loss and has sufficient mechanical strength. SOLUTION: In this multilayer circuit board, insulator layers 3, alloy foils 2 for holding the insulator layers 3 and a plurality of circuit wirings 4 are installed, and the respective layers of the circuit wiring 4 are electrically connected at prescribed positions by using electric continuous paths 5 which penetrate the insulator layers 3 and the alloy foils 2. The insulator layers 3 are composed of porous thermal resistance material.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multilayer circuit board and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, various electronic devices including communication devices have been miniaturized and improved in performance. ing. On the other hand, the porous film contains many vacancies, and thus has better low dielectric properties and low dielectric loss than conventional resins. By adopting this as the insulating layer, there is an advantage that the impedance control of a fine circuit for a high frequency application can be easily performed, and the degree of freedom in circuit design can be obtained.

[0003] Further, due to the necessity of high-density mounting, it is required that an unpackaged semiconductor (bare chip) is directly mounted on a circuit board. In this bare chip mounting, ensuring the dimensional accuracy of the circuit board has become increasingly important from the viewpoint of terminal alignment. further,
In order to obtain reliability after mounting, attempts have been made to suppress thermal stress in the mounting process caused by the difference between the silicon material of the bare chip and the thermal expansion coefficient of the circuit board.

[0004]

However, a porous film having a porosity of 30% or more is excellent in low dielectric properties, but lacks mechanical strength by itself, so that it cannot support a circuit wiring layer. , It is difficult to obtain dimensional accuracy. In addition, even if the porous membrane is filled with fibers or the like, or a cloth such as glass fiber is buried and reinforced, the mechanical strength is not sufficient. The properties are impaired. On the other hand, in order to exhibit low dielectric properties, if the filling amount is reduced or the basis porosity of the cloth is increased, the supporting effect becomes insufficient.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a multilayer circuit board having excellent low dielectric properties and low dielectric loss and having sufficient mechanical strength, and a method of manufacturing the same. And

[0006]

In order to achieve the above object, the present invention comprises an insulator layer, a support layer for holding the insulator layer, and a plurality of circuit wiring layers. A multilayer circuit board in which each layer of a circuit wiring layer is electrically connected at a predetermined position using an electrical conduction path penetrating the layer and the support layer, wherein the insulator layer is formed of a porous heat-resistant material. The multi-layer circuit board described above has a first gist, and a conductor layer is laminated on both sides of a support layer holding the insulator layer via an insulator layer made of a porous heat-resistant material. Forming a laminate of the first laminate, forming an electrical conduction path through the insulator layer and the support layer of the first laminate,
Forming circuit wiring on the conductor layers on both sides of the laminated board to produce a double-sided circuit board, and forming an insulator layer made of a porous heat-resistant material on the circuit wiring layers on both sides of the double-sided circuit board. A step of forming at least a conductive layer to form a second laminate by laminating the conductive layer; a step of forming a conductive path extending from the front conductive layer to the rear conductive layer in the second laminate; Forming a circuit wiring on the conductor layers on both surfaces of the second laminated board.
Forming a first laminate by laminating conductor layers on both sides of a support layer holding the insulator layer via an insulator layer formed of a porous heat-resistant material; Forming an electrical conduction path penetrating the insulator layer and the support layer of the laminate, and forming a circuit wiring on both conductor layers of the first laminate to form a double-sided circuit board; A step of preparing two or more double-sided circuit boards, aligning the two or more double-sided circuit boards, and laminating via predetermined layers of an adhesive insulating resin layer in which conductive paths in the thickness direction are formed; And a step of electrically connecting the circuit wiring layers of the two double-sided circuit boards sandwiching the adhesive insulating resin layer by the conductive path.

That is, the multilayer circuit board of the present invention comprises an insulator layer made of a porous heat-resistant material, a support layer for holding the insulator layer, and a plurality of circuit wiring layers. I have. As described above, the multilayer circuit board of the present invention supports the porous insulator layer having insufficient mechanical strength by the support layer, and thus has excellent low dielectric properties and low dielectric loss. Has sufficient mechanical strength.

Further, when a material having a high elastic modulus is used as a material constituting the support layer, the mechanical strength of the entire laminated structure can be greatly improved. In addition, when a low thermal expansion material is used, the difference in thermal expansion from silicon can be reduced, so that the occurrence of thermal stress can be suppressed.
Therefore, by laminating the support layer having a high elastic modulus and low thermal expansion with the porous insulator layer, dimensional stability can be obtained, and the positional dimensional accuracy of the circuit wiring is improved. Positioning between circuit wiring layers and during chip mounting becomes easy. In particular, when a metal foil having a low thermal expansion is used, it has excellent rigidity and is hard to crack even when bent. In addition, it bears the pressure at the time of mounting at the time of bare chip mounting, has a high effect of suppressing thermal stress due to a difference in thermal expansion, and has good reliability.

On the other hand, according to the method for manufacturing a multilayer circuit board of the present invention, a multilayer circuit board exhibiting the above-described excellent effects can be manufactured.

Next, the present invention will be described in detail.

The present invention comprises an insulator layer made of a porous heat-resistant material, a support layer, and a circuit wiring layer.

As the insulating resin constituting the insulator layer, polyimide-based, polyamide-based, polyester-based, polyetherimide-based, epoxy-based, silicone-based, or a mixture of these materials is preferred in view of heat resistance, electrical characteristics, and the like. Although used, it is preferable to use a polyimide or polyamide resin which has heat resistance and high mechanical strength among resins. These insulating resins include those containing a fluorine-based resin (for example, polytetrafluoroethylene [PTFE], polychlorotrifluoroethylene [PCTFE], tetrafluoroethylene-perfluoroalkylvinyl ether copolymer [PFA], Tetrafluoroethylene-hexafluoropropylene copolymer [FEP]) may be used.

[0013] The polyimide resin may contain another copolymer component or a blend component as long as it is mainly composed of a repeating unit in which an acid residue and an amino residue are imide-bonded. Preferably, in terms of heat resistance and mechanical strength,
A polyimide having an aromatic group in the main chain can be given. In particular, 0.55 to 3.00, preferably 0.60
It is desirable that the polymer has an intrinsic viscosity of ~ 0.85 (measured value at 30 ° C). Those having an intrinsic viscosity in the above range have good solubility in a solvent and high mechanical strength when the porous insulator layer is formed by a wet coagulation method.

The polyimide resin is obtained by using, for example, an acid component and a diamine component. Examples of the acid component include tetracarboxylic dianhydride. Specific examples of the above tetracarboxylic dianhydride include pyromellitic dianhydride, 3,3 ', 4,4'-biphenyltetracarboxylic dianhydride, 2,2'-bis (3,4- (Dicarboxyphenyl) propane dianhydride, butanetetracarboxylic dianhydride and the like. Butanetetracarboxylic acid, even if it is not an anhydride, can form an imide ring by a heat reaction with a diamine.

On the other hand, examples of the above diamine component include:
4,4'-diaminodiphenyl ether (DDE),
4,4'-diaminodiphenylmethane, 4,4'-diaminophenylsulfone, 2,2'-bis-4- (4-aminophenoxy) phenylpropane, paraphenylenediamine and the like.

As the polyimide resin, the polymer or its precursor (polyamic acid) can be used, but since polyamic acid has higher solubility than polyimide, there is an advantage that there is little restriction on the molecular structure. There is. The polymer is preferably completely imidized, but may be one having an imidation ratio of 70% or more.

As the acid component and the amine component constituting the polyamide resin, for example, the following can be used.

Specific examples of the dicarboxylic acid as the acid component include phthalic acid, isophthalic acid, terephthalic acid,
Chloroterephthalic acid, naphthalenedicarboxylic acid and the like can be mentioned.

On the other hand, examples of the amine component include 4,
4'-diaminodiphenyl ether (DDE), 4,
Examples include 4'-diaminodiphenylmethane, 4,4'-diaminophenylsulfone, 2,2'-bis-4- (4-aminophenoxy) phenylpropane, paraphenylenediamine and the like.

The formation of the porous insulating resin layer includes various film forming methods such as a wet coagulation method, a dry coagulation method, and a stretching method.
In the wet coagulation method, in general, a film-forming stock solution (dope) in which a resin, an additive, and the like are dissolved in a solvent is prepared, and the solution is applied to a substrate (cast) and immersed in a coagulation solution to replace the solvent. Thus, the resin is coagulated (gelled), and thereafter, the coagulation liquid or the like is dried and removed to obtain a porous resin layer. Or, by adding a dispersible compound to the dope and stripping it by heating or extracting it with a specific solvent,
It can be made porous.

The dope is preferably -20 to 40.
It is applied in a temperature range of ° C. The coagulation liquid is not limited as long as it does not dissolve the resin and is compatible with the solvent, but water, alcohols such as methanol, ethanol, isopropyl alcohol and the like, and a mixture thereof are used. In particular, water is preferably used.
The temperature of the coagulating liquid during immersion is not particularly limited, but is preferably a temperature of 0 to 50 ° C.

The polymer concentration of the dope is preferably in the range of 5% by weight to 25% by weight, more preferably 7% by weight to 20% by weight. If the concentration is too high, the viscosity becomes too high and handling becomes difficult. If the concentration is too low, a porous insulating resin layer cannot be formed.

The solvent for dissolving the polyimide resin or the polyamic acid resin as a precursor thereof is not particularly limited as long as it dissolves. From the viewpoint of solubility, for example, N-methyl-2-pyrrolidone, N, N'-dimethylacetamide, N, N'-dimethylformamide, dimethylsulfoxide and the like can be mentioned.

An inorganic substance such as lithium nitrate and an organic substance such as polyvinylpyrrolidone can be added for controlling the pore shape and pore diameter. The concentration of the additive is preferably from 1% by weight to 10% by weight in the solution. When lithium nitrate is added, the replacement speed between the solvent and the coagulating liquid is high, and a finger void structure (a structure having finger-like voids) can be formed in the sponge structure. By adding an additive such as polyvinylpyrrolidone which slows down the coagulation speed, a porous film having a sponge structure uniformly spread can be obtained.

The above-mentioned dope is applied to a certain thickness and immersed in a coagulating liquid such as water to coagulate, or left in a steam atmosphere to coagulate, and then immersed in water.
The porous layer is desolvated. After the formation of the porous layer, it is taken out of the coagulating liquid and dried. The drying temperature is not particularly limited, but drying at 200 ° C. or lower is desirable.

When a precursor (polyamic acid) is used as the polyimide resin in the porous resin layer, 20
A heat treatment is performed at 0 to 500 ° C., and the precursor (polyamic acid) is heated and closed to form a polyimide.

In the case of a polyamide resin, a material obtained by dissolving a polyamide resin in a polar solvent is applied to a non-porous substrate such as a glass plate to a certain thickness, and then immersed in water for coagulation or steam. After leaving to coagulate in an atmosphere, it is immersed in water or the like to obtain a solvent-free porous film. As the non-porous base material, in addition to inorganic substances such as a glass plate and a stainless steel plate, a polymer film such as a polyethylene sheet can be used.

In the case of using a dispersible compound and extracting it with a solvent, those which are not completely compatible with the polyimide resin or polyamide resin are preferable, and those which can be extracted with a specific solvent are preferable. As such a compound, an oligomer having a relatively low polymerization degree in which two or more identical or different monomers are polymerized is exemplified. For example, polyacrylate oligomer, polyether oligomer, polyester oligomer, polyurethane oligomer and the like can be mentioned.

The extraction solvent may be a commonly used organic solvent, and may be appropriately selected depending on the composition of the polyamic acid resin and the type of the dispersing compound. Examples of such organic solvents include amide polar solvents such as N-methyl-2-pyrrolidone, alcohol solvents such as methanol, ether solvents such as tetrahydrofuran, ketone solvents such as cyclohexanone, and aromatic solvents such as toluene. Examples include hydrocarbon solvents.

In the extraction method, it is particularly preferable to use liquefied carbon dioxide or carbon dioxide in a high-temperature, high-pressure or supercritical state. When such carbon dioxide is used, for example, 0 to 1 in a pressure vessel.
At 50 ° C, further at 20-120 ° C, 3.5-100
It is preferable to perform extraction at a pressure of 6 MPa to 50 MPa.

The thickness of the porous resin layer is usually 0.1 to 2
It is about 00 μm, preferably 10 to 50 μm.

The pore size of the porous resin layer is determined by taking a photograph of the resin layer using a scanning electron microscope (SEM) and analyzing the photograph with a computer.

The porosity of the porous resin layer is determined by measuring the volume and weight of the insulating layer, and using the density of the material of the insulating layer.
It is determined by the following equation (1).

[0034]

(Equation 1)

When the pores on the surface or inside are too small, the low dielectric effect is small, and when too large, there is a problem in strength. For this reason, it is preferable that both the front and back surfaces have a hole diameter of 0.05 μm or more. More preferably, it is 0.1 to 5 μm. The pore size of the sponge structure portion (inside) is 0.05 μm.
To 10 μm, but preferably 1 μm to 7 μm. In the finger void structure, a diameter of 0.
The thickness is preferably from 05 μm to 10 μm, but the length is about the film thickness when the length is the longest. About porosity, 30%
Although it is set to be less than 98% in the above, preferably 5%
0% or more and less than 95%. If the porosity is less than 30%,
A low dielectric effect is hardly obtained, and if it is 98% or more, even if laminated with a support layer, the mechanical strength of the insulator layer is insufficient, and the circuit wiring layer cannot be supported.

As a method of forming a through hole for forming an electric conduction path in the insulator layer, an appropriate method may be used depending on the hole diameter, and examples thereof include a drill, a punch, and a laser.

Alternatively, holes may be formed by imparting photosensitivity to the insulator layer, and exposing and developing the same. In this case, a photosensitive agent is added to the dope to impart photosensitivity.

As the photosensitive agent, any one can be used as long as it can provide a solubility contrast between an exposed portion and an unexposed portion when the cast and dried resin is exposed. Examples thereof include dihydropyridine derivatives, diazonaphthoquinonesulfonic acid ester derivatives, and aromatic diazide compounds.

Such a photosensitizing agent is usually used with respect to 1 mole part of a polyimide resin or a polyamide resin.
It is used in the range of 0.05 to 0.5 mol part. If necessary, imidazole may be blended as a solubilizing agent for the developer. In such a case, the imidazole is usually added to 1 mol part of the polyimide-based resin or the polyamide-based resin. It is used in the range of 0.05 to 0.5 mol part.

After exposing the hole pattern to the cast and dried resin, a positive or negative latent image is formed by heating at 100 to 220 ° C., if necessary.
A predetermined hole is formed by dipping in a developer or spraying the developer. The above heating temperature is 10
When the temperature is lower than 0 ° C., formation of a latent image is insufficient, and a contrast of solubility in a developing solution cannot be obtained. At 220 ° C. or higher, a desired porous insulating resin layer cannot be formed due to deterioration and decomposition of the photosensitive agent.

Examples of the developer include an aqueous solution of an organic alkali such as tetramethylammonium hydroxide and an aqueous solution of an inorganic alkali such as sodium hydroxide and potassium hydroxide. The alkali concentration is usually 2 to 5% by weight. If necessary, a lower aliphatic alcohol such as methanol, ethanol, N-propanol, or isopropyl alcohol may be added to the aqueous alkali solution. The addition amount of the alcohol is usually 50% by weight or less.

Examples of the material constituting the support layer include engineering plastics having low thermal expansion (polyimide, polyamide, polyester, polyetherimide, epoxy, silicone, or a mixture thereof), high-density fiber cloth. (Inorganic fiber such as glass, resin fiber such as aramid, carbon fiber), ceramic material, and metal foil are laminated with a porous insulating layer.

In particular, it is preferable to use a metal foil having uniform thermal expansion in the plane direction and the thickness direction and having a high elastic modulus. As metal foil, Fe, Ni, Cr, Cu, Al,
There are Ti, Co, Pt or alloy foils containing these,
In order to suppress the difference in thermal expansion coefficient between the chip and the substrate, it is particularly preferable to use one having a low thermal expansion coefficient (20 ppm / ° C. or less at 20 to 250 ° C.). These metal foils can be used alone or in a laminate.

In the case of an Fe / Ni-based alloy foil, Fe and N
The coefficient of thermal expansion varies depending on the component ratio with i. In the present invention, the Ni content (% by weight) is in the range of 31 to 50% by weight, preferably 31 to 45% by weight.
If it is more than or less than this range, the coefficient of thermal expansion is large, and the difference in the coefficient of thermal expansion between the chip and the substrate cannot be suppressed.

The modulus of elasticity of the support layer was measured by a tensile tester (for example, Autograph manufactured by Shimadzu Corporation) and measured by 1GP.
a or more, preferably 10 GPa or more. A support layer of 1 GPa or less cannot exhibit a function as a support layer.

The thickness of the support layer is set in the range of 10 to 500 μm, preferably in the range of 20 to 200 μm. If the thickness is smaller than this, dimensional accuracy cannot be ensured. Further, the difference in thermal expansion between the circuit board and the silicon chip cannot be suppressed. If the thickness is larger than this, for example, it is not possible to easily form fine holes of 300 μm or less, and it becomes difficult to form a high-density circuit.

When a conductive support layer such as a metal foil is used, it is necessary to previously form a hole having a diameter larger than that of the electric conduction path in order to insulate it from the electric conduction path in the thickness direction. Is, for example, a drill, a punch, a laser or a chemical etching. And
After the holes are formed, an insulating resin is applied or filled on the peripheral surface of the holes (that is, the inner peripheral surface of the conductive support layer) to thereby insulate the inner peripheral surface.

As the metal foil for forming the circuit wiring layer, Cu, Ag, Au, Ni, Co or an alloy foil thereof is used. Before or after forming the through-hole of the insulating layer, heating is performed. It is pressed and laminated on both sides.

The circuit pattern is made of a photosensitive resist, an exposure,
It is formed using development, and is formed by a subtractive, additive, or semi-additive method by chemical etching, plating, or the like. If necessary, the circuit surface is polished, plated or rust-proofed.

The porous insulating layer, support layer, and circuit wiring layer obtained as described above are laminated using an adhesive. As the adhesive, a liquid or adhesive sheet of polyimide, polyamide, polyetherimide, epoxy, silicone or a mixture thereof is preferably used. Further, a polyester-based thermoplastic liquid crystal polymer film having low moisture absorption is also preferable. Alternatively, a porous insulating layer itself may be provided with an adhesive function using a thermoplastic material, and may be laminated without using an adhesive, or a resin solution may be applied to the support layer or the circuit wiring layer, and A porous treatment may be performed by a method, and the layers may be laminated. For lamination, a hot plate press, an autoclave that heats and pressurizes at atmospheric pressure, or the like can be used. The surface of the adhesive or the porous insulator layer is melted by heating and pressing at a temperature lower than the thermal decomposition temperature, and integrated with the support layer or the circuit wiring layer.

When a metal foil or a carbon fiber cloth having electric conductivity by itself is used for the support layer, the hole formed in the support layer is filled with an insulating resin in advance to insulate the inner periphery of the hole. There is a need. Unless insulated, when the circuit wiring is formed by electrically connecting the through holes after lamination, the through holes are short-circuited with a metal foil or the like.

The thickness of the adhesive layer is 0.01 to 0.5 m.
m. If it is smaller than this range, workability is poor. If it is more than this range, it is difficult to form a metal layer on the inner periphery of the through-hole or to fill the inside of the through-hole with a conductive paste or the like when electrically conducting through-holes formed after lamination. Become. In addition, the low dielectric effect of the porous heat-resistant material constituting the insulator layer is reduced.

In order to make the through holes of the insulating layer electrically conductive, a metal layer is formed on the inner peripheral surface of the through holes by electrolytic plating, electroless plating, sputtering or evaporation, or a conductive paste containing metal powder is printed. A method of filling the inside of the through hole with a squeegee using a method or a combination thereof is used.

The metal powder constituting the conductive paste includes S
n, Pb, Cu, Ag, Au, Ni, Pd, Zn, B
A single, alloy, or mixture of i, Sb, Co, etc. is used depending on the required heat resistance. Also, depending on the diameter of the through hole, 50
Those having a diameter of not more than μm, preferably not more than 10 μm are used. In particular, a solder material containing Sn (melted at a temperature of 300 ° C. or less) is melted in a heating and pressurizing step at the time of lamination to form an alloy layer with other metal powder constituting a conductive paste or a metal forming a circuit wiring layer. A highly reliable electrical connection is obtained. In order to make these metal powders into a paste, a predetermined amount of a binder such as an epoxy resin, a flux, an organic solvent, and the like are mixed as necessary.

The exposed portion of the electrical conduction path can be formed by being raised on a bump-like projection. In this case, the bumps pressed at the time of connection are crushed and follow the uneven shape of the chip or the substrate terminal, so that a reliable electrical connection is possible. Further, electrical conduction may be performed by using the above-described method by utilizing the holes of the porous insulator layer. In this case, it is not necessary to form the through holes after lamination. Alternatively, a method may be used in which a conductive paste is printed in a dot pattern on the circuit wiring layer, and the insulating layer is pierced and penetrated when the circuit board is laminated by heating and pressing.

As a method of forming a multi-layer circuit, a plurality of double-sided circuit boards composed of the support layer, the porous insulator layer and the circuit wiring layer as described above are formed, and these are aligned. And a method of performing multilayering by performing alignment using an adhesive layer such as an adhesive sheet. In this case,
On one surface of the double-sided circuit board, an adhesive sheet in which a through-hole is formed in advance is laminated according to the circuit pattern, or after the adhesive sheet is laminated, a hole is formed at a predetermined position with a laser or the like. Thereafter, a method of printing and filling the through-hole with the conductive paste to form a conductive path, aligning another double-sided circuit board, and laminating the same is used.

Alternatively, after forming a double-sided circuit board composed of the support layer, the porous insulator layer, and the circuit wiring layer as described above, a photoconductive porous insulator layer is laminated. Then, a predetermined insulator layer or a circuit pattern may be formed by exposure and development, and each circuit wiring layer and the insulator layer may be sequentially laminated while forming a conductive path in the thickness direction in the insulator layer. .

[0058]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the multilayer circuit board of the present invention. In the figure, reference numeral 1 denotes a double-sided circuit board in which a circuit wiring (circuit wiring layer) 4 made of copper foil is formed on both front and back surfaces of a porous insulator layer 3 having a Fe / Ni-based alloy foil 2 as a metal core layer. is there. In this embodiment, two double-sided circuit boards 1 are used, whereby a four-layer circuit board is manufactured as a multilayer circuit board. Reference numeral 5 denotes a conductive paste in a through hole 1a formed in each of the double-sided circuit boards 1.
This is an electrically conductive path filled with a, and electrically connects the circuit wiring 4 on both front and back surfaces. Reference numeral 6 denotes a polyimide adhesive layer for bonding the two-sided circuit boards 1 to each other. Reference numeral 7 denotes a conductive path for electrically connecting the circuit wiring 4 of each of the double-sided circuit boards 1. In the figure, reference numeral 8 denotes a polyimide-based adhesive layer formed on both front and back surfaces of the insulator layer 3.

The double-sided circuit board 1 can be manufactured as follows. That is, first, at a predetermined position (a position where the electric conduction path 5 is provided), the Fe /
A laminate 10 (see FIG. 2) comprising a Ni-based alloy foil 2 and a porous insulator layer 3 is prepared.
The polyimide-based adhesive sheet 11 is adhered from both front and back sides of the above to produce a laminate 12 as shown in FIG. Next,
As shown in FIG. 4, a portion of the laminated plate 12 corresponding to the through hole 2a of the Fe / Ni alloy foil 2
A through hole 1a smaller than a is opened. Next, as shown in FIG. 5, after the conductive paste 5a is filled in the through-hole 1a, a conductor layer 4a made of copper foil is bonded from both the front and back surfaces, so that the conductor layer 4a on both front and back surfaces is formed. The holes 1a are electrically connected by an electric conduction path 5 (formed by filling the conductive paste 5a) (see FIG. 6). Next, the circuit wiring 4 is formed on the conductor layers 4a on both the front and back surfaces of the double-sided copper-clad laminate 13 shown in FIG. 6 to manufacture the double-sided circuit board 1 (see FIG. 7).

The above-described multilayer circuit board can be manufactured as follows. That is, first, two double-sided circuit boards 1 (see FIG. 7) in which circuit wirings 4 are formed on both front and back surfaces of a porous insulator layer 3 having a Fe / Ni-based alloy foil 2 as a metal core layer, An adhesive sheet (see FIG. 8) 14 made of a polyimide-based adhesive is prepared. Next, as shown in FIG. 9, the adhesive sheet 14 is placed on the upper surface of one double-sided circuit board 1, and the opening 14a of the adhesive sheet 14 is placed on the double-sided circuit board 1.
Is temporarily aligned at a predetermined position of the circuit wiring 4 (the position where the conductive path 7 in FIG. 1 is provided). Next, a solder paste is put into the opening 14a of the adhesive sheet 14 by screen printing, and is heated and melted to form a solder bump 15 on the circuit wiring 4 of the double-sided circuit board 1 (see FIG. 10). Next, the double-sided circuit board 1 on which the solder bumps 15 are provided and the double-sided circuit board 1 on which only the circuit wiring 4 is formed are aligned and stacked (see FIG. 11), and then heated and pressed to be integrated. In this state, the adhesive sheet 11 holds the adhesive layer 8
The adhesive sheet 14 becomes the adhesive layer 6, and each solder bump 15 becomes the conductive path 7 (see FIG. 1). This allows
A four-layer wiring board in which the two double-sided circuit boards 1 are laminated and integrated can be obtained.

As described above, in this embodiment, the porous insulator layer 3 and the Fe / N
Since it has the i-based alloy foil 2, it has excellent low dielectric properties and low dielectric loss, and has sufficient mechanical strength. Further, the two double-sided circuit boards 1 can be integrated by one heating / pressing operation, and at the same time, the electrical connection between the four layers can be performed. In addition, since the Ni—Fe alloy foil 2 is provided in a ratio of one layer to the two layers of the circuit wiring 4, even when the circuit wiring 4 is formed of copper foil, the entire four-layer wiring substrate Can have a low coefficient of thermal expansion, and extremely high connection reliability can be obtained. Furthermore, the position of the joint of each conductive path 7 is not affected by the conductive paste 5a of the electric conductive path 5, and can be arranged at an arbitrary position. Therefore, the degree of freedom in design is increased and high-density wiring can be realized.

Hereinafter, the effects of the present invention will be described with reference to examples.

[0064]

EXAMPLE 1 Butanetetracarboxylic acid and 4,4'-diaminodiphenyl ether were dissolved in N-methyl-2-pyrrolidone (NMP) in approximately equimolar amounts, and polymerized at a temperature of about 200 DEG C. or less for 25 hours to obtain a polyimide. Polymer (30 ° C
At a limiting viscosity of 0.86). Polyvinylpyrrolidone was further added to and mixed with this polymer solution to obtain a dope consisting of 16% by weight of a polyimide polymer, 7% by weight of polyvinylpyrrolidone, 71% by weight of NMP, and 6% by weight of water. This was applied on a glass plate with a thickness of 30 μm and immersed in a water bath at 40 ° C. Next, the coated body was peeled off from the glass plate and stored in water for 24 hours to remove the solvent.

The obtained porous membrane 21 (see FIG. 12)
The structure had a thickness of 30 μm, no dense layer on the surface layer, and continuous holes formed in the thickness direction. The average pore diameter of the surface layer is 4 μm, the average pore diameter of the back layer is 2 μm, and the porosity is 70%.
was. The relative dielectric constant was 1.6 and the dielectric loss was 0.5%.

3,3 ', 4,4'-Tetracarboxydiphthalether dianhydride, 2,2-bis-4 (4-aminoxy) phenylpropane, and a diamine modified with a silicone at a terminal ratio of 1: 0. N so that 85: 0.15
Polymerization in -methylpyrrolidone gave a polyamic acid solution (solid content 20% by weight). This was applied, dried, and further treated at 300 ° C. to produce a thermoplastic polyimide film 22 having a thickness of 25 μm (see FIG. 12). The glass transition temperature of the produced thermoplastic polyimide film 22 is 21
It was 0 ° C.

Thermal expansion coefficient 20 ppm / ° C., elastic modulus 9.3 M
The surface of a support layer made of a polyimide film 20 (Upilex-75S manufactured by Ube Industries, Ltd.) having a thickness of 75 μm is roughened by sputtering, and a thermoplastic polyimide film 22, a porous film 21, and a thermoplastic polyimide film are formed on both surfaces. A copper foil 23a having a thickness of 18 μm was bonded by heating and pressing (5 MPa, 250 ° C., 60 minutes) to form a double-sided copper-clad laminate 24 (see FIG. 13).

Next, a through hole 24a of 200 μmφ was formed at a predetermined position by a puncher (see FIG. 14). A copper layer was formed on the inner peripheral surface of the through hole 24a using electroless plating and electrolytic plating, and a through-hole conductive path 25 was formed (see FIG. 15). Next, the circuit wiring 23 is formed on the copper foil 23a on both sides by an etching method, and the double-sided circuit board 26 is formed.
Was obtained (see FIG. 16).

On both surfaces of the double-sided circuit board 26, two porous films 27 (made in the same manner as the porous film 21),
Six thermoplastic polyimide films 28 (manufactured in the same manner as the thermoplastic polyimide film 22) and two 18 μm-thick copper foils 29a are heated and pressed (5 MPa,
(250 ° C., 60 minutes) (see FIG. 17), and copper foil 29 on both sides.
A substrate 30 having a was formed (see FIG. 18). Next, a through hole 30a of 200 μmφ was formed at a predetermined position by a puncher (see FIG. 19). A copper layer is formed on the inner peripheral surface of the through hole 30a using electroless plating and electrolytic plating,
A through-hole conductive path 31 was formed (see FIG. 20). Thereafter, circuit wirings 29 were formed on the copper foils 29a on both sides by an etching method to obtain a four-layer circuit board (see FIG. 21).

[0070]

Example 2 A film applicator was applied to a black-treated surface of a 35 μm-thick copper foil 36a (see FIG. 22) by doping with a 10 wt. Using the gap 50
It was applied to a uniform thickness of μm. After the application, it was blow-dried with a dryer at 100 ° C. for 15 minutes.

After drying, the temperature was lowered to room temperature, and the same dope was applied to the dried polyimide precursor film using a film applicator to form a gap of 100 μm.
And applied to a uniform thickness. Immediately after the application, the polyimide precursor was immersed in pure water at 25 ° C. to solidify the polyimide precursor. After coagulation, 90
Dry at ℃ for over 1 hour.

After drying, a heat treatment was performed at 400 ° C. for 3 hours in a nitrogen atmosphere, and the polyimide precursor was heated and closed to obtain a laminate 35 of a polyimide resin layer 37 and a copper foil 36a (see FIG. 22). The polyimide resin layer 37 includes a non-porous layer 38
(Thickness: 10 μm) and the porous layer 39 (thickness: 30 μm). The relative dielectric constant of the porous layer 39 was 1.6, and the dielectric loss was 0.5%.

Next, a bismaleimide-triazine resin prepreg 40 (GHPL-830, manufactured by Mitsubishi Gas Chemical Company, thickness: 100 μm, elastic modulus) was reinforced with a glass cloth so that the copper foil 36 a was exposed to the outside. 20
GPa, thermal expansion coefficient in the plane direction of 16 ppm / ° C.) as a support layer by heating and pressing (4 MPa, 200 ° C., 60 ° C.).
Minutes) and bonded to form a double-sided copper-clad laminate 41 (see FIG. 23). In FIG. 22, reference numeral 40a denotes an adhesive layer provided on both surfaces of the prepreg 40.

Next, a through hole 41a of 200 μmφ was formed at a predetermined position with a puncher (see FIG. 24). A copper layer was formed on the inner peripheral surface of the through hole 41a using electroless plating and electrolytic plating, and a through-hole conductive path 42 was formed (see FIG. 25). Thereafter, the circuit wiring 36 is formed on the copper foil 36a on both sides by an etching method, and the double-sided circuit board 4 is formed.
No. 3 was obtained (see FIG. 26).

A polyimide-based adhesive sheet 44 (SPB50, manufactured by Nippon Steel Chemical Co., Ltd.) was bonded to one side of the double-sided circuit board 43 by heating and pressing (2 MPa, 175 ° C., 30 minutes) (see FIG. 27), and then placed at a predetermined position. 200 to reach circuit wiring 36
A hole 44a of μmφ was opened by a YAG laser (see FIG. 28). Next, Sn-Sb solder paste (manufactured by Nippon Genma Co., Ltd.) mixed with 15% by weight of Ni powder was printed and filled in the opening 44a, and reflowed at a maximum of 240 ° C. for 1 minute to form a bump 45. (See FIG. 29). After that, another double-sided circuit board 43 is aligned and stacked (FIG. 3).
0) and heating and pressurizing (5 MPa, 180 ° C., 60 minutes) to obtain a four-layer circuit board (see FIG. 31).

[0076]

Embodiment 3 Thermal expansion coefficient: 3 ppm / ° C., elastic modulus: 70 GP
a, 350 μmφ, 500 μm on a support layer of carbon fiber cloth 50 (W3101 manufactured by Toho Rayon Co., Ltd.) having a thickness of 100 μm.
Through-hole 50a for through-hole conductive path 53 having a pitch of μm
Was drilled (see FIG. 32). Next, on both sides of the carbon fiber cloth 50, the laminated board 35 obtained in Example 2 was placed via a 50 μm-thick adhesive resin film 51 (a liquid crystal aromatic polyester FA grade manufactured by Kuraray Co., Ltd., glass transition temperature 205 ° C.). Is heated and pressurized (1 MPa, 290 ° C., 1
0 minutes), and the through-hole 50a was filled with an adhesive resin to form a double-sided copper-clad laminate 52 (see FIG. 33).

Next, a through hole 52a of 150 μmφ was formed at a predetermined position by using a YAG laser (see FIG. 34). A copper layer was formed on the inner peripheral surface of the through hole 52a using electroless plating and electrolytic plating, and a through-hole conductive path 53 was formed (see FIG. 35). Next, a circuit wiring 36 is formed on the copper foil 36a on both sides by an etching method.
4 was obtained (see FIG. 36).

Next, in the same manner as in Example 2, a polyimide adhesive sheet 55 (SPB50 manufactured by Nippon Steel Chemical Co., Ltd.) was bonded to one side of the double-sided circuit board 54 under heat and pressure (2 MPa, 17 MPa).
(5 ° C., 30 minutes) (see FIG. 37), and a hole 55 a of 150 μmφ reaching the circuit wiring 36 at a predetermined position is formed by YAG.
The laser was opened (see FIG. 38). Next, Sn-Sb mixed with 15% by weight of Ni powder was added to the opening 55a.
Solder paste (manufactured by Nippon Genma Co., Ltd.) was printed and filled, and reflowed at a maximum of 240 ° C. for 1 minute to form bumps 56 (see FIG. 39). After that, another double-sided circuit board 5
4 are aligned and overlapped (see FIG. 40), and heated and pressed (5
(MPa, 180 ° C., 60 minutes) to obtain a four-layer circuit board (see FIG. 41).

[0079]

Example 4 A hexane solution of isophthalic acid chloride and m-
An aqueous solution of phenylenediamine was reacted equimolarly to obtain an aromatic polyamide. This aromatic polyamide (precipitate)
Is repeatedly washed with water, alcohol, and water.
Vacuum dried for 2 hours to obtain a dried polymer. This polymer was dissolved in NMP at 80 ° C. and lithium nitrate was further dissolved to obtain a dope containing 5% by weight of lithium nitrate and 10% by weight of polymer.

A support layer of a 50 μm thick Fe / Ni alloy foil 2 (Ni content: 36% by weight, thermal expansion coefficient: 1.5 ppm)
/ ° C.), a through hole 2 a for the electric conduction path 5 having a pitch of 250 μm and a pitch of 350 μm was opened by chemical etching (see FIG. 2). This was immersed in the above dope and immediately immersed in a water bath at 40 ° C. After that, it was stored in water for 24 hours to remove the solvent. The obtained insulator layer 3 (see FIG. 2) is made of Fe / N
Both sides of the i-alloy foil 2 were formed with a thickness of 50 μm and filled the through holes 2a. Further, the finger void structure had continuous holes formed in the thickness direction. The average pore diameter was 5 μm for the minor axis, 25 μm for the major axis, and the porosity was 78%. The relative dielectric constant was 1.4 and the dielectric loss was 0.4%.

Next, a polyimide-based adhesive sheet 11 (SPB50 manufactured by Nippon Steel Chemical Co., Ltd.) having a thickness of 50 μm was bonded to both surfaces of the laminated plate 10 (see FIG. 2) by heating and pressing (2 MPa,
After 175 ° C. for 30 minutes (see FIG. 3), a through-hole 1a having a diameter of 150 μm was formed concentrically with the through-hole 2a using a YAG laser (see FIG. 4). Using a metal plate (opening diameter 200 μmφ, thickness 100 μm), Sn-Sb eutectic solder paste mixed with 15% by weight of Ni powder (manufactured by Nippon Genma Co., Ltd.) was filled into the through-hole 1a.
Furthermore, press both ends of the opening (10 MPa, 30 ° C.,
After 2 minutes), the paste was press-fitted, and excess metal powder was removed by buffing.

The electric conduction path 5 was obtained by heating to 230 ° C. under pressure and melting the solder powder (FIG. 5).
Of the laminated plate 12). On both sides of the laminated plate 12, a thickness of 1
The copper foil 4a of 2 μm is heated and pressed (5 MPa, 220 MPa).
(C, 15 minutes) to form a double-sided copper-clad laminate 13 (see FIG. 6). Next, circuit wirings 4 were formed on the copper foils 4a on both sides by an etching method to obtain a double-sided circuit board 1 (see FIG. 7).

A polyimide adhesive sheet 1 having a thickness of 50 μm
4 (SPB50 manufactured by Nippon Steel Chemical Co., Ltd.)
A through-hole 14a of mφ was formed with a YAG laser (FIG. 8).
reference). Next, the adhesive sheet 14 is positioned and adhered to one side of the double-sided circuit board 1 by heating and pressing (2 MPa,
(175 ° C., 30 minutes) (see FIG. 9). In the same manner as above, Sn-Sb solder paste (manufactured by Nippon Genma Co., Ltd.) was printed and filled to form bumps 15 (see FIG. 10). After that, another double-sided circuit board 1 is aligned and laminated (5 MPa, 240 ° C., 30 minutes) (see FIG. 11).
A four-layer circuit board was obtained (see FIG. 1).

[0084]

Embodiment 5 A support layer of a 50 μm thick Fe / Ni alloy foil 2 (Ni content: 36% by weight, thermal expansion coefficient: 1.5 ppm)
/.Degree. C.), a through hole 2a for an electric conduction path 5 having a diameter of 250 .mu.m.phi. This was immersed in the same dope as in Example 2, and immediately immersed in a water bath at 25 ° C. to solidify the polyimide precursor. After coagulation, 90
Dry at ℃ for over 1 hour.

After drying, the polyimide precursor was heat-treated at 400 ° C. for 3 hours in a nitrogen atmosphere, and the polyimide precursor was heated and closed to obtain a laminate of the polyimide resin layer 60 and the Fe / Ni alloy foil 2.
The porous layer of the polyimide resin layer 60 is formed on both sides of the Fe / Ni alloy foil 2 to have a thickness of 30 μm and fills the through-hole 2a, and has a relative dielectric constant of 1.6 and a dielectric loss of 0.1.
5%. Using this laminate, a double-sided circuit board 61 was produced in the same manner as in Example 4 except that the same polyimide-based adhesive sheet as in Example 1 (polyimide-based adhesive sheet 11) was used (see FIG. 42).

In the same dope as in Example 2, a photosensitive agent (4-o-
Nitrophenyl-3,5-dimethoxycarbonyl-2,
6-dimethyl-1,4-dihydropyridine and 4-o-nitrophenyl-3,5-diacetyl-1,4-dihydropyridine each in an amount of 2% by weight) and 3.8% by weight of urethane acrylate. A resin solution was obtained.

The photosensitive resin solution was applied to the double-sided circuit board 6
Using a spin coater on both sides, apply the coating so that the thickness of the coating after drying is 20 μm, and dry at 90 ° C. for 15 minutes, so that the urethane acrylate domain is formed in the coating layer 62. 62 were formed (see FIG. 43).

Next, 350 to 420 n are passed through a mask.
m ultraviolet light to 700 mJ / cm ² ,
After exposure in a hot air circulating oven at 180 ° C. for 10 minutes, heating is performed, and immersion treatment is performed in a developing solution. A hole 62a) was formed (see FIG. 44).

This was put in a 500 cc pressure vessel,
After pressurizing to 25 MPa in an atmosphere of ° C., carbon dioxide is injected at a flow rate of about 3 L / min while maintaining the pressure,
The air was evacuated and the urethane acrylate was extracted for 2 hours. Thereafter, the substrate was heated to a maximum temperature of 330 ° C. in a state where the pressure was reduced under a vacuum of 1.33 Pa, and an insulating layer made of a porous polyimide resin having a thickness of 12 μm and having closed cells was laminated.

Next, the inner periphery and both surfaces of the porous polyimide resin holes 62a are catalytically activated, and the holes 62a are filled by electroless plating and electrolytic plating to form conductive paths 63, and the thickness is reduced. A 10 μm copper layer 64a was formed (FIG. 4).
5). Thereafter, a circuit wiring 64 was formed by a chemical etching method to obtain a four-layer circuit board (see FIG. 46).

[0091]

Comparative Example 1 A copper foil 23a having a thickness of 18 μm and a porous film
1, a thermoplastic polyimide film 22, a porous film 21,
A copper foil 23a having a thickness of 18 μm was laminated, perforated, plated with through holes, and formed with a circuit wiring 23 by a chemical etching method to produce a double-sided circuit board (not shown).

Although the undulation of the substrate surface was large and there was a problem in appearance, a copper foil 23a having a thickness of 18 μm was adhered to both surfaces of the double-sided circuit board via the porous film 21 and the thermoplastic polyimide film 22. And copper foil 23a on both sides
Was formed. An attempt was made to form a 200 μmφ through hole at a predetermined position using a puncher, but a dimensional deviation occurred, and the circuit wiring 23 of the double-sided circuit board as an inner layer at a predetermined position was formed.
And conduction in the thickness direction of the four-layer circuit could not be obtained.

[0093]

COMPARATIVE EXAMPLE 2 In Example 2, without using the support layer of the glass cloth reinforced bismaleimide-triazine resin prepreg 40, they were bonded by heating and pressing (4 MPa, 200 ° C., 60 minutes), and the polyimide resin layer 37 and copper Laminated plate 35 with foil 36a
Was bonded by heating and pressing (4 MPa, 200 ° C., 60 minutes) so that the copper foil 36 a was exposed to the outside to form a double-sided copper-clad laminate (not shown).

Next, a through hole 41a of 200 μmφ was formed at a predetermined position by a puncher. A copper layer was formed on the inner peripheral surface of the through hole 41a using electroless plating and electrolytic plating, and a through-hole conductive path 42 was formed. After that, the circuit wiring 36 was formed on the copper foil 36a on both sides by an etching method to obtain a double-sided circuit board (not shown).

A polyimide adhesive sheet 44 (SPB50, manufactured by Nippon Steel Chemical Co., Ltd.) was bonded to one side of the double-sided circuit board by heating and pressing (2 MPa, 175 ° C., 30 minutes), and then 200 μmφ reaching a predetermined position to the circuit wiring 36. Hole 44a was opened with a YAG laser. Next, the opening portion 44a
Is filled with a eutectic solder paste (manufactured by Nippon Genma Co., Ltd.) mixed with 15% by weight of Ni powder.
The reflow was performed in minutes to form the bumps 45. Thereafter, another double-sided circuit board was aligned and stacked, and integrated by heating and pressing (5 MPa, 180 ° C., 60 minutes) to obtain a four-layer circuit board (not shown).

[0096]

Comparative Example 3 The same dope as in Example 2 was applied to a glass plate and immediately immersed in a water bath at 25 ° C. to solidify a polyimide precursor. After coagulation, it was dried at 90 ° C. for 1 hour or more.
After drying, heat treatment at 400 ° C. for 3 hours in a nitrogen atmosphere,
The polyimide precursor was heat-closed and peeled from the glass plate to obtain a polyimide porous film having a thickness of 30 μm.

Using the thermoplastic polyimide film 22 produced in Example 1, a thermoplastic polyimide, a polyimide porous film, a thermoplastic polyimide, a polyimide porous film, and a thermoplastic polyimide were laminated.

Next, a through hole of 150 μmφ was formed with a YAG laser. Using a metal plate (opening diameter 200 μmφ, thickness 100 μm), N
A Sn-Sb eutectic solder paste (manufactured by Nippon Genma Co., Ltd.) mixed with i powder at 15% by weight was printed and filled. Further, both ends of the opening were pressed (10 MPa, 30 ° C., 2 minutes), and after press-fitting the paste, excess metal powder was removed by buffing.

An electric conduction path was obtained by heating to 230 ° C. under pressure and melting the solder powder. Thereafter, a copper foil having a thickness of 12 μm was laminated on both sides of the laminate by heating and pressing (5 MPa, 220 ° C., 15 minutes), and circuit wiring was formed on the copper foil on both sides by an etching method. Is shifted from the circuit position, and conduction of the double-sided circuit cannot be obtained.

Examples 1 to 5 produced as described above
Shock test (-6)
5 to 150 ° C., 10 minutes each), and the presence or absence of electrical conduction in the thickness direction of the substrate was examined. The results are shown in Table 1 below.

[0101]

[Table 1]

The samples of Examples 1 to 5 and Comparative Example 2 were each provided with a flip chip (8
mm □, 100i / o daisy chain, 120μmφ
The sample on which the Sn / Pb solder bumps (300 μm pitch) were mounted (without underfill) was subjected to a heat cycle test (−40 to 125 ° C., 10 minutes each), and the presence or absence of electrical conduction in the thickness direction of the substrate was examined. . The results are shown in Table 2 below.

[0103]

[Table 2]

As is clear from Tables 1 and 2, it can be seen that the products of Examples 1 to 5 have better mechanical strength than the product of Comparative Example 2.

Although the above-described embodiments and examples are examples of multilayering up to a four-layer circuit, they can be laminated using a similar method to produce a multilayer circuit board having four or more layers. .

[0106]

As described above, the multilayer circuit board of the present invention has an insulator layer made of a porous heat-resistant material,
It has a support layer for holding the insulator layer and a plurality of circuit wiring layers. As described above, the multilayer circuit board of the present invention supports the porous insulator layer having insufficient mechanical strength by the support layer, and thus has excellent low dielectric properties and low dielectric loss. Has sufficient mechanical strength.

When a material having a high elastic modulus is used as a material constituting the support layer, the mechanical strength of the entire laminated structure can be greatly improved. In addition, when a low thermal expansion material is used, a difference in thermal expansion from silicon can be reduced, so that generation of stress can be suppressed. Therefore, dimensional stability can be obtained by laminating the support layer having high elastic modulus and low thermal expansion with the porous insulator layer, and the positional dimensional accuracy of the circuit wiring is improved,
Positioning between circuit wiring layers at the time of lamination and chip mounting becomes easy. In particular, when a metal foil having a low thermal expansion is used, it has excellent rigidity and is hard to crack even when bent. In addition, it bears the pressure at the time of mounting at the time of bare chip mounting, has a high effect of suppressing stress due to a difference in thermal expansion, and has a high reliability.

On the other hand, according to the method for manufacturing a multilayer circuit board of the present invention, a multilayer circuit board exhibiting the above-described excellent effects can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of a multilayer circuit board of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the multilayer circuit board.

FIG. 3 is a cross-sectional view showing a manufacturing process of the multilayer circuit board.

FIG. 4 is a sectional view showing a manufacturing process of the multilayer circuit board.

FIG. 5 is a cross-sectional view showing a manufacturing process of the multilayer circuit board.

FIG. 6 is a cross-sectional view illustrating a step of manufacturing the multilayer circuit board.

FIG. 7 is a sectional view of the multilayer circuit board.

FIG. 8 is a cross-sectional view showing a step of manufacturing the multilayer circuit board.

FIG. 9 is a cross-sectional view showing a step of manufacturing the multilayer circuit board.

FIG. 10 is a cross-sectional view showing a step of manufacturing the multilayer circuit board.

FIG. 11 is a cross-sectional view showing a step of manufacturing the multilayer circuit board.

FIG. 12 is a cross-sectional view showing a process of manufacturing the four-layer circuit board of Example 1.

FIG. 13 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the first embodiment.

FIG. 14 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the first embodiment.

FIG. 15 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the first embodiment.

FIG. 16 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the first embodiment.

FIG. 17 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the first embodiment.

FIG. 18 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the first embodiment.

FIG. 19 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the first embodiment.

FIG. 20 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the first embodiment.

FIG. 21 is a sectional view showing the four-layer circuit board of the first embodiment.

FIG. 22 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 2.

FIG. 23 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 2;

FIG. 24 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 2;

FIG. 25 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 2;

FIG. 26 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 2;

FIG. 27 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 2;

FIG. 28 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 2;

FIG. 29 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 2;

FIG. 30 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 2;

FIG. 31 is a sectional view showing the four-layer circuit board of the second embodiment.

FIG. 32 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 3.

FIG. 33 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the third embodiment.

FIG. 34 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the third embodiment.

FIG. 35 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the third embodiment.

FIG. 36 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 3;

FIG. 37 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 3;

FIG. 38 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the third embodiment.

FIG. 39 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 3;

FIG. 40 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 3;

FIG. 41 is a sectional view showing the four-layer circuit board of the third embodiment.

FIG. 42 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of Example 5;

FIG. 43 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the fifth embodiment.

FIG. 44 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the fifth embodiment.

FIG. 45 is a cross-sectional view showing a step of manufacturing the four-layer circuit board of the fifth embodiment.

FIG. 46 is a sectional view showing the four-layer circuit board of the fifth embodiment.

[Explanation of symbols]

 2 Alloy foil 3 Insulator layer 4 Circuit wiring 5 Electrical conduction path

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kei Nakamura 1-1-2 Shimohozumi, Ibaraki-shi, Osaka Nitto Denko Corporation (72) Inventor Shinya Ota 1-2-1, Shimohozumi, Ibaraki-shi, Osaka Inside Nitto Denko Corporation (72) Kenichi Ikeda 1-1-2 Shimohozumi, Ibaraki City, Osaka Prefecture Inside Nitto Denko Corporation (72) Shu Mochizuki 1-1-2 Shimohozumi, Ibaraki City, Osaka Prefecture Nitto Denko In-house F-term (reference) 5E346 AA03 AA04 AA06 AA12 AA15 AA29 AA32 AA43 CC05 CC10 CC32 CC37 CC38 CC39 CC54 CC55 DD03 DD32 DD33 EE02 EE12 EE13 EE15 EE18 EE20 FF01 FF06 FF07 FF08 FF09 HFF HFF HFF HFF HFF HFF HFF HFF HFF HFF H

Claims (10)

[Claims] 1. A circuit comprising an insulator layer, a support layer holding the insulator layer, and a plurality of circuit wiring layers, wherein a circuit is formed using an electrical conduction path penetrating the insulator layer and the support layer. A multilayer circuit board in which each layer of a wiring layer is electrically connected at a predetermined position, wherein the insulator layer is made of a porous heat-resistant material. 2. The multilayer circuit board according to claim 1, wherein the porosity of the insulator layer made of the porous heat-resistant material is 30% or more and less than 98%. 3. The method according to claim 1, wherein the porous heat-resistant material is a polyimide resin or a polyamide resin.
The multilayer circuit board according to the above. 4. A hole having a diameter of 0.05 μm or more formed in a state where a hole of the insulator layer made of the porous heat-resistant material penetrates the insulator layer in a thickness direction of the insulator layer. The multilayer circuit board according to claim 1, further comprising a hole. 5. The insulating layer made of the porous heat-resistant material has pores each having a pore diameter of 0.
The multilayer circuit board according to any one of claims 1 to 3, wherein the multilayer circuit board includes a hole having a diameter of 05 m or more. 6. The support layer has a tensile modulus of 1 GP.
a, the coefficient of thermal expansion in the plane direction is 2 at 20 to 250 ° C.
The multilayer circuit board according to claim 1, wherein the multilayer circuit board has a concentration of 0 ppm / ° C. or less. 7. The support layer comprises a metal core layer made of an Fe / Ni-based alloy foil, the Ni content of which is 31 to 5.
The multilayer circuit board according to claim 1, wherein the multilayer circuit board has a weight of 0% by weight and a thickness of 10 to 500 μm. 8. The multilayer circuit board according to claim 1, wherein the electric conduction path includes a solder material that melts at 300 ° C. or lower. 9. A step of forming a first laminate by laminating conductor layers on both sides of a support layer holding the insulator layer via an insulator layer formed of a porous heat-resistant material; Forming an electrical conduction path through the insulator layer and the support layer of the first laminate; forming circuit wiring on conductor layers on both sides of the first laminate to form a double-sided circuit board; A step of making;
A step of laminating at least a conductor layer on a circuit wiring layer on both sides of the double-sided circuit board via an insulating layer made of a porous heat-resistant material to produce a second laminate;
Forming a conductive path penetrating from the conductor layer on the front surface to the conductor layer on the back surface of the laminate, and forming circuit wiring on the conductor layers on both surfaces of the second laminate. Of manufacturing a multilayer circuit board. 10. A step of forming a first laminate by laminating conductor layers on both surfaces of a support layer holding the insulator layer via an insulator layer formed of a porous heat-resistant material; Forming an electrical conduction path through the insulator layer and the support layer of the first laminate; forming circuit wiring on conductor layers on both sides of the first laminate to form a double-sided circuit board; A step of preparing, a step of preparing two or more double-sided circuit boards, a step of aligning the two or more double-sided circuit boards, and forming an adhesive insulating resin layer having a conductive path in a thickness direction formed at a predetermined position. And electrically connecting the circuit wiring layers of the two double-sided circuit boards sandwiching the adhesive insulating resin layer by the conductive path.