JP2002132709A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor capable of unwanted radiation by an inexpensive method without lowering a transfer clock. SOLUTION: This data processor has a means for changing a transfer cycle for each of transfer cycles of serial transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processor having a clock signal line and a data signal line, and serially transferring data in synchronization with a clock signal.

[0002]

2. Description of the Related Art Serial transfer using a clock signal line and a data signal line can be realized by a simple configuration of both a transmission circuit and a reception circuit, and the number of signal lines required for transfer can be reduced. Widely used in data processing equipment. For example, in a serial printer, printing is performed by a print head mounted on a carriage, and serial transfer is used for data transfer from a control board of the printer to the print head. The print head has 160 inkjet nozzles, and the electrical circuit is a 160-bit shift register, 160
A bit latch circuit and a driving circuit for each nozzle are provided. Each bit data stored in the latch circuit is associated with print data of each nozzle.

FIG. 5 shows a timing chart of a serial transfer in a conventional example. Clock signal CLK and data signal DATA
, The 160-bit data is serially transferred and stored in a shift register in the print head. The stored data is stored in a latch circuit by a latch signal LAT and used as print data. Shift register and latch circuit 2
With the multi-stage configuration, print data can be stored in the shift register next while printing is performed using the data of the latch circuit. Assuming that the transfer period T is 200 ns, the frequency of the clock signal is 5 MHz.

[0004]

However, since information processing apparatuses generate electromagnetic waves due to high-speed changes in electrical signals associated with data processing, even if the apparatus does not aim to generate electromagnetic waves, it does not. are doing. This electromagnetic wave is called unnecessary radiation and generates noise on nearby televisions and radios and causes malfunctions of other information processing devices. Therefore, it is preferable that the electromagnetic wave be as small as possible. Unnecessary radiation is regulated in many countries, and a device that generates unnecessary radiation exceeding a specified value cannot be shipped. Therefore, it is indispensable to suppress unnecessary radiation to a specified value or less.

However, in order to improve the processing speed of the information processing apparatus, it is necessary to shorten the transfer time even in serial transfer, and the clock frequency of the transfer tends to increase. This causes an increase in unnecessary radiation.
In particular, serial transmission tends to generate unnecessary radiation since it transmits a relatively long distance among information processing apparatuses.

[0006] Also in a printer, a flexible cable or the like having a length of about several tens of cm is often used for data transfer from a control board of the printer to a print head, and this cable acts as an antenna to generate unnecessary radiation. Tends to.

FIG. 6 is a graph showing the frequency components of the clock signal shown in FIG.
Shown in In Fig. 6, from 40MHz to 160M where unwanted radiation is likely to occur
The frequency range up to Hz is displayed. Clock frequency 5M
Strong peaks occur every 10 MHz, which is twice the Hz.
At these frequencies, there is a high possibility that a peak occurs even at the unnecessary radiation level. In order to keep the peak value below the specified value, it is necessary to take expensive shielding measures and use components such as a noise filter. These measures have caused the price of the information processing device to increase.
Unnecessary radiation has been a factor that hinders an increase in transfer speed, such as the necessity of reducing the clock frequency of serial transfer in order to lower the unnecessary radiation level.

[0008] The present invention has been made in view of the above points, and it is an object of the present invention to provide a data processing apparatus capable of reducing unnecessary radiation without lowering a transfer clock by an inexpensive method.

[0009]

In order to achieve the above object, a data processing apparatus according to the present invention has means for changing a transfer cycle for each transfer cycle of serial transfer.

[0010] According to the above configuration, the frequency of unnecessary radiation can be dispersed to suppress the radiation level.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings. FIG. 1 is a block diagram showing a main configuration of a control circuit of a printer, which is one of data processing apparatuses embodying the present invention. In FIG. 1, 1 is a CPU, 2 is a ROM, 3 is a parallel interface, 4 is a printer control IC, 5 is RAM, 6 is a print head, 8 is a carriage motor, and 9 is a paper feed motor. 10 is a serial transfer circuit.

The CPU 1 controls the entire printer, and includes a timer function, an input / output port, and the like in addition to a processor unit for executing a program. The ROM 2 stores programs executed by the CPU 1 and various data necessary for control. The parallel interface 3 is connected to a host system such as a computer and receives print data and commands. The printer control IC 4 is connected to the CPU 1 by a bus signal.
Parallel interface 3, R based on the instruction from 1
Controls AM5 and print head 6. The RAM 5 is used for storing received data, image data, and the like. The print head 6 is an inkjet head in which 160 inkjet nozzles are arranged in a line, and is controlled by the printer control IC 4. Data transfer from the printer control IC 4 to the print head 6 includes a clock signal CLK, a data signal DATA,
Serial transfer using three signal lines of the latch signal LAT is used. The carriage motor 8 is controlled by the CPU 1 to scan the carriage in the main scanning direction. Paper feed motor
Reference numeral 9 is controlled by the CPU 1 to convey the print medium in the sub-scanning direction. Serial transfer circuit 10 is a printer control IC
4 for transferring data to the print head 6.

FIG. 2 is a block diagram showing a configuration of the serial transfer circuit 10. In FIG. 2, 21 is a control unit, 22 is a pattern generator, 23 is a frequency divider, 24 is a counter, and 25 is a shift register. The control unit 21 controls the transfer circuit and outputs the latch signal LAT. The pattern generator 22 is a circuit based on a shift register, and determines a transfer cycle for each transfer cycle of serial transfer by outputting a specific pattern to the signal PER. Divider 23 is the original vibration 25
The clock signal CLK is output by dividing the MHz. The frequency division of the original vibration is determined by the level of the signal PER. Counter 2
4 manages the number of transfer data by counting clocks.
Shift register 25 is an 8-bit parallel data signal D
[7: 0] is converted to serial data and output as a data signal DATA. The parallel data signal D [7: 0] is updated every 8 bits of the serial transfer.

FIG. 3 is a timing chart showing the operation of the transfer circuit 10. The control unit 21 starts the operation in response to the start pulse of the START signal. After outputting a pulse to the LAT signal, the control unit 21 initializes the pattern generator 22,
And the operation of the counter 24 are enabled. The pulse of the LAT signal causes the data previously serially transferred to the print head to be stored in a latch circuit in the head. Pattern generator
Reference numeral 22 outputs a specific pattern to the PER signal using the CLK signal as a clock. The frequency divider 24 divides the frequency of the original signal by 4 when the PER signal is at the L level, and outputs the CLK signal by dividing the frequency of the original signal by 25 when the PER signal is at the H level. Since the source vibration is 25 MHz, the period Tl when dividing by 4 is 160 ns, and the period T2 when dividing by 6 is 240 ns
become. The counter 24 counts the CLK signal, and sets the STOP signal to the H level at the 160th clock, that is, when the counter value is 159. The control unit 21 ends the operation in response to the STOP signal. The shift register 25 converts the parallel data D [7: 0] into serial data using the CLK signal as a clock, and outputs the data signal DATA.

With the above operation, 160-bit data is serially transferred. The cycle of each transfer cycle changes for each cycle based on the pattern output from the pattern generator 22. Since the ratio between T1 and T2 is 2 to 1, the average transfer cycle is 186.7 ns, and the effective transfer frequency is 5.3.
6MHz.

FIG. 4 shows the frequency components of the clock signal shown in FIG.
In FIG. 4, the peaks are dispersed and the height of the peak is lower than in FIG. 6, so that the peak of the unnecessary radiation is also lower. Therefore, while the transfer frequency of the serial transfer shown in FIG. 5 was 5 MHz, the level of unnecessary radiation should be kept low in spite of the fact that the transfer frequency of the serial transfer shown in FIG. 3 is substantially increased. Is possible.

[0017]

As described above, according to the present invention, a data processing apparatus for serially transferring data in synchronization with a clock signal has means for changing a transfer cycle for each transfer cycle of serial transfer. In addition, unnecessary radiation can be reduced without lowering the transfer clock.

Further, by suppressing the radiation level,
It is possible to reduce the cost of the data processing device by reducing noise suppression components such as a shield material and a noise filter.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main configuration of a data processing device.

FIG. 2 is a block diagram illustrating a main configuration of a serial transfer circuit.

FIG. 3 is a timing chart of serial transfer.

FIG. 4 is a graph showing frequency components of a clock signal for serial transfer.

FIG. 5 is a timing chart of serial transfer in a conventional example.

FIG. 6 is a graph showing frequency components of a clock signal for serial transfer in a conventional example.

[Explanation of symbols]

 1 CPU 2 ROM 3 Parallel interface 4 Printer control IC 5 RAM 6 Print head 8 Carriage motor 9 Paper feed motor 10 Serial transfer circuit 21 Control unit 22 Pattern generator 23 Divider 24 Counter 25 Shift register

Claims (2)

[Claims] 1. A data processing device having a clock signal line and a data signal line, and serially transferring data in synchronization with a clock signal, wherein a means for changing a transfer cycle for each transfer cycle of serial transfer is provided. A data processing device characterized by the above-mentioned. 2. A data processing apparatus having a clock signal line and a data signal line and serially transferring data in synchronization with a clock signal, wherein a source signal for generating a source signal for generating a clock signal is generated. A signal generator, a pattern generator for generating a predetermined pattern, a source signal from the source signal generator and a pattern from the pattern generator, and a frequency division ratio according to the pattern from the source signal. A frequency divider for generating clock signals different from each other.