JP2002132520A - Program control method and apparatus using the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a program control method and an apparatus using the method capable of selecting an option program responding to functions desired by a user and capable of setting an arrangement configuration of memories responding to operations of the selected program. SOLUTION: In the method, when it is decided that the option program is selected at a step 24-100, the program is stored on a memory (STEP 24-110), next, a maximum value of memory capacity of work data needed at the operations of each program is calculated (STEP 24-200), work areas needed at each program are arranged on the memory responding to the maximum value (STEP 24-300).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention provides a method for freely selecting a program to be operated and a memory configuration according to a purpose of use.
The present invention relates to a program control method that can be controlled and an apparatus using the method.

[0002]

2. Description of the Related Art Conventionally, when programs having different specifications are operated, individual programs are created, and programs conforming to the specifications are individually operated, or when only the memory capacity is different, individual programs are created. Sometimes, it was necessary to specify the required memory capacity before operating.

[0003]

However, when operating programs having different functions, a hardware package is separately created, a program adapted to each function is developed, and even if the functions are the same, the program is used. If the memory configuration is different, or the size or the number used is different, there is a problem that a program must be created for each, and a capacity must be set at the time of creation.

Further, in a program package capable of realizing a plurality of functions, when a user uses different functions, there is a problem that a program and a memory capacity must be set according to the function configuration to be used.

An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to select an option program corresponding to a function desired by a user, and to store data in a memory according to the operation of the selected option program. An object of the present invention is to provide a program control method capable of setting an arrangement configuration and an apparatus using the method.

[0006]

In order to achieve the above object, the present invention provides a program control method for controlling a plurality of functions to be realized by a program, wherein a plurality of option programs are selected according to a selection operation by a user. A plurality of functions corresponding to the plurality of option programs are realized by setting a memory area required for operation of each of the plurality of selected option programs on a memory and executing the plurality of selected option programs. It is characterized by doing.

Here, in the program control method of the present invention, when selecting the option program, option selection information indicating all of the option programs to be selected according to a user's selection operation is generated, and Each of the selected option programs may be arranged in the memory based on the generated option selection information. In the case where the memory areas are respectively set in the memory, the maximum memory capacity of a data configuration (work data area) necessary for operation of each of the selected option programs is calculated based on the option selection information. Then, a memory area necessary for operation of the selected option program may be arranged on the memory according to the calculated maximum memory capacity.

Further, in the above-mentioned present invention, a memory area necessary for operation of the selected option program may be arranged in a partial area of a RAM.
Further, the memory may be an expandable RAM, and a memory area necessary for operation of the selected option program may be arranged in a partial area of the basic RAM and an entire area of the added RAM. More preferably, the memory capacity is smaller than the memory capacity required for operation of all selectable optional programs.

Further, in order to achieve the above object, the present invention comprises an arithmetic processing unit and a memory unit, and the arithmetic processing unit executes a plurality of option programs, for example, a telephone billing function and a traffic data collecting function. In an apparatus that implements a plurality of functions, a selection unit that selects an option program in accordance with a user's selection operation, the selected option program, and a data configuration necessary for operation of the option program are stored in the memory unit. And a memory arranging means for arranging the memory.

According to the program control method of the present invention, in order to achieve the above object, an area for selecting an optional program (function) to be operated and an area for each function for recognizing an area to be used in accordance with the function. A work area for determining the use / non-use information is provided on a memory, and the area use / non-use information is read by reading the function presence information stored in the medium for each function, and the recognition can be performed.
Each memory is provided with a capacity area for recognizing the size from the read information, and a function and a capacity value are determined at the time of starting the system, and program control can be performed.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, a device using the program control method of the present invention and having a traffic data collection function and a telephone billing function will be described as an example.

FIG. 1 shows a memory (RAM, ROM) and a central controller (C) to which the program control method of the present invention is applied.
FIG. 2 is a configuration diagram illustrating a basic configuration of a device including a (PU).
That is, the device of the present embodiment is a central control device (CP
U) 14, a ROM (IP) for controlling the initial startup of the device.
L) 11, a hardware control interface unit 12 for controlling communication control and the like, an ATA card storing a basic program and selectable optional programs, an ATA card storing key data for identifying an optional program to be selected, and the like ATA control interface unit 13 for controlling the basic and optional programs, program work data, station data, etc.
The AM 15, the additional RAM-1 (16), the additional RAM-2 (17), which can store an optional program added in accordance with the operation and can be added as a work area for data storage, and the components 11 to 17 are connected. A bus 18 is provided.

FIG. 2 shows an example of a storage area configuration of the RAMs 15 to 17. The basic RAM 15 includes a backup area 211 for work and operation data, a basic program area 212 in which a basic program always required for system operation is stored, and a variable RAM area 213 whose contents can be changed according to operation. It is composed. Variable R
For example, when an option program is selected, the AM area 213 stores the selected option program, data necessary for its operation, and the like. Further, the additional RAM-1 (16) and the additional RAM-2 (1
7) is provided as a variable RAM area in the case where the storage area is insufficient in the basic RAM 15, each of which is added according to the required capacity.

FIG. 3 shows an example of the detailed configuration of the basic program stored in the basic RAM 15. The basic program of this example includes a fixed unit 300 in which the memory capacity to be used is fixed in advance, and a variable unit 310 in which the memory capacity to be used is variable.

In the fixed part 300 of the basic program of this embodiment, a main body IPL (SYSYIPL PRG) program 3 called from the ROM IPL 11 at the time of system startup is provided.
01 and a common SUB JM that can be started even if a commonly used program is called from any area
P table 302, GTR common SU controlling a GTR common subroutine used only in the program level GTR
B JMP table 304 and RAM JM for controlling program startup corresponding to each hardware interrupt
The P table 304 is stored. Here, the GTR is a common routine used only at the level of a general transaction (a queue routine at the lowest level of a program).

On the other hand, the variable section 310 has a basic message area 311 for securing a message of the basic program,
Common SUB PRG where the actual common program is located
An area 312, a GTR common SUB PRG area 313 in which an actual GTR common program is placed, an initial program area 314 for initializing each work, etc.
In addition, programs SYS1 (315) to SYS5 (317) necessary for operating the basic program are arranged. Also, a sufficient spare area 318 is provided so as to be able to cope with additional functions and the like.

FIG. 4 shows a configuration example of a program arranged on the basic ATA card 40. Basic ATA card is AT
It is connected to the A card control interface unit 13, downloads the basic programs and option programs stored in the basic ATA card to the device side, and writes data for backup.

The basic ATA card 40 of this embodiment is provided with a program section 41 for storing programs and the like, and a data writing section 42 for writing operation data.
The program unit 41 includes, for example, the basic program 400, the option program 410, the communication control program 420 used for communication control, and the basic card recognition character string OUS SYS4 for recognizing the basic ATA card.
40, a recognition character string SYSIPL431 with the basic program loading program for recognizing that the basic program loading program is in the ATA card, and a recognition character string SYSYTM430 with the basic program for recognizing that the basic program is in the card are stored. Have been.

Data writing section 42 of basic ATA card 40
For example, as shown in FIG.
Extension unit data 451 to 453, office line billing unit data 454 to 455, and logging data 456
Is stored. Here, the station data constant 450 corresponds to the work and operation data backup area 21 shown in FIG.
The extension units 451 to 453 are areas in which information such as a charge for each telephone is stored.
This corresponds to the size shown in (501). In this example,
Only the case of extension capacity 1024, 2048, 10240 is described.

FIG. 5 shows an example of the configuration of an option presence / absence storage area for storing information for indicating the selection status of an option program, that is, for storing and determining the presence / absence of an option. This option presence / absence storage area is stored as station data for operation in the work and operation data backup area 211 shown in FIG. 2, and can be assigned to the entire memory area, that is, the basic RA shown in FIG.
M15 variable RAM area 213, additional RAM-1 (1
6) and the additional RAM-2 (17) are used to determine the memory capacity to be used according to the selected option.

The option presence / absence storage area of the present embodiment can be selected from an extension capacity area 501 for controlling the capacity of an extension to be used, an external detail output soft area 510, a billing detail accumulating and expanding area 520, an external detail expanding area 530, and the like. It is composed of information 560 indicating the content of the option program, an option valid / invalid flag 550 indicating whether or not each option program is selected, and an option number 540 for identifying each option program.

The setting of the option presence / absence flag 550 in FIG. 5 is managed by reading the option ATA card 60 storing the option number 540 to be selected. FIG. 6 shows a configuration example of the optional ATA card 60. The option ATA card 60 includes, for example, an option number 600 for recognizing an option program to be selected with the option ATA card, and an OU indicating that the ATA card is an option card.
S OPT mark 610 is stored.

In the apparatus of the present embodiment, for example, as many as the number of options selectable in the apparatus, FIG.
The optional ATA card 60 shown in FIG. 1 is prepared, and one or a plurality of optional ATA cards indicating options corresponding to the functions required by the user are sequentially connected and read, so that the apparatus according to the present embodiment should be realized. Select an optional function.

In this embodiment, each option AT
Although the A card is configured to select a single option program, an optional ATA card capable of selecting a plurality of option programs may be prepared and used for option selection as needed.

FIG. 7 shows an office transaction save area 700 in which office transaction values corresponding to the extension capacity 501 shown in FIG. 5 are stored in advance in correspondence with the number of extensions. Also, FIG. 8 is similar to FIG. 5 and FIG.
And a variable RAM area maximum value storage area 800 for storing the maximum value of the work data required for the operation of each option program.

The local line transaction save area 700 and the variable RAM area maximum value storage area 800
Are stored in the work and operation data backup area 211 shown in FIG.

Variable RAM area maximum value storage area 800
7 corresponds to the contents of the option selected in FIG.
0, a maximum transaction area value area 801 for storing the maximum transaction value determined with reference to 0, a maximum extension area area 802 for the extension unit, a maximum accumulation area area 803 for other billing extensions, and a maximum accumulation area area 80 for external details.
4 and so on.

FIGS. 9, 10, 11, and 12 show the data of each unit which is created in a number corresponding to the operation capacity of the selected option program and is arranged in the variable RAM area 213 in FIG. An example of the configuration is shown.

In the present embodiment, FIGS.
2 are local line transaction units (128
Byte), extension unit (256 bytes), billing detail storage unit (64 bytes), and external detail unit (64 bytes). These units are created in a number corresponding to the maximum value 801 of the local line transaction, the maximum value 802 of the extension unit, the detail storage area 803 for billing, and the maximum value 804 of the external detail unit shown in FIG.
They are sequentially arranged in the M area 213. Note that the additional RAM 1
(16) When the additional RAM 2 (17) is mounted, the variable RAM area
Use as

FIG. 13 shows an example of a hardware configuration of an apparatus having a telephone billing and traffic data collection function having the basic configuration shown in FIG.

As shown in FIG. 13, the apparatus of this embodiment has a basic RAM 1300 and batteries (BATTA) 1310 and 131 for memory backup for backing up the RAM.
1), a switch (SW) 1312 for controlling ON / OFF of a memory backup battery, an ATA card insertion unit 1
320, additional memory -1 to increase RAM capacity according to specifications
(1330), extension memory-2 (1331), connector 1340 for attaching extension memory-1, extension memory-
2 is provided with a connector 1341 for mounting the communication terminal 2, a command, a maintenance terminal, a communication port-1 (1350) for external communication, and a communication port-2 (1351).

Further, the apparatus of this embodiment has a card key 1363 used when inserting and removing an ATA card,
LED 1363-1 for indicating no, a reset key 1364 for resetting the system, an IPL key 1361 for reading data in the ATA card, a dump key 1 used when writing operation data to the ATA card
365, a compare key 1360 used when comparing data in the ATA card with data in the RAM, a boot key 1 used when initializing the ATA card and the RAM
362, LEDs 1370 and 1371 for displaying a communication line state and a failure state of the RAM, and a CPU 1370 for controlling the system.

Incidentally, the main body package 1390 of the apparatus of this embodiment
And additional memory-1 (1330) and additional memory-1
(1332) is constituted by a separate package, and is added only when necessary. Also, memory backup batteries 1310 and 1311 for backing up the memory
Are the additional memory-1 (1330) and the additional memory-2 (1
The RAM data of 331) can also be backed up.

FIGS. 14 and 15 show an example of processing executed in the apparatus of the present embodiment. This processing belongs to the basic program described above, and activates only the basic part when the apparatus of the present embodiment is operated only with the basic program, and activates the basic part and the optional program when the optional program is selected. This is the main part of the program startup.

In FIG. 14, the REST processing (step 14-000), which is started by a reset interrupt, proceeds to the following step 14-211.

In the exception processing (step 14-100) in which an interruption occurs during execution of the exception processing (illegal instruction execution), the contents of the exception processing are logged in a preset error information storage area, and an infinite loop (WDT) interrupt wait is performed. .

In level 7 processing (step 14-200) in which an interrupt is generated in a WDT or an infinite loop, the contents of a failure are logged in a preset failure logging area.
ROM IPL processing described later (steps 14-21)
1), an initial process (steps 14-212) is executed. This processing will also be described later, but when this processing ends,
The program goes online, the system clears the infinite loop, which is the operation program lock determination (steps 14-213), and performs a program SAM check (steps 14-214) to check that the program area has not been improperly rewritten. The program area is divided and steps 14-215, 14-216, 14-21
7, and 14-218.

In the level 6 processing (14-300) in which an interrupt occurs every 500 ms, the value of 500 ms is stored 50
Update one 0 ms counterwork. This 500ms
The counter work has a LONG size area, and returns to 0 upon overflow.

In FIG. 15, the level 5 processing interrupted every 4 ms (steps 14-400) is a level control means for controlling the main tasks of the operation of the present apparatus. First, the WDT for determining whether or not the 4 ms interrupt has stopped is cleared (step 14).
(-400), prohibit level 4, level 3, level 2, and unused level 1 which are not to be activated during this interrupt processing.

The H level control processing (steps 14-410) and the L level control processing LLVCTL (steps 14-42) are performed for each task priority.
0), high-level queue (triggered in order of occurrence) TRC control processing (steps 14-43)
0), M level control processing MLVCTL (steps 14-440), N level control processing NLVC
TL (steps 14-450) and low-level control processing (steps 14-460) are executed.

H level control processing (step 14)
(−410) is the highest priority control process that starts every 4 ms. In the L level control process (step 14-420), it starts every 20 ms.
The task activation time of each L level is controlled.

FIG. 16 shows an example of the task configuration in the L level control processing (steps 14 to 420).
FIG. 7 shows an example of a task activation configuration at this level. This example has a 16-bit configuration, and can start up to 16 tasks. The start timing is controlled by a task start table shown in FIG. Here, rows 16-90 in FIG.
The task group shown in each of FIGS.
The system is activated every 0 ms.

For example, Task 1 shown in FIG.
s, the first bit (16-01) of each row extending in the horizontal direction in the table shown in FIG.
Is set to "1" in all rows 16-90 to 16-99. Further, in order to activate Task2 in, for example, 40 ms, data corresponding to the second bit (16-02) of each row is intermittently set to "0" in row 16-90 and "1" in row 16-91. Set.

Each task includes a basic task (14-900) belonging to the above-described basic program and an optional task (14-910) belonging to the optional program. When the program is created (when the system is started by the initial program), The configuration shown in FIGS. 16 and 17 is created in advance.

Returning to FIG. 15, the M level control processing (steps 14 to 440) is started every 8 ms, and has the same configuration as the L level control processing. Also, N-level control processing (step 1)
4-450) is activated every 100 ms, and has the same configuration as the M level control processing and the L level control processing.

TRC ring processing (steps 14-43)
0) is a program for executing not the process started periodically but the sequential process if there is data in the ring buffer. Specifically, this processing is performed in step 14-6 described later.
When the information from the PBX is picked up at 00 and written to a transaction ring buffer that is not filled in,
It starts when there is information by looking at this ring.

The processing at the remaining levels will be described. In this example, in addition to the above-described processing, a level 4 processing (steps 14-500) activated by an interruption due to communication data of the connection terminal (I / O), and a level 3 processing activated by an interruption with the PBX (Steps 14-600), L
It has a level 2 process (steps 14-700) in which an interrupt is activated by LAN transmission / reception data by an AN connection, and an unused level 1 process (steps 14-800).

FIGS. 18 to 24 are flowcharts showing an example of the processing flow at the time of starting the program. This process is shown in FIG.
This will be described in conjunction with FIG.

When a reset interrupt (when the system is activated or the reset key is pressed) of the REST processing (step 14-000) is entered, the ROM IPL processing (step 14-2) is performed.
11) After that, the processing shifts to the main processing in FIG.
This processing is the same processing as Steps 14-212 in FIG. In this processing, initial processing necessary for operation (step 17-100) is performed. Specifically, as shown in FIG. 19, the initialization of the interrupt processing (steps 17-11)
0), initialization of flags (steps 17-111) is executed.

Returning to the processing of FIG. 18, in order to enable various types of interrupts, an interrupt inhibition release processing (step 17-1)
01). Note that the interrupt prohibition processing is performed by the RO
This is performed by MIPL processing. In the present embodiment, FIGS.
As shown in the processing of (1), REST processing (step 14-000), exception processing (step 14-100),
Level 7 processing (Steps 14-200), Level 6 processing (Steps 14-300), Level 5 processing (Step 1)
4-400), level 4 processing (steps 14-50)
0), level 3 processing (steps 14-600), level 2 processing (steps 14-700), and level 1 processing (steps 14-800).

It should be noted that level 5 (step 14)
-400) is activated, for example, by a periodic interrupt every 4 ms, and by performing the interrupt prohibition canceling process (step 17-101), enters an interrupt waiting state in step 17-102, and activates the level 5 process once every 4 ms. Is done. In the interruption waiting (steps 17-102), each interruption is waited while executing the processing of steps 14-213 to 14-218 in FIG.

When an interrupt of 4 ms is input, FIG. 14 and FIG.
The processing described in 5 is executed. The level control processing of FIGS.
14 shows details of activation of the processing programs from 14 to 470.

Here, the H level control processing (steps 14-410) corresponds to steps 17-200 through 17-200 in FIG.
17-205, L level control processing (step 1
4-420) corresponds to steps 17-300 through 17-300 in FIG.
17-306, TRC ring process (steps 14-43)
0) corresponds to steps 17-320 to 17-322 in FIG.
M level control (steps 14-440) is shown in FIG.
1 (B), steps 17-310 to 17-316, and the base level control (steps 14-470) are shown in FIG.
0 corresponds to steps 17-208 to 17-212, respectively. In the description of this configuration example, the description of NLVCTL (steps 14 to 450) is omitted.

During the H-level processing, the interruption is inhibited for 4 ms. Therefore, when this level control processing is started, the interruption inhibition processing (steps 17-200) is first performed.
Next, since the L level is activated once every 20 ms and the M level is activated once every 8 ms, the activation bit (level flag) is updated (step 17-201). In this example, FIG.
As shown in step 17-300 of FIG. 21A and step 17-310 of FIG.
ms × 5 = 20 ms) and the M level flag is 2 (4 ms × 5 ms)
2 = 8 ms). The abbreviation N
Since the level starts at 100 ms, when adding a process, it is determined whether the process is performed 25 times or more.

Next, H_lv_ctl processing is executed (step 17-202). Fig. 1
6 corresponding to the L-level llv_ctl_tbl shown in FIG. That is, at the H level, FIG.
Two sets corresponding to the configuration of FIG. 17, and 3 sets at the L level
There are two sets at the M level.

In this H_lv_ctl processing, FIG.
As shown in (A), it is checked whether the activation flags of the H-level tasks 1 and 2 are ON (steps 17-400, 17-40).
2) Turn ON with the initial program according to the operation.
This is because the program to be started differs depending on the option. H_task_prog1, 2 (steps 17-401, 17-403) are processes for activating an actual task (program) with reference to FIGS. Here, the reason why there are only tasks 1 and 2 is that as shown in FIG.
6. In the sense that there are two configurations in FIG. 17 and FIG. 17, the task (program) activation can actually activate 32 tasks in 16 × 2 as can be seen from FIG.

Returning to the processing of FIG. 20, step 17-20
At 3, it is determined whether an interrupt has occurred at the L level.
This is because when a 4 ms interrupt is input again during execution of the L-level task and the processing is executed from step 17-200, the processing is executed in step 1
This is a determination to return to the interrupted processing instead of executing from the L-level control of 7-300.

If it is determined in step 17-203 that an interrupt has occurred at the L level, an L level restart flag is set (step 17-204), and interrupts are generated at the L level, M level, and base level. Is determined (step 17-205). If it is determined that an interrupt has occurred, the interrupt mask is cleared (step 17-206), and the process moves to the interrupt occurrence point (17-206).
207).

In this example, the H-level task is a new 4m
s interrupt is not accepted and executed, but after the L level, if a 4 ms interrupt occurs even during task activation, the process returns to the interrupted place after executing a higher level process and resumes the process. . For this reason, important tasks are arranged and executed at such a level as not to be interrupted.

For example, if there is a 4 ms interrupt during the execution of a group of programs activated by the optional programs indicated by the black circles below steps 14-450 in FIG. 14-4
Execute Step 10. In the control of step 14-420, if the execution time of the group of programs activated by the optional program indicated by the mark ● below step 14-420 is 20 ms, the program group is executed, and 430, proceed to steps 14-440,
At step 14-450, it is determined that the processing is in progress, and the processing is shifted to the position where the program group marked with "●" below step 14-450 is interrupted, and another activation of step 14-450 is determined. Becomes

In step 17-204, the L level is interrupted by 20 ms. However, if the processing exceeds 20 ms in the entire L level within 20 ms, the start of 20 ms will not be protected, so the step 17-204 described later will be performed. 30
6 is for determining L-level restart.

If it is determined in step 17-205 that no interrupt has occurred, a base level interrupt occurrence flag is set (step 17-208), the interrupt mask is cleared (step 17-209), and the base level processing is performed. (Steps 17-210). Next, interrupt mask processing is performed (step 17-211), and the base level interrupt occurrence flag is cleared (step 17-2).
12). Here, the base level indicates a level in the BLVCTL process executed in steps 14 to 470 in FIG. 15 and is a program described as GTR.

On the other hand, if it is determined in step 17-203 that no L-level interrupt has occurred,
To step 17-300, and determine whether the L level flag is 5 or more. If it is 5 or more, the L level flag is cleared (step 17-301), and the L level interrupt flag is set (restart flag clear) (step 1).
7-302). Next, after clearing the interrupt mask (steps 17-303), L_lv_ctl shown in FIG.
The processing is executed (steps 17-304).

The processing shown in FIG. 24 is basically the same as that shown in FIG.
This is the same as the H_lv_ctl processing shown in FIG. L_tas
For k_progs 1, 2, and 3, respectively, FIG.
The processing described above with reference to FIG. 17 is executed. The reason why three task_progs are provided only for the L level is that the configuration is such that 48 tasks can be started in 16 × 3.

Returning to the processing of FIG. 21A, L_lv_c
After the tl process (step 17-304) is completed, an interrupt mask process is performed (step 17-305), and it is determined whether or not there is an L-level restart (step 17-30).
6). If there is a restart, the process returns to step 17-300. If there is no restart, the L level interrupt flag is cleared (step 17-307), and the process proceeds to step 17-309 of FIG.

If the L level flag is less than 5 in step 17-300, the flow advances to step 17-306.

In step 17-309, it is determined whether or not an interrupt has occurred at the M level. If it is determined that the interrupt has occurred, an M level restart flag is set, and
It returns to step 17-205 of FIG. If it is determined that no interrupt has occurred, the TRC process shown in FIG. 22 is performed (steps 17-309a).

In the TRC process, it is determined whether an interrupt has occurred in the TRC ring (steps 17-320). If it is determined that an interrupt has occurred, steps 17-205 in FIG. 20 are performed.
Return to If it is determined that no interrupt has occurred,
It is determined whether the read / write for the TRC ring is different (steps 17-321).
The C ring (steps 14 to 430 in FIG. 15) is activated (steps 17 to 322).

Returning to the processing of FIG.
At -310, it is determined whether the M level flag is 2 or more, and if it is 2 or more, the M level flag is cleared (step 1).
7-311), an M level interrupt flag is set (restart flag clear) (step 17-312), and the interrupt mask is cleared (step 17-313).
The lv_ctl process (steps 17 to 314) is executed. The M_lv_ctl process is the same as the process at the H level in FIG. 23 (A), although the level is different, as shown in FIG. 23 (B), and the description is omitted here.

Returning to the processing of FIG.
After performing the interrupt mask processing at -315, it is determined whether there is an M-level restart (steps 17-316). If there is no restart, the M level interrupt flag is cleared (steps 17-317) and step 17-2 in FIG.
05, if there is a restart, step 17-31
Return to 0. If it is determined in step 17-310 that the M level flag is less than 2, the M level interrupt flag and the M level restart flag are cleared (step 17).
-319).

The processing in the apparatus of this embodiment will be described in more detail.

FIGS. 25 to 27 are flow charts showing the startup processing of the system according to the present embodiment. Reset (R
EST: Step 14-000 in FIG. 14) or IRQ
7 (level 7: step 14-200 in FIG. 14), the cause of the interrupt is stored (step 18-100).

FIG. 28 shows hard keys 1360 to
A configuration example of a hardware for saving each reset factor at the time of key input of 1365 or the like is shown. Here, the hard work is a storage area used to notify corresponding software that an event has occurred in hardware. For example, when a certain key switch is depressed, a corresponding bit is set so that the fact is noticed.

The hardware work of this example is a POW-ON (19-100) indicating that the power is on, an IPL key (19-110) indicating that the IPL key is pressed, and so on.
SP reset (19-130), CMP key (19-1)
40), a monitor key (19-150), a soft reset (19-160), and a reboot key (19-170).

Further, the hard work of the present example has a {loop (1) indicating that the reset is activated by an infinite loop.
9-190), a WDT (19-180) indicating that the 4 ms interrupt has not been activated is provided, and these factors are saved.

Further, the hard work of the present example includes:
Different from reset factors, a DMP key (19-200) used when saving memory to ATA, a card key (19-210) used when removing a card, additional RA
Additional RAM-1 existence / non-existence (19-240) for judging the presence / absence of M-1 mounting, Additional RAM-2 existence / non-existence (19-230) for judging the presence / absence of extension RAM-2, ATA
An ATA card presence / absence (19-220) for determining the presence / absence of card insertion is provided.

Returning to FIG. 25, it is next determined whether or not an ATA card has been inserted (step 18-101). If no card has been inserted, the process proceeds to step 18-130.

When it is determined that the ATA card is inserted, for example, by detecting the recognition mark 431 with the basic program load program shown in FIG. 4, the basic program load program SYSIPL in the ATA card is detected. The presence / absence is determined (steps 18-110).

If there is no SYSIPL, step 18-
Proceed to 130, and if there is, the basic ATA shown in FIG.
From the card, the basic program load program contained in the basic program 400 (FIG. 4) is stored in the SYSIPL in the basic program area of the basic RAM 15 shown in FIG.
(Basic program load program) is read into the area 301.

Next, it is determined whether or not the basic program load program (SYSIPL) exists in the memory (on the RAM) (steps 18 to 130). If there is no SYSIPL, the process moves to FIG. 27, where "NO IPLPGFUND" is set in a predetermined error message storage area (steps 18-300).

Next, when the reset factor is the power ON (POWO)
N) or not (step 18-301),
In the case of N, it is determined that the processing is indefinite (the RAM has never been in the operating state), and the infinite loop processing (step 14-3)
20), and waits for a key input.

When the power is not turned on, the presence or absence of the basic program (SYSTEM) in the memory is determined in order to determine whether or not operation is possible with the current data in the RAM. (Steps 18-310). If undefined (no), the process proceeds to the infinite loop processing (step 14-320) as described above. If valid (yes), the restart type is set to "LDIPL" and the online initial program (INIT3 in FIG. 3) is executed.
The processing shifts to 14).

At step 18-130 in FIG. 25, the basic program load program (S
YSIPL), the process proceeds to FIG.
The processing shifts to the basic program load program (SYSIPL) read from the OMIPL. Up to here is R
This is the OMIPL process.

Now, the operation of the basic program load program (SYSIPL) will be roughly described with reference to FIG. According to the restart type recognized by the ROM IPL, the basic program load program (SYSIPL) performs each processing (steps 18 to 140), shifts the processing to the online initial program (INIT 314 in FIG. 3), and adds the contents of the restart type. At the same time, the memory is initialized, and the memory goes online (operation) (step 18-9).
00, 18-901).

Next, the reboot process (steps 20-100) first performed in the system start-up process will be described with reference to FIG.
This will be described with reference to FIGS. The reboot process is a process for initializing a RAM area, loading a basic program, and performing a basic operation in order to operate the program.

As shown in FIG. 29, the ROM IPL
The restart type is activated by booting (step 20-10).
0), the presence or absence of card insertion is determined again. If there is no card inserted, ATA will be used despite system initials.
To indicate that a card has not been inserted, "NO CARD" is set in a predetermined error message area (steps 20-200), RST is set in the restart type (steps 20-201 in FIG. 30), and online initials are set. The processing shifts to the program (INIT 314 in FIG. 3).

If it is determined that a card has been inserted, the AT
It is determined whether there is a basic program in the A card (steps 20-110). If there is no basic program in the ATA card, it means that it cannot be operated because there is no basic program, so "NOMASTER FOUN"
D "is displayed as a message, and RS
T is set (steps 20-201 in FIG. 30), and an online initial program (INIT314 in FIG. 3) is set.
The processing shifts to.

If it is determined in step 20-110 that the basic program exists in the ATA card, the R shown in FIG.
All the AM areas are written, and it is checked whether the reading is valid (steps 20-120). At this time, the additional RAM
1. The additional RAM-2 has the additional RAM-1 with / without (19-240) and the additional RAM-2 with / without (19-23) shown in FIG.
By determining 0), the extension unit is also checked.

When writing or reading is impossible,
In order to notify that the memory is NG, L in FIG.
The ED 1370 or 1371 is turned on, and an infinite loop is waited for hardware replacement, and the process is terminated (steps 20-140 and 20-141 in FIG. 30).

In FIG. 30, when writing and reading are possible, the basic program is read from the ATA card in FIG.
Basic program, common SUB JMP table 302
To the spare area 318 are read into the memory (steps 20-130).

After the reading is completed, the resuming type is set to "BOO".
As T "(steps 20-140), the processing shifts to the online initial program (INIT 314 in FIG. 3) (steps 20-150).

Next, the online initial processing is performed as shown in FIG.
This will be described with reference to the flowcharts of FIGS.

First, a case where the online initial process is started (step 21-000) in the above-described reboot process will be described. In this case, first, as shown in FIG. 2, the constant part 211 of the work and operation data backup area, the variable RAM area 213, and the additional RA
M-1 (16) and additional RAM-2 (17) are cleared to "0" (steps 21-1000).

Next, data is written to the station data constant section 450 of the ATA card 40 shown in FIG. 4 (step 2).
1-110). At this time, no information is written in the extension unit of FIG. 4 because it is not possible to determine the presence or absence of the option at this time.

Thereafter, the work area is cleared to "0", the system is put into operation (step 21-010), and the system is brought online (starting up). At this point, only the basic program is operated, and thereafter, options are set to create a RAM configuration.

From this online (system operation) initial state, the input / output terminal is connected to the communication port 135 shown in FIG.
0 or 1351, a mode for changing a large amount of data that cannot be changed on-line, a maintenance program is started, and option data is read.

Next, FIG.
This will be described with reference to FIGS. When the maintenance is started, the option storage area shown in FIG. 5 is evacuated to the maintenance option storage area (step 22-000 in FIG. 34). The option storage area and the maintenance option storage area are provided in advance, for example, in the work and operation data backup area 211 in FIG. The current state of the option storage area is all cleared to “0” by the reboot process. This option storage area is stored once the options are set,
This is for the purpose of comparing and determining when additional changes are made again in this mode.

When the saving is completed, the input of the command is awaited, and the input command is analyzed (step 22-).
100). As a result of analysis, if the command is a data change,
The command is executed according to the input contents (step 22).
-101), and again waits for a command input.

When the optional ATA load command is input, first, the optional card recognition mark "OUS OPT" shown in FIG. 6 is determined, and the optional ATA card is checked (step 22-200 in FIG. 36).
"ATA CARD ERR" for different cards
(Steps 22-300) are connected to the communication ports 1350, 1
From 351, output is performed from the terminal connected thereto, and command input is awaited.

If the operation is normal, the option recognition number 600 shown in FIG. 6 is read, and the option is added to the maintenance option storage area (step 22-21).
0).

The optional ATA card reading process is performed only for the required number of times, and the optional reading operation is completed.
Note that the optional ATA card has a read counter in the card so that it cannot be used a plurality of times, and performs a process of clearing the count to "0" and making it unusable when a specified number of read operations are performed.

When the reading of the option data is completed, FIG.
Returning to step 22-100 of step 4, a maintenance end command is input to end the maintenance mode.

When the end command is input, the maintenance option storage area is compared with the option storage area shown in FIG. 5 to determine whether or not the option data has been changed (step 22-400).

If there is no change in the option data, the processing is shifted to the online initial program (INIT 314 in FIG. 3) with the restart type set to “maintenance recovery” (steps 22 to 450 in FIG. 35).

If there is a change in the option data, it is determined whether or not a RAM having a capacity corresponding to the read option is connected (step 22-50 in FIG. 35).
0) If the RAM capacity is insufficient, an "additional RAM insufficient" error message is output (steps 22-800), and command input is waited.

The required RAM capacity is shown in FIG.
In the start-up processing described later using 1, 42, when the reading of the option program and the selection status thereof are determined, the capacity necessary for the operation of the selected option program is determined.

If the RAM capacity is sufficient, before and after the change of the option content is output from the terminal, and the confirmation of the option content is prompted (step 22-600).

If there is an error in the contents, a cancel command is input (steps 22-900),
The command input waits again, and the option information is corrected by the command including the processing in steps 22-800. Note that it is impossible to add the read option information using a command, but it is possible to delete the option information.

If the contents of the option are correct, a confirmation command is input, so that the soft reset 1 shown in FIG.
9-160 is set (step 22-700), an infinite loop process (step 22-710) is performed, and an interrupt is waited. After reading the option information, the basic ATA
A card return program reading process is performed.

When an interrupt occurs, step 1 in FIG.
The above-described ROM IPL process starting from 8-100 is performed, and the SYS IPL process determines the cause of the reset (steps 18-140 in FIG. 26), and thereafter the process proceeds to the PRG load process.

Next, details of the PRG loading process will be described.
This will be described with reference to FIGS. First, when the PRG load is activated, the basic program “SYS” is stored in the memory.
The presence / absence of "TEM" is checked to determine whether the memory is valid (step 23-000 in FIG. 37).

If the memory is undefined, an error due to the PRG loading process is set by using the watchdog timer (WDT) as an error factor, the error content is logged in a predetermined error storage area, and the process waits for an interrupt in an infinite loop process. When the memory is valid, the basic program “SYST” is stored in the card to perform the program loading process from the ATA card.
EM "is checked (step 23-10).
0).

If the basic program is not in the ATA card, it is impossible to read the program.
An error message “O MSTER FOUND” is set in the error message storage area, and the process proceeds to the RTS processing in steps 18 to 140 shown in FIG. 26. If the basic program is found in the ATA card, the option data is stored in the maintenance processing. The contents are moved to the option storage area (FIG. 5) for online use (steps 23-120 in FIG. 38).

Next, the basic program is read from the ATA card into the memory (the basic RAM 15 in FIG. 2) (steps 23-130). Further, it is determined whether or not it is necessary to read an option program (internal charging program) based on the presence or absence of the option content 501 in the option storage area (steps 13-140).

If there is no option (internal charging), the process proceeds to step 23-160. If there is an option (internal charging), the option program is stored in the memory (410 in FIG. 2) from the ATA card (410 in FIG. 4). R
AM area 213) (step 23-15).
0).

After reading, “PRG load” is set to the restart type.
As an online initial program (INI in FIG. 3)
The process moves to (T314) (steps 23-16)
0).

Next, returning to the online initial processing described above, the PRG loading will be described in detail. PRG loading is determined by online initial processing, and the presence or absence of option information is determined in the option storage area (FIG. 5) (steps 21 to 200 in FIG. 32).

When there is no option information, the variable RAM
The area 212 is all cleared to "0", and the constant part (the operation data area 211 in FIG. 2) is written to the ATA card (FIG. 4) (steps 21 to 310 in FIG. 33).

If there is optional information, it is determined whether or not there is an optional program (internal charging) (step 21-2).
10) After the option program (internal charging), the contents of the options stored in the option storage area of FIG. 5 and the respective MAX values shown in FIG. 8 are determined (step 21).
-220), build up the memory. If there is no option program (internal charging), the contents of the option shown in FIG. 5 and the respective MAX values shown in FIG. 8 are determined from the next of the basic program (steps 21 to 240), and a memory is built up (steps 21 to 240). ). The memory creation process will be described later. Steps 21-220 and 21-250 are processing for writing data necessary for each configuration to the basic ATA card shown in FIG.

Next, the memory creation process will be described with reference to FIGS. Here, FIG. 39 shows an example of a memory creation processing flow, and the creation processing when there is an optional program will be described as an example. FIG.
0 indicates the RAM configuration after the completion of this process.

In the present process, first, it is determined whether or not an optional program is selected by referring to, for example, the contents of the optional storage area shown in FIG. 5 (24-100). The option program 410 of the card 40 is stored in the option program area 25-11 on the basic RAM 15 shown in FIG.
0 is read (steps 24-110).

Next, the maximum value of the memory capacity of the work data area required by each option program as shown in FIG. 8 is calculated from the contents of the option storage area of FIG. 5 (steps 24-200). As specific processing, for example, steps 24-210 to 24-240
Process as follows.

In this example, if the extension capacity 512 has been selected in the option storage area, the number of extensions is set to 512 (steps 24-210).
Since it is 12, the line transaction value in FIG. 7 is determined to be 128 (steps 24-220). Also,
When the external specification output software is not selected in the option storage area in FIG. 5, the external number storage maximum number is set to “0” (steps 24-230), and when the charging specification storage addition is selected, , Maximum value 60
000 (steps 24-240) is set. In this example, the number of billing details stored is determined in advance to be 4096 when there is no extension, and 60000 when there is. Here, the number of extensions, the number of local line transactions, the number of external details, and the number of billing details correspond to the numbers of the data structures shown in FIGS. 10, 9, 12, and 11, respectively.

Next, based on the maximum value obtained in the above-described steps, the configuration is arranged on the actual memory (variable RAM area) in the order of the configuration of the maximum value as shown in FIG. 8 (steps 24-300). In this example, 128 bytes (FIG. 9) × 128 are secured as the line transactions,
The memory area 25-200 shown in FIG. 40 is used as a local line transaction area (steps 24-31).
0).

The extension unit is 256 bytes (FIG. 10).
The memory area for memory area 25-2 shown in FIG.
10 as an extension unit (step 24-3).
20). Similarly, a memory area is secured based on the option storage area and the number thereof, and at the same time, an address or an address area corresponding to each area during program operation is calculated and operated.

By completing the above processing, the variable RA is changed from the basic configuration of the RAM shown in FIG. 2 to the selection status of the optional program of this example and the system operation status.
In the M area 213 (FIG. 2), storage areas 25-110 to 25-230 for option programs and work data are provided.
Are assigned, and a configuration as shown in FIG. 40 is formed.

FIG. 41 shows an example of the start-up procedure processing in the apparatus of the present embodiment described above.

In this process, first, the hardware configuration state such as the presence or absence of an additional RAM is detected, and the connection state of the input / output terminal or PBX for creating station data is detected (steps 41-100). , Basic ATA Card 40
(FIG. 4) is received (step 41-10).
2). Next, an initial startup (reboot) process is performed (steps 41-104), and a group of programs necessary for the initial startup such as the basic program 400 stored in the program section 41 of the basic ATA card 40 is read into the basic RAM 15. .

Next, an option program is selected. In this embodiment, after the basic ATA card 40 is removed, insertion of the optional ATA card 60 provided with data (option number) for indicating an option to be selected as shown in FIG. (Steps 41-108 to 41-112 and 41-12
4), one or more option programs to be selected are determined, and an information table indicating an option selection status as shown in FIG. 5 is generated.

Next, the optional ATA card 60 is removed, the basic ATA card 40 is reinserted (steps 41-114), and the option program to be selected determined above is transferred from the basic ATA card 40 to the variable R on the device side.
The contents are read into the AM area 213 and the contents of the operation corresponding to the selected option program are determined (steps 41 to 116). Further, a memory capacity corresponding to the determined operation content is obtained, and R is sufficient to secure the memory capacity.
It is determined whether the AM is installed in the device (steps 41 to 118).

If the capacity of the RAM is not sufficient, an error message to that effect is output (step 41-).
126) Return to steps 41-108 to redo the option selection. Instead of re-selecting the option as in the present embodiment, the present process may be terminated and a necessary amount of RAM may be added.

If it is determined that the RAM capacity is sufficient, the option program selected according to the processing procedure shown in FIG.
The layout is set on the variable RAM area 213, the RAM area configuration adapted to the operation as shown in FIG. 40 is constructed (steps 41 to 120), and the operation is started (step 41).
-122).

According to the present embodiment, an option program corresponding to a function desired by the user is selected from a plurality of selectable functions, and the memory arrangement is set according to the operation of the selected option program. be able to.

Further, according to the present embodiment, the RA on the device side is
Even when the capacity of M is relatively small, it is possible to select an optional program as needed. Therefore, a large number of optional programs can be prepared to expand the range of selection by the user, and at the same time, the RAM to be mounted on the device can be provided.
Can be kept to the minimum necessary, so that the economy and convenience can be improved.

In the present embodiment, selectable option programs are stored in the basic ATA card, all of them are temporarily read into the basic RAM 15, and then the types of options actually used are determined by the option ATA card. However, the method of reading the option program in the present invention is not limited to this. For example, a program relating to the basic program is stored in the basic ATA card, and the program is first transferred to the device side memory, and the optional program to be actually used is stored in the optional ATA card, and these are sequentially stored in the device. By moving to the side, a group of programs necessary for operation may be arranged on the RAM of the apparatus.

[0136]

According to the present invention, an option program corresponding to a function desired by a user is selected from a plurality of selectable functions, and a memory arrangement is set according to the operation of the selected option program. And a device using the method.

Further, according to the present invention, it is possible to use one CPU and hardware and operate programs having different functions as required, and to select different works required for operation and perform operations. The matching capacity can be varied. Therefore, it is possible for the user to freely select the operation with one program and one hardware.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a connection configuration example of a memory and a central control unit (CPU) according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating a configuration example of a RAM area according to the embodiment;

FIG. 3 is an explanatory diagram showing a configuration example of a basic program in the present embodiment.

FIG. 4 is an explanatory diagram showing a program arrangement of a basic ATA card in the embodiment.

FIG. 5 is an explanatory diagram showing a configuration example of an option storage area in the embodiment.

FIG. 6 is an explanatory diagram showing a configuration example of an optional ATA card in the embodiment.

FIG. 7 is an explanatory diagram showing a configuration example of an area for storing a line transaction value according to the embodiment;

FIG. 8 is an explanatory diagram illustrating a configuration example of a variable RAM area maximum value storage area according to the present embodiment.

FIG. 9 is an explanatory diagram illustrating a configuration example of a line transaction in the present embodiment;

FIG. 10 is an explanatory diagram illustrating a configuration example of an extension unit in the present embodiment.

FIG. 11 is an explanatory diagram showing a configuration example of a billing detail storage unit in the present embodiment.

FIG. 12 is an explanatory diagram illustrating a configuration example of an external specification unit according to the present embodiment.

FIG. 13 is an explanatory diagram showing a hardware configuration of the device of the present embodiment.

FIG. 14 is an explanatory diagram illustrating a configuration example of a program task according to the embodiment;

FIG. 15 is an explanatory diagram illustrating a configuration example of a program task according to the embodiment;

FIG. 16 is an explanatory diagram illustrating an example of a task configuration table in program level control according to the present embodiment.

FIG. 17 is an explanatory diagram illustrating an example of a task activation table in program level control according to the present embodiment.

FIG. 18 is a flowchart of a program activation process (part 1) in the embodiment.

FIG. 19 is a flowchart of a program activation process (part 2) in the embodiment.

FIG. 20 is a flowchart of a program startup process (part 3) in the embodiment.

FIG. 21A is a flowchart of a program activation process (part 4) in the present embodiment. FIG. 21B is a flowchart of a program start process (part 5) in the present embodiment.

FIG. 22 is a flowchart of a program activation process (part 6) in the embodiment.

FIG. 23A is a flowchart of a program activation process (part 7) in the present embodiment. FIG. 23B is a flowchart of a program start process (8) in the present embodiment.

FIG. 24 is a flowchart of a program activation process (part 9) in the embodiment.

FIG. 25 is a flowchart illustrating a system startup process (part 1) according to the present embodiment.

FIG. 26 is a flowchart illustrating a system startup process (part 2) according to the present embodiment.

FIG. 27 is a flowchart illustrating a system startup process (part 3) according to the present embodiment.

FIG. 28 is an explanatory diagram illustrating a configuration example of a hard work according to the present embodiment.

FIG. 29 is a diagram illustrating a reboot process (part 1) according to the embodiment;
It is a flowchart.

FIG. 30 is a diagram illustrating a reboot process (part 2) according to the present embodiment;
It is a flowchart.

FIG. 31 is a flowchart of online initial processing (part 1) in the embodiment.

FIG. 32 is a flowchart of online initial processing (part 2) in the embodiment.

FIG. 33 is a flowchart of an online initial process (part 3) in the embodiment.

FIG. 34 is a flowchart of a maintenance process (part 1) in the embodiment.

FIG. 35 is a flowchart of a maintenance process (part 2) in the embodiment.

FIG. 36 is a flowchart of a maintenance process (part 3) in the embodiment.

FIG. 37 is a flowchart of a program load process (part 1) in the embodiment.

FIG. 38 is a flowchart of a program load process (part 2) in the embodiment.

FIG. 39 is a flowchart showing a memory layout creation process in the embodiment.

FIG. 40 is an explanatory diagram showing a memory arrangement after memory creation in the present embodiment.

FIG. 41 is a flowchart illustrating an example of a start-up process according to the embodiment;

[Explanation of symbols]

11: ROM IPL, 12: hardware control interface, 13: ATA card control interface, 14
... CPU, 15 ... Basic RAM, 16 ... Expansion RAM-1,
17: Additional RAM-2, 40: Basic ATA card, 60
... Option ATA card, 211 ... Work and operation data backup area, 212 ... Basic program area, 213 ... Variable RAM area.

Claims (7)

[Claims] 1. A method for controlling a plurality of functions to be realized by a program, comprising: selecting a plurality of option programs in accordance with a user's selecting operation; Is set in a memory, and a function corresponding to each option program is realized by executing the plurality of selected option programs. 2. The program control method according to claim 1, wherein, when the option program is selected, option selection information indicating all of the option programs to be selected according to the user's selecting operation is generated. Based on the generated option selection information, the selected plurality of option programs are arranged in the memory, and when the memory area is set on the memory, based on the option selection information, Calculating a maximum memory capacity of a data configuration necessary for operation of each of the selected option programs, and, according to each of the calculated maximum memory capacities, the memory area corresponding to each of the plurality of selected option programs; A program characterized by being arranged on the memory Your way. 3. The program control method according to claim 1, wherein the memory is a first RAM, and a memory area required for operation of the selected option program is a partial area of the first RAM. A program control method, wherein the program control method is arranged in a computer. 4. The program control method according to claim 2, wherein the memory includes one or more Rs in addition to the first RAM.
AM can be added, and the memory is one or more RAMs in addition to the first RAM.
When the additional RAM is added, the memory area necessary for the operation of the selected option program is the first RAM.
A program control method, wherein the program control method is arranged in a partial area of the RAM and in an entire area of the added RAM. 5. The program control method according to claim 1, wherein a capacity of the memory is smaller than a memory capacity required for operation of all selectable optional programs. 6. An apparatus that includes an arithmetic processing unit and a memory unit and realizes a plurality of functions by causing the arithmetic processing unit to execute a plurality of option programs. Selecting means for selecting, the selected plurality of option programs, and a data configuration required for operation of the plurality of option programs,
An apparatus using a program control method, comprising: a memory arranging unit arranged in the memory unit. 7. An apparatus according to claim 6, wherein said realizable function includes at least one of a telephone billing function and a traffic data collection function.