JP2002132376A - Computer system for automatically selecting service voltage and frequency - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically select a service voltage and an operation frequency in a computer system. SOLUTION: This computer system is provided with a voltage-controlled oscillator for generating a clock signal, a processor for receiving the clock signal and a power source for feeding a variable service voltage for operating the computer system, the voltage-controlled oscillator outputs a signal whose frequency changes within a prescribed range in accordance with the change of the variable service voltage, and the frequency changes at a rate that is larger than the rate of the change of the variable service voltage to the voltage- controlled oscillator.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer power system, and more particularly, to a computer system that automatically selects a voltage to the computer system and that is based on current requirements of the system or control signals from the computer system. The present invention relates to a computer power system for automatically selecting an operating frequency of a computer.

[0002]

2. Description of the Related Art Currently, portable computers have a limited operating time before the battery in a system is exhausted. Typical portable computers known to date operate at a single voltage, typically 5V, and
Uses a fixed frequency system clock. A major drawback is that these computers do not have the features to reduce battery load and extend operating time. C
In a typical semiconductor circuit device using a MOS semiconductor device, the power consumed by the system is expressed by the following equation.

Since the capacity of a P = CV ² F system is variable and cannot be adjusted by the designer, the variables that can be changed are system voltage and operating frequency. Computer systems that include a clock having one or more frequencies are known in the art,
The variable frequency clock is used as a function of the operation mode, and does not correspond to the average use within a certain time. In a conventional system, if the power supply could not supply the required voltage for high frequency clock operation, the data in the system would be lost, because the clock would be higher than its maximum frequency. This is because they cannot operate at low frequencies and, even if low voltages are possible, they cannot operate at that low supply voltage. Further, in the conventional system, it is impossible to give a relationship between a continuous voltage and a system clock frequency that the system clock changes based on a voltage that can be continuously supplied.

[0004]

SUMMARY OF THE INVENTION The present invention relates to power systems and oscillators for use with a computer, the computer system being minimally required to perform the functions of the system, and secondly reducing the power consumption of the system. It also functions to provide an operating voltage for the system to reduce the frequency of the system clock to reduce.
In addition to reducing power by lowering the voltage and frequency, the use of a variable frequency oscillator to supply the system clock signal causes the supply voltage to be typically required to perform the computational tasks of the system due to the heavy load on the system Even in an environment where the value is lower than the required value, the frequency of the oscillator can be changed as a function of the system supply voltage, and a danger preventing means for saving the system data can be provided.

[0005] The present invention discloses a power system and an oscillator for use in a computer system, which computer system is described and claimed in co-pending patent applications. And entitled "Portable Low Power Computer," filed Jun. 30, 1989, filed on Jun. 30, 1989, and whose agent's docket number is M-96.
8 For the convenience of those reading the present invention, reference numbers used in the above-mentioned co-pending applications are used correspondingly in this application.

For certain tasks, such as word processing, accomplished by a computer system, it is possible to operate the system clock at a lower clock speed than that required for the computational task. Similarly, in a word processing operation, circuits in the system can be operated at a voltage lower than the voltage required when the operation is performed. By operating at such a low clock frequency and low voltage, the performance of the system is not reduced as much as the user expects, and the power consumption is reduced. Similarly, if the system clock is operated at a lower frequency, the devices used in the system are also operated at a lower voltage, which means that at lower voltages, switching at lower frequencies is not possible. Because it is enough. For example, in the above-mentioned co-pending patent applications which use the invention and which are described and claimed in the appended claims, a computer system for processing information in a word processing mode of operation. ,
It has been found that almost full performance is achieved using a VDD of about 3 V and a system clock frequency of 2.3 MHz. However, when the operation mode of the computer includes calculation of numerical data, it is desirable to execute the calculation function quickly in most situations. Therefore,
In the operation mode, the power supply output changes from 3 V to 5 V, and the frequency of the system clock changes from 2.3 MHz to 6.6 MHz. Under these conditions described below, the highest speed processing is achieved. As described above, by using a variable frequency oscillator for generating a clock signal (hereinafter, a variable frequency oscillator for generating a clock signal is referred to as a VCO (Voltage Controlled Oscillator)), the system power supply is The computation frequency can be increased, as well as protecting data when the required power cannot be supplied or when the battery is discharged to an amount sufficient to degrade system performance. The VCO includes circuitry for achieving a reduction ratio at the operating frequency that is greater than the reduction ratio at the supply voltage. For example, if the frequency of the VCO at 5 V is 6.6 MHz, at 3 V, the operating frequency of the VCO is expected to be 3.96 MHz, assuming that the reduction ratio in frequency is the same. However, it is known that further power savings may be achieved by providing greater reduction rates, the preferred rate being V, as previously mentioned.
The DD is 3 V and the frequency of the VCO is 2.3 MHz. Under these conditions, the formula P = CV ² F reduces power consumption by approximately 3: 1 by changing the voltage from 5V to 3V, and reduces the frequency from 6.6MHz to 2.3MHz. To achieve further power savings, which is another factor in reducing power from about 3 to 1. Therefore, by combining these well, the power can be reduced to about 8: 1.

[0007] In the present invention, the power system is provided with a supply voltage (V
DD) operates in an automatic mode where it is either 3 or 5 volts, or operates in an override mode, which is independent of the magnitude of the current drawn by the computer system, Is limited by the processor of the system, which is regulated to the 5V limit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a power system having a plurality of outputtable voltages and a clock of a processor having a variable frequency. To allow operation of the system feasible at the lowest voltage and frequency based on

A further object of the present invention is to provide a condition in which the battery voltage drops, that is, a situation in which the system is required to operate without loss of data, and the supply voltage cannot be maintained due to excessive system load. At
In order to keep complete data, the operating frequency of the processor is reduced by changing the frequency of the VCO.

[0010]

According to the present invention, there is provided a computer system comprising processor means for receiving a clock signal, and a voltage controlled oscillator for generating a clock signal, wherein the voltage controlled oscillator is variably supplied. Receiving a voltage and providing an output signal whose frequency varies within a predetermined range in response to a change in the variable supply voltage, wherein the frequency varies at a rate greater than a corresponding rate of change in the supply voltage. Is provided.

According to the present invention, an automatic voltage selection override circuit is responsive to a control signal from a computer system to limit a supply voltage to a predetermined maximum value regardless of the current drawn by the computer system. Give as.

Also, according to the present invention, the supply voltage increases with increasing ambient temperature, and the device is maintained in a circuit to operate efficiently so that the resistance increases with increasing temperature. Such a temperature compensation circuit is provided.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a power system 13 of the present invention is schematically illustrated. For simplicity, the power system 13 is shown in a section surrounded by a broken line in the figure. Function blocks. The supply voltage VDD produced by the power system 13 is used through the computer system and, as described above, is set to 3V based on the requirements of the computer system or based on the voltage selection control from the computer system supplied to the line SELVDD.
And a voltage of 5V. Lines SELVDD, LOW BAT / DEAD BAT, and BATMON shown near reference numeral 17 in the lower right portion of the drawing are control lines from the computer and indicate status to the peripheral ASIC of the computer system. The lines are illustrated in the co-pending patent applications set forth above. Control by SELVDD from the computer system is used to place the power system 13 in either an automatic mode for establishing the value of the supply voltage VDD or a forced override mode. The operation of this power system will be described in detail hereinafter, but first, the LO on the SELVDD line is
W (LOW indicates ground) defines the magnitude of VDD at approximately 5 V, and the power system
It will be adjusted to keep DD at that level. The next state of SELVDD is a state in which an automatic operation in which the size of VDD is automatically determined is given. That is, the output of VDD at 3V or 5V depends on the current drawn by the system described above, and this automatic mode is achieved by forcing SELVDD to float or VDD state. When SELVDD is floating or VDD, the output will be 3V or 5V depending on the amount of current drawn by the system. In most situations, it is desirable for the system output voltage (VDD) to be 3V. However, a desirable parameter for changing VDD from 3V to 5V is that the current demand of the system is 10 mA.
In addition to the above, it is known that the level at which this current flows lasts approximately 500 ms.

The BATMON line is used to control the operation of the battery status monitoring portion of the power system. The power source for the power system is a battery BT1, preferably two AA alkaline batteries with an initial output of approximately 3V. When the battery voltage drops to 1.8V, LOW
A low battery indicator is provided on the BAT / DEAD BAT line, and when the battery voltage drops to 1.6V, L
An indication of battery drain is provided to the system through the OW BAT / DEADBAT line.

The battery exchange backup circuit shown in the broken line on the right side of FIG. 1 serves as a voltage supply when the battery is exchanged. The operation of this battery exchange circuit will be described later. The rest of the power system 13 has a voltage selection section and a supply voltage generation section.

[0016] the supply voltage generating section, the cathode is connected to ground, there is a battery BT1 to the anode is connected to the line V _{BA TT.} In the supply voltage generating section there is a bipolar transistor T1 whose emitter is connected to V _BATT and whose collector is further connected to a resistor R18, which is further connected to a resistor R15 which is connected to ground, but which is connected to one terminal. . A set of switching transistors T2 and T3 are connected in parallel for the current handling process, each one of their emitters connected to ground,
Their collectors are connected together, and their bases are connected together and connected to the junction between resistors R18 and R15. In the first current path of the transistors T2 and T3 is a coil L1, one terminal of which is connected to the commonly connected collector of the transistors T2 and T3;
The other terminal is connected to the V _BATT line. Feedback between the collectors of transistors T2 and T3 and the base of transistor T1 is provided by a first circuit including a capacitor C23, a resistor R16 and a Schottky diode D1.
This is accomplished by a second circuit containing zeros. The Schottky diode D10 is, for example, a part number HP-5 of a Schottky diode manufactured by Hewlett-Packard Company.
082-2810. The resistor R22 is a transistor T
1 is a connection path from the base to the ground. Schottky diode D9 is connected between nodes N4 and N1. The supply voltage circuit of the power system 13 performs a DC-DC conversion of the voltage from the battery BT1, this conversion comprising transistors T1, T2 and T3, together with its feedback circuit, which switches ON and OFF. Is achieved by its function as an oscillator. The energy stored in the conducting coil L1 is converted to a DC voltage by rectification through the diode D9 when the transistors T2 and T3 are turned off by switching operation. The resulting D
VDD is generated at the node N1 due to the storage of the C potential. The operation of this supply voltage section will be described in more detail later in the schematic description of power system operation. In practicing the present invention, the aforementioned supply voltage circuit regulated by the on-off regulation method described later is used as a preferable circuit for generating the supply voltage (VDD). However, other types of supply voltage generation circuits are used in the practice of the present invention, for example, circuits such as linear series regulators. An example of this latter type of circuit is the National
Semiconductor 3-terminal regulators are possible, part numbers LM117, LM217, and LM317.

Returning to the voltage selection section shown in FIG. 1, this section regulates the voltage as well as the voltage selection. As noted earlier, this voltage selection is
It is performed automatically by the amount of current supplied to the system through the D line, or is set to a predetermined level according to a control signal on the line SELVDD. In the present invention, the supply voltage circuit is satisfied by the use of a converter that performs DC-DC switching, and the magnitude of the current supply to the system is detected based on the duty cycle of the oscillator in the supply voltage circuit. You. It should, of course, be appreciated that the present invention may be implemented by using a supply voltage circuit apart from switching and supplying DC to DC. The voltage selection section is also illustrated on an enlarged scale in FIG. 4, and with reference to FIG. 4 in addition to FIG. 1, a description of circuit operation as well as interconnection with the rest of the power system 13 will be provided. It will be easier to understand. Determine the supply voltage VDD,
And to establish a reference point for defining
By connecting 13 between V _BATT and node N3 and connecting zener diode D6 between node N3 and ground, a reference voltage is generated at node N3. As shown in FIGS. 1 and 4, the anode 1 of the Zener diode D6 is connected to the ground, and the cathode 2 of the Zener diode D6 is connected to the node N3. It is known that it is advantageous to use the part number LM385 for the diode D6 as a 1.2V band reference diode manufactured by Motorola, and if this is used, a potential of 1.2V is applied to the node N3. Is given. The current limiting resistor R13 preferably has a value of 100 KΩ. Node N3 is connected to the non-inverting input of comparator U5A. The inverting input of comparator U5A is connected to node N2. Voltage division operation, current flow to computer system, and SEL from computer system
Node N established by control signal through VDD
2 determines the voltage level, which in the preferred embodiment of the power system is 3
Or 5V to regulate VDD to achieve either. Resistor R12, preferably 270
KΩ is connected between VDD and the node N2. The diode D11 has its anode 3 connected to the node N2, its cathode 4 connected to one terminal of a resistor R11 which is preferably 75 KΩ), and
The other terminal 11 is connected to the ground. The diode D11 is, for example, an IN914 silicon diode manufactured by Motorola, and its part number is MMBD914.
L. Diode D11 serves to provide temperature compensation for the power system, which will be described more fully hereinafter. The resistor R21 is connected between the node N2 and the node N5, and the resistor R10 is connected between VDD and the node N5. Capacitor C26 has one terminal connected to node N5, and the other is connected to ground. A resistor R19 (preferably 6.2 KΩ) is connected between the node N5 and the node N6.
A capacitor C22 having a capacitance of 0.1 μf is connected between the ground and the ground. Diode D13 (which may be of the same type as diode D11) has its cathode 5 connected to control line SELVDD and its anode 6 connected to node N5. Diode D1
3 is forward biased when a ground level is applied to its cathode 5 via line SELVDD,
The resulting voltage level at node N5 regulates VDD to 5V regardless of the current drawn by the computer system. How this is achieved will be fully explained in the description of the operation of the voltage selection circuit.

To indicate the level of current drawn by the computer system, a resistor R19 (6.2 KΩ) connected between nodes N5 and N6, and its anode 7 connected to node N6 and its cathode 8
Schottky diode D1 connected to node N4
4, and a new circuit comprising a capacitor C22 (0.1 μf) connected between node N6 and ground is provided in the voltage selection section, and the indication of the magnitude of the current is provided by the computer through the supply voltage line VDD. Supplied to the system. The Schottky diode D14 is, for example, a Schottky diode manufactured by Hewlett-Packard Company and has a part number of HP-5082-2810,
The Schottky diode D9 is, for example, a part number SGL41-30 of a Schottky diode manufactured by General Instruments.

The comparator U5A operates to determine the on / off switching of the oscillator in the supply voltage circuit. The output of comparator U5A is connected via line 9 to a resistor R17 (30 KΩ) which is connected to the base of transistor T4. The emitter of the transistor T4 is V
Connected to the _BATT line, the collector of which is connected to the base of transistor T1 in the supply voltage circuit. The pull-up resistor R14 is connected between the V _BATT line and the base of the transistor T4. The transistor T4 is, for example, a part number MMPQ6700 manufactured by Motorola. The need to provide an oscillator in the supply voltage circuit of the power system 13 that generates a DC voltage at node N1 to maintain the supply voltage line VDD at a specified value is due to the inverting and non-inverting inputs of the comparator U5A. It is determined by the comparison voltage at nodes N2 and N3 respectively connected. The output signal on line 9 from comparator U5A controls the conduction of transistor T4, and the collector voltage of transistor T4 determines whether transistor T1 is conductive or non-conductive. In short, when the transistor T4 is turned on, the transistors T1, T2 and T3 of the supply voltage circuit
Becomes non-conductive and the converse applies correspondingly, ie, if T4 is non-conductive, the transistors T1, T2
T2 and T3 become conductive and current flows through coil L1. When the transistors T2 and T3 are turned off, the energy stored in L1 is released through the Schottky diode D9, rectified by this diode and the supply voltage VDD is generated and stored in the capacitor C24. Details of the operation of this circuit will be described later.

A battery condition monitor circuit (shown in FIG. 1) to help ensure that system data is not lost when the battery charge condition is low and to alert the user to a low battery condition Are included in the power system 13. The battery condition monitor includes a comparator U5B, which is connected to its inverting input via a resistor R29.
ASIC around the computer system through the line
Receives control signals from From the output of comparator U5B, a signal is output on the LOW BTA / DEAD BAT line, which is provided to the computer to notify the battery of a low or depleted battery status detected by the battery status monitor. The V _BATT line is connected to the inverting input of the comparator U5B through the resistor R26, and the resistor R
The junction between 26 and R29 is connected to ground through a resistor R27. Power to comparator U5B is provided by conductive line 10 that connects VDD to the power input terminal of comparator U5B. The comparator U5B is of course connected to ground, but this connection is not shown. The feedback resistor R28 is connected between the LOW BTA / DEAD BAT line and the conductive line 10. The operation of the battery condition monitoring circuit will be described in the following description of the overall operation of the power system.

To power the system so that operation continues during the replacement of a weak or depleted battery, a battery replacement backup circuit is provided in the right portion of FIG. The battery replacement backup circuit includes a diode D8 whose anode 12 is connected to the VDD line and whose cathode is connected to one terminal of the capacitor C21. Capacitor C
The second terminal 21 is connected to the ground. This capacitor C21 is preferably 0.047 farads. Capacitor C21 stores charge and serves to provide an operating potential to the system when the battery is removed. Another circuit of this battery replacement backup circuit includes a diode D7 and a transistor T5. The cathode 15 of the diode D7 is connected to the VDD supply line,
The anode 16 of the diode D7 is connected to the emitter of the transistor T5. The base and collector of transistor T5 are coupled together and connected to the junction of the cathode of diode D8. Transistor T5, of course, functions as a diode and is conveniently used in place of a regular diode because transistor T5 is convenient to use as part of a pack of multiple transistors. It goes without saying that a normal diode of the same type as the diode D7 or D8 can be used instead of the transistor T5. Diodes D7, D8, D11 and D13 are Motorola IN914 silicon diodes with part number MMBD
It is convenient to use 914L. The operation of the battery replacement backup circuit will be described later in connection with a description of the operation of the system.

As mentioned earlier, one of the fundamental features of the present invention is the use of a system clock whose frequency decreases in response to a decrease in the supply voltage to the system, and in particular, the system clock frequency. Is reduced at a greater rate than the voltage. This achieves a further reduction in power consumption when slower system operating speeds can be tolerated at lower clock speeds in certain types of operations, for example, operations such as word processing. Attention is now directed to FIG. 2A, where the circuit for the system clock circuit 18 is:
It is depicted with an oscillator circuit 19 providing a second oscillator for the computer system. Oscillator circuit 19, however, is designed such that its frequency does not substantially change with changes in the supply voltage. However, as shown in the graph 2E of FIG. 2, the output frequency of the system clock circuit 18 becomes 2.3 MHz when the supply voltage VDD supplied to the system changes from 3V to 5V.
From 6.6 MHz to 6.6 MHz. This change in frequency is achieved by the feedback circuit. Paying attention to the system clock circuit 18, the NAND gate 24,
This is, for example, a two-input NAND gate manufactured by Texas Instruments with part number 74H132 (or similar NAND gate with Schmitt trigger input).
Whose output is connected to node N24 to provide an oscillating output to circuitry internal to the system. The feedback circuit from the node N24 includes a parallel circuit of a diode and a resistor. In particular, the resistor includes a resistor having a first terminal connected to the node N24 and a second terminal connected to the cathode 20 of the diode D22. R22
(This is, for example, 1.8 KΩ). The anode 21 of the diode D22 is connected to the cathode 22 of the diode D21, the anode 23 of the diode D21 is connected to one terminal of the capacitor C22, and the common connection between the anode 23 (of the diode D21) and the capacitor C22. The part is NAN by the conductive wire 25
It is connected to the X input of D gate 24. Node N24
A second parallel feedback circuit between the input and the input X of the NAND gate 24 includes a resistor R23 (preferably 820Ω) having one terminal connected to the node N24. The other terminal of the resistor R23 is connected to the anode 26 of the diode D24, the cathode 27 of the diode D24 is connected to the anode 28 of the diode D23, and the cathode 29 of the diode D23 is connected to the node N25. . Diodes D21, D22, D23,
And D24 are, for example, Motorola IN914 silicon diodes with part numbers MMBD914L. The capacitor C22 adjacent to the system clock circuit 18 is preferably 47 pf to achieve a frequency range from reduction to the end of the wide range, as shown in the frequency voltage graph.

The oscillation circuit 19 is the same as the old design,
Even if the value of the supply voltage changes, the frequency is substantially constant. In the computer system in which the invention is used, the oscillating circuit 19 represents a fixed frequency oscillator, such as the display system used in the display system described in the previously mentioned co-pending patent application. It can be a data clock. NAND gate 3
0 is the NA in the system clock circuit 18, for example.
The same type as the ND gate 24 may be used. The output of NAND gate 30 provides a relatively fixed frequency of approximately 830 KHz at its output terminal (node N21). Feedback from the output to the input of circuit 19 is provided by coupling node N21 to node N22 with a resistor R21 (having a resistance of approximately 24 KΩ). Node N22 is connected to input A of NAND gate 30 by conduction path 31. Capacitor C21
Has a capacity of approximately 47 pf and has a node N2
2 and ground. The ENABLE1 line is connected to the NAND gate 30, and the ENABLE1
This allows the oscillator to operate because the E2 line is connected to NAND gates 24 and normally provides these gates with an enable function. Graphs 2D and 2E of frequency and voltage for the system clock circuit 18 and the oscillation circuit 19, and graph 2 of the waveform of the oscillator
B, 2C are drawn adjacent to these circuits. Circuit Operation The operation of the power system 13 shown in FIG. 1 will be described hereinafter, but here, the circuit has not previously operated, and the battery BT1 is first mounted on the circuit, and the voltage of V _BATT is applied to the circuit. It is explained under the assumption of supply. Battery B under the assumption that the circuit has not previously operated
When T1 is mounted, the voltage at node N3 rises and stabilizes at 1.2V, which is the reference voltage used in various sections of the system. This voltage exceeds the voltage at node N2 because the DC voltage VDD has not previously developed in the supply voltage section. Therefore, the output of comparator U5A, which is connected by line 9 to the base of transistor T4, causes transistor T1 to be biased to start operating and to oscillate the oscillator of the supply voltage section. This operation is started by turning on the transistor T1, so that the current flowing through the base-emitter of the transistor T1 flows into the resistor R22, which is a startup resistor. Transistor T1 supplies current to the bases of transistors T2 and T3 through resistor R18. Thereby, the transistor T2 is instantaneously
And the collector voltage of T3 drops, turning on these components. Due to this voltage drop, the AC circuit through the capacitor C23 conducts, and the DC circuit including the resistor R16 and the diode D10 also conducts. Transistor T
2 and T3 remain on until the current through coil L1 is large enough to saturate transistors T2 and T3. This causes the voltage at the collectors of T2 and T3 to increase, and this increased voltage causes the resistance R1
6. The current flowing between the diode D10 and the emitter-base of the transistor T1 decreases. Also, T2 and T
3 causes the capacitor C to rise.
23 increases the current through transistor T1
The base current passing through is further reduced. Then, T1 is turned off, and by this turn-off, the transistors T2 and T3 are similarly turned off. Resistor R15 acts as a shunt to ground, and connects the bases of transistors T2 and T3.
Helps discharge between emitters and speeds up the turn-off process. The rapid charging of the current through coil L1 causes the voltage at node N4 to rise, which in turn biases diode D9 forward and charges capacitor C24. When the coil L1 discharges,
The voltage at node N4 drops, which causes transistor T1 to be retriggered and a new process to begin. This circuit operates as a free-running oscillator, and the capacitor C
It will be seen that 24 continues to charge and the voltage at C24 increases until voltage regulation is performed via the voltage selection circuit. That is, when the voltage regulation point is reached, the output of the comparator U5A becomes low, and the transistor T4 is turned on through the resistor R17. This raises the base of transistor T1 to near V _BATT, preventing transistor T1 from turning on. By turning off the transistor T1, the transistors T2 and T3 are also turned off, and the oscillation operation stops.

A voltage selection circuit, which is shown in greater detail in FIG. 4, is used to divide the supply voltage (VDD) generated at node N2 and applies the voltage generated at node N2 to node N3. Compare with reference voltage. Resistance R1
3. Zener diode D6 and capacitor C25
Generates a reference voltage of about 1.2V. When the voltage at the inverting input of comparator U5A exceeds the reference voltage (ie, when V _N2 > V _N3 ), the output transistor in comparator U5A (shown in FIG. 4) turns on. When the output transistor of comparator U5A turns on, transistor T4 turns on, which turns off the free running oscillator, as previously described. When the voltage on the VDD line is high (meaning that VDD has reached the required voltage), the oscillator of the supply voltage circuit does not oscillate, and the voltage at node N2 is reduced by the resistors R10, R12, And R21, diode D1
1 and a resistor R11. This equivalent circuit is shown in FIG. At low current levels, the voltage drop across diode D11 is about 0.4V. Diodes are used here to provide temperature compensation in power systems rather than resistors. By placing diode D11 in this position in the circuit, the diode voltage changes by -2.5 mV / ° C with temperature change, and 0.2% / ° C positive going no matter what voltage is selected. Temperature compensation. The temperature fluctuation due to this compensation is about half of the temperature fluctuation in the CMOS circuit. The voltage at node N2 is made equal to the voltage at forced node N3 (FIG. 1) by a free running oscillator in the feedback loop. Therefore,
The potential difference at the resistor R11 is about 0.8V. Another circuit of the voltage divider is formed by resistors R10 and R21 connected in series, this circuit being connected in parallel with resistor R12. This circuit is equal to about 140Ω between node N2 and the supply voltage VDD (shown in FIG. 5 as _REAUIVALENT ). By Ohm's law and Kirchhoff's law,
The voltage between VDD and node N2 is equal to about 1.5V.
Thus, the total voltage at VDD is equal to about 2.7V (since node N2 is equal to 1.2V). In practice, this voltage will be close to 3V. The equivalent circuit assumes a duty cycle of zero. This duty cycle is actually very low, but never goes to zero,
Thus, the voltage never reaches 2.7V.

In FIG. 5, the equivalent circuit for N2 is drawn for low current / low duty cycle operation of the supply voltage circuit. Higher currents are required in digital systems and, as a result, different equivalent circuits for node N2 have been established for the oscillator of the supply voltage circuit to operate most of the time. This equivalent circuit is shown in FIG. Due to the high current demands of the digital system, when the oscillator of the supply voltage circuit operates for most of the time, the voltage on the capacitor C22 is clamped very close to 0.2V by the Schottky diode D14, This is because the anode is at about 0.2 V with the cathode connected to ground. This relationship also exists when transistors T2 and T3 are conducting, of course, because their collectors are essentially ground. As a result of the foregoing, the circuit is essentially clamped, sampled, or held, which is the method used to detect current in the system. Since the time ratio at which the oscillator of the supply voltage circuit operates is directly proportional to the current supplied by the power system 13, the voltage on the capacitor C22 can be adjusted in this manner, as if a directly connected current sensing device were used. Provides an accurate indication of whether the current being detected is reducing the load on the power system. Resistor R19 and capacitor C26 essentially function as a filter that averages the voltage on capacitor C22 and provides a time delay in the process. As the digital system continues to draw high current for about 1/2 second, the power supply (VDD) changes to a high voltage setting. Since this change occurs as a result of a positive feedback process, it occurs very quickly. An increase in the power supply (VDD) increases the output frequency of the VCO circuit, thereby increasing the amount of current drawn, thereby causing an increase in VDD and the like. The arrow near the resistor in FIG. 6 indicates the direction of current flow when a high load condition exists. The equations shown below illustrate the approximate high VDD voltage operation through the current solution at nodes N2 and N5.

[0026] Substituting V _N5 into the equation for node N5, VDD = 17.47 (.48)-3.64 VDD = 4.74 (V) In practice, VDD is close to 5V, which is the voltage of the coil. This is because the node N4 becomes slightly lower than the ground potential due to the “ringing” of the coil that occurs when is inverted. Thereby, C22 becomes. VDD is clamped to a voltage lower than 2V and VDD rises slightly.

FIGS. 3A and 3B show the on / off switching of the supply voltage circuit, a preferred scheme of which is shown in FIG.
B. The technique shown in FIG. 3B would be evaluated in relation to the load conditions, but with a large number of pulses given per unit time that varies depending on the magnitude of the load,
The oscillator is switched between on and off by using pulses of equal width. In contrast to this,
A typical scheme used in the prior art is shown in 3A, where a base current to a switching transistor is input to its base to turn on the transistor and effectively provide pulse width modulation. It changes based on the current flowing.

As mentioned above, the detection of the required current is accomplished by connecting the cathode 8 of the diode D14 to the collectors of the transistors T2 and T3; however, in another possible embodiment, as shown in FIG. The connection of the cathode 8 to the node N24 of the system oscillator 18 so that the oscillator operates with the cathode 8 operating on a large current demand and that a high supply voltage (VDD) is desired. Connected to a low voltage level logic signal. This is advantageous when using a single system oscillator that is switched on and off. However, in situations where many oscillators are turned on or off, it is desirable to use the configuration shown in FIGS. The capacitor C22 shown in FIG.
If a circuit is used connected to 24, adjustment is necessary, and its capacitance will decrease in a decreasing direction due to the higher frequency of the system oscillator (higher than the switching frequency of the oscillator in the supply voltage circuit). It is possible to reduce to. In the above example, it is assumed that the SELVDD line is either floating or VDD, which causes the system to operate automatically to achieve 3 or 5V based on the current drawn. In some situations, it may be desirable for the supply voltage to be locked at about 5 V, regardless of the current requirements of the digital system, which is achieved by providing an automatic voltage selection override circuit. To accomplish this, SEL
The VDD line is connected to the ground, so that the power supply V
DD is forced to about 5V. In system operation, this SELVDD line is connected to a tri-state CMOS output device in the peripheral ASIC of the computer system, which is also shown in FIG. 4 and also in FIG. The SELVDD line is pulled to ground when a high voltage is desired. In particular, FIG.
When the SELVDD line is connected to the ground, the voltage drop through the diode D13 is such that when the cathode 8 of the diode D14 is at a low level, the diode D14 is a Schottky diode and the diode D13 is a silicon diode. It will be understood that the voltage drop across resistor R19 and diode D14 is approximately the same as the voltage drop that occurs in automatic operation for large current demands.
In both the automatic mode and the override mode of operation, node N5 reaches approximately 0.4 to 0.5V, thereby selecting a higher voltage through either SELVDD control or current sensing through resistor R19 and diode D14. Will be.

Referring to FIG. 1, it will be recalled that the system includes a battery status monitor section that provides an indication of the relative charge status of the battery. The battery voltage is sensed by a voltage divider consisting of resistors R26 and R27, which voltage is connected by lead 32 to comparator U2.
Compared to the reference voltage from node N3 connected to the non-inverting input of 5B. The initial state of the line BATMON has its input connected to ground, which results in the resistor R2
6, R27 and R29 form a voltage divider, the common terminal of which is connected to the inverting input of comparator U5B. After a low battery voltage condition is detected, BAT
The MON line goes open, the voltage level at node N8 changes, causing the comparator to go low. This makes it possible to find the level of the depleted state of the battery in the same way as searching for the low battery state in the same circuit. When the level of the battery depletion state is detected, LOW BAT / DEA
The output of the T BAT line prevents data transfer in the system by providing an interrupt signal to the peripheral ASIC chip, which has the docket number of the agent entitled "Computer Power Management System" with M-9.
24, and co-pending patent application Ser. No. 07 / 373,440, filed Jun. 30, 1989. This safety measure is used together when the VCO oscillator is reduced to a lower operating frequency such that the 5V level cannot be achieved even with the current demands of the system. In such a situation, the supply voltage VDD is 5
V, the system clock frequency, which is generated from the system clock circuit 18, but is lowered,
Prevent any loss of data processed by the system.

In connection with the operation of the battery exchange backup circuit shown in FIG. 1, during operation of the system, the capacitor C21 is charged to a level that is one diode drop below the level of the supply voltage VDD. If the voltage drop of the supply voltage VDD is very large, for example, when the battery is removed for replacement, the capacitor C21 is lower than the terminal voltage of the capacitor C21 by the voltage drop of the two diodes. A voltage is supplied to maintain the supply voltage VDD. If the supply voltage VDD continues to operate at 5V, when the voltage level of the supply voltage VDD becomes lower than about 3.5V,
Capacitor C21 starts supplying the backup supply voltage to the supply voltage VDD line. To adjust to these voltage levels described above, directly connected diodes may be added, or no diodes may be used. To optimize the performance of the system, the software of the system includes an instruction to instantly increase the supply voltage VDD to 5 V each time the system is turned off, thereby maximizing the charge on the diode. , Capacitor C21. In addition, the user has been instructed to turn on the unit before replacing the battery, and then to turn off, so that the system provides a potential up to 5V within the maximum discharge time of capacitor C21 until the battery is removed. Is guaranteed.

The foregoing is illustrated in the present invention. However, many applications and modifications will occur to those skilled in the art by practicing the invention without departing from the spirit or scope of the invention. It goes without saying that the invention is not limited by the above description, but only by the claims.

[Brief description of the drawings]

FIG. 1 is a diagram showing a power system.

FIG. 2 illustrates a typical oscillator used with a computer system.

FIG. 3 shows ON / OFF of a supply voltage generator of a power system.
It is a figure showing a waveform to switching of OFF.

FIG. 4 is an enlarged circuit diagram of a voltage selection circuit of the power system.

FIG. 5 is a diagram showing an equivalent circuit of a voltage selection unit of the power system for operating the power system at a low current.

FIG. 6 is an equivalent circuit diagram of the same portion of the voltage selection circuit shown in FIG. 5 under high current and high voltage conditions.

Continued on the front page (72) Inventor Euan, Andy Sea. USA, California 95070, Saratoga, Solana Drive 19682 F-term (reference) 5B011 DB03 LL02 LL13 5B079 BA04 BC01

Claims (11)

[Claims] 1. A computer system, comprising: processor means for receiving a clock signal; and a voltage controlled oscillator for generating the clock signal, wherein the voltage controlled oscillator receives a variable supply voltage and the variable supply voltage Providing an output signal whose frequency changes within a predetermined range in response to a change in the supply voltage, wherein the frequency changes at a rate greater than a corresponding rate of change in the supply voltage. 2. The computer system according to claim 1, wherein said voltage controlled oscillator has a non-linear voltage-frequency characteristic. 3. The computer system according to claim 2, wherein said non-linear characteristic is provided by one or two diodes in said voltage controlled oscillator. 4. The computer system according to claim 1, further comprising a power supply for supplying a variable supply voltage for operating the computer system. 5. The computer system according to claim 1, further comprising means for suppressing generation of the clock signal in order to suppress power consumption. 6. The computer system according to claim 1, further comprising a switching power supply regulator. 7. The computer system according to claim 1, further comprising an on-off switching power supply regulator. 8. A computer system, comprising: processor means for receiving a clock signal; and a voltage controlled oscillator for generating the clock signal, wherein the voltage controlled oscillator receives a variable supply voltage and the variable supply A computer system for supplying an output signal whose frequency changes within a predetermined range in response to a change in voltage, comprising: an input terminal and an output terminal; And the output terminal substantially reaches the supply voltage when the input terminal is substantially at the ground voltage and when the input terminal is substantially at the supply voltage. An inverting logic gate substantially reaching the ground voltage, comprising a first and a second terminal, wherein the first terminal is an input of the inverting logic gate. The second terminal is connected to the ground terminal, the second terminal is connected to the ground voltage, the second terminal is charged with the capacitor, and the second terminal is provided with an input terminal and an output terminal. Feedback means coupled to the input terminal of the inverting logic gate, and discharging the capacitor, comprising an input terminal and an output terminal, wherein the input terminal is the input terminal of the inverting logic gate. Feedforward means coupled to an input terminal and the output terminal coupled to the output terminal of the inverting logic gate. 9. The computer system of claim 8, wherein said inverting logic gate comprises a NAND gate having first and second input terminals, said first input terminal of said inverting logic gate. The input terminal is coupled to the second input terminal, the second input terminal being coupled to receive an enable signal. 10. A computer system, comprising: processor means for receiving a clock signal; and a voltage controlled oscillator for generating said clock signal, wherein said voltage controlled oscillator receives a variable supply voltage and said variable supply Providing an output signal whose frequency varies within a predetermined range in response to a change in voltage, wherein the rate of change of the frequency of the voltage controlled oscillator is greater than the rate of corresponding frequency change in the variable supply voltage by 0.
A computer system characterized by varying at a large rate exceeding three. 11. A computer system, comprising: processor means for receiving a clock signal; and a voltage controlled oscillator for generating said clock signal, wherein said voltage controlled oscillator receives a variable supply voltage and said variable supply Providing an output signal whose frequency changes within a predetermined range in response to a change in voltage, wherein the rate of change of the frequency of the voltage controlled oscillator is 1.
A computer system characterized by changing at a large rate exceeding zero.