JP2002124879A - D-a converter and semiconductor integrated circuit device with built-in d-a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a D-A converter capable of realizing a sufficient output voltage accuracy by suppressing a differentiated linear error in association with relative irregularity of a constant current circuit to a small value by preferentially using a constant current source circuit for a more significant bit. SOLUTION: At a node N1, another end of a switch S2 is connected to a constant current source circuit I2 one bit more significant, another end of a switch S4 is connected to a constant current source circuit I3 two bits more significant and another end of a switch S7 is connected to a constant current source circuit I4 three bits more significant. At nodes N2 and N3, the switches are similarly connected. At the node N2, switches S5 and S8 are connected to the circuit I3 one bit more significant and to the circuit I4 two bits more significant. At the node N2, a switch S9 is connected to the circuit I4 one bit more significant. These switches are controlled to be preferentially used from the more significant node and to be preferentially used from the constant current source circuit for the more significant node according to an internal control signal based on the input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter, and more particularly to an improvement in a monotonic increase in output voltage and a differential linearity error in a D / A converter.

[0002]

2. Description of the Related Art As shown in FIG. 1, a constant current input from a constant current source circuit I1, I2, I3, I4 to each node N1, N2, N3, N4 of an R-2R ladder resistor string RR. To the digital input signals DS1, DS2, DS34, DS
4 is used to obtain an analog voltage output by switching.

FIG. 1 shows a 4-bit input D / A converter. Each of the constant current source circuits I1, I2, I3, I4
(The output currents are I1, I2, I3, and I4.) And R2R ladder resistor including resistors R1 to R7 having resistance values of R1 = R2 = R4 = R6 = R7 = r and R3 = R5 = 2r. Switches S101, S103 controlled by digital signals DS1, DS2, DS3, DS4 input from 4-bit digital input terminals 1, 2, 3, 4 between nodes N1, N2, N3, N4 of column RR. , S10
6, the connection is made in S110. Here, the digital input terminal 1 (DS1) is the LSB, and the digital input terminal 4 (DS4) is the MSB.

Each switch S101, S103, S10
6, S110 is a digital signal DS1, DS2, DS3,
Assuming that conduction is performed by the positive logic of DS4, for the input of the digital input signal DS1 (DS1 = 1), the constant current from the constant current source circuit I1 flows into the node N1, but the configuration of the R-2R ladder resistor string RR Accordingly, the constant current input to the node N1 is divided by ３ and flows into the next stage (I1 · 1
/ 3), at nodes N2 and N3, the flow is halved,
Current flowing through the node N4, as the ^{(1/3) · (1/2) 2} · I1 = (1/12) · I1 becomes the output voltage Vo (DS1), Vo (DS1 ) = (1/12) · I1・ R ・ ・ ・ ・ ・ ・ ・ (1) Similarly, each digital input DS
For DS2, DS3 and DS4, Vo (DS2) = (2/12) · I2 · r (2) Vo (DS3) = (4 / 12) · I3 · r (3) Vo (DS4) = (8/12) · I4 · r (4) An output voltage Vo is obtained. Then, these are summed to obtain a D / A converted output for a 4-bit input: Vo = (1/12) · I1 · r · DS1 + (2/12) · I2 · r · DS2 + (4/12) · I3 · r · DS3 + (8/12) · I4 · r · DS4 ... (5) is obtained. Here, the digital input signals DS1, DS
2, DS3 and DS4 are binary signals of 1 or 0, and when they become 1, the switches S101, S103, S3
106 and S110 conduct.

By making the current weights of the constant current source circuits I1, I2, I3, and I4 all the same (I1 = I2 = I3 = I3
4 = i), each digital input signal DS1, DS2, DS
3, the output voltage Vo binary-weighted to DS4 is obtained. Vo = {(1/12) · DS1 + (2/12) · DS2 + (4/12) · DS3 + (8/12) · DS4} · i · r (6)

[0006]

However, in the above prior art, all the constant current source circuits I1, I2, I3, I
4 is the same (I1 = I2 = I3 = I4 = i), an output voltage Vo having a binary weight can be obtained. As is clear from the equation (5), each output current value Due to the relative variations of I1, I2, I3, and I4, the differential linearity error, which is the error of the output voltage Vo for each of the digital input signals DS1, DS2, DS3, and DS4, increases, and there is a problem that the monotonous increase characteristic deteriorates. .

The constant current source circuits I1, I to the output voltage Vo
2, the contribution of the output current from I3, I4 increases as the higher-order bit increases, so that the relative variation in the output currents of the constant current source circuits I1, I2, I3, I4 on the higher-order bit side increases. , The differential linearity error becomes large, and the digital input signals DS1, DS2, DS3,
There is a problem that the monotonic increase characteristic of the output voltage Vo with respect to DS4 is deteriorated. For example, if I1 = I2 = I3 = i, I4 = 0.875i (7), the digital input is changed from “0111” to “1000”
The change of the output voltage Vo when changing to is estimated. From equation (5), the output voltage for the digital input “0111” is given by Vo (0111) = (1/12) · ir · 1 + (2/12) · ir · 1 + (4/12) · i R · 1 + (8/12) · 0.875i · r · 0 = (1/12) · i · r + (2/12) · i · r + (4/12) · i · r = (7/12 ) · I · r · · · · · · · · (8)

The output voltage corresponding to the digital input “1000” is Vo (1000) = (1/12) · ir · 0 + (2/12) · ir · 0 + (4/12) · i · r · 0 + (8/12) · 0.875 i · r · 1 = (8/12) · 0.875 i · r = (7/12) · i · · · · ·・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ (9)

Therefore, from equations (8) and (9), Vo (0
111) = Vo (1000), ΔVo = Vo (1000) −Vo (0111) = 0 (10), and the differential linearity error becomes −1 LSB, and the input signal “0111” There is a problem that the difference in the output signal Vo between "" and "1000" disappears.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem of the prior art, and the relative current of the constant current source circuit is reduced by preferentially using the circuit for the upper bit as the constant current source circuit. It is an object of the present invention to provide a D / A converter capable of suppressing a differential linearity error due to variation to a small value, improving a monotonically increasing characteristic, and achieving sufficient output voltage accuracy.

[0011]

According to a first aspect of the present invention, there is provided a D / A converter comprising: an R-2R ladder resistor string in which a current is input to a node according to a digital input signal; In a D / A converter including a constant current source circuit provided for each of them and having a constant current weight, and a switch circuit for appropriately connecting the two according to a digital input signal,
2R, one end of which is connected to the same node of the
The above switch circuit is provided, and the other end of one switch circuit is connected to a constant current source circuit corresponding to the same node, and the other end of the other switch circuit is connected to a constant current source circuit corresponding to an upper node. It is characterized by the following.

In the D / A converter according to the first aspect, when a constant current is input to the node of the R-2R ladder resistor string with respect to the digital input signal, two or more switch circuits of one switch circuit and another switch circuit are provided. Since a switch circuit is provided, a constant current is input from a constant current source circuit corresponding to a node when one switch circuit is conductive, and a constant current source circuit corresponding to a higher node is provided when another switch circuit is conductive. A constant current is input.

According to a second aspect of the present invention, in the D / A converter according to the first aspect, two or more switch circuits are preferentially conducted from another switch circuit. I do.

In the D / A converter according to the second aspect, the constant current from the constant current source circuit corresponding to the upper node is preferentially input, so that the constant current input to the node is higher than that of the upper node. And supplied by a common constant current source circuit.

A D / A converter according to a third aspect of the present invention is the D / A converter according to the second aspect, further comprising two or more nodes having two or more switch circuits.
Which of the above switch circuits is to be rendered conductive is determined by priority from the upper node.

In the D / A converter of the third aspect, of the two or more switch circuits, the conduction of the other switch circuits is 2
Of the two or more nodes including the above switch circuit, the higher-order node is preferentially determined.

According to a fourth aspect of the present invention, there is provided a D / A converter according to the first to third aspects.
The A converter has a decoding circuit for decoding a digital input signal, and selects a constant current source circuit to be connected to a node based on the output signal.

In the D / A converter according to the fourth aspect, the switch circuit to be turned on is determined by the signal obtained by decoding the digital input signal output from the decode circuit.

Thus, the constant current source circuit is set to the corresponding R
The same constant current source circuit switches the current path to a different node before and after the transition even when multiple bits transition at the same time in the digital input signal, even when multiple bits transition simultaneously in the digital input signal. Since it is used continuously, a differential linearity error due to relative variation between the constant current source circuits is unlikely to occur, and further, the continuous use of the constant current source circuit is preferentially performed for higher nodes. So 2
For the higher nodes where the lead weight is large and the variation of the constant current value greatly affects the output value, the differential linearity error due to the relative variation of the constant current due to the difference in the constant current source circuit does not occur, and the constant current source The differential linearity error can be suppressed to be small with respect to the relative variation of the circuit, and the D / A converter having a sufficient output voltage accuracy by improving the monotonically increasing characteristic can be realized.

Further, an upper node having a large binary weight is appropriately selected according to the required differential linearity error characteristic,
By selecting a combination of lower nodes that share the corresponding constant current source circuit, the necessary differential linearity error characteristic can be realized by adding the minimum necessary switch circuit, so that the circuit size is small and the current consumption is low. D having a sufficient differential linearity error characteristic with respect to the relative variation of the constant current source circuit
/ A converter can be realized.

According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit device according to at least one of the first to fourth aspects.
It is characterized by having an A converter.

Thus, the differential linearity error of the D / A converter based on the relative variation of the built-in constant current source circuit can be improved, and a semiconductor integrated circuit device having uniform characteristics can be realized. .

[0023]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a D / A converter according to the present invention; FIG. FIG. 2 is a circuit diagram of the 4-bit input D / A converter according to the first embodiment. FIG. 3 is a conceptual diagram illustrating input / output characteristics of the decoding circuit according to the first embodiment. FIG. 4 is a circuit diagram of a 4-bit input D / A converter according to the second embodiment.

In the first embodiment shown in FIG. 2, each node N1, N2, N3,
An analog voltage output Vo is obtained by inputting constant currents from the constant current source circuits I1, I2, I3 and I4 to N4.
2 shows an A / A converter.

In FIG. 2, each of the constant current source circuits I1, I
2, I3, I4, an R-2R ladder resistor array RR including resistors R1 to R7, and switches S101, S103, S
The components consisting of 106 and S110 have the same configuration as the 4-bit input D / A converter (see FIG. 1) in the prior art, and a description thereof will be omitted.

The components in the first embodiment include switches S2, S4, S5, S7, S8, S9, and all switches S101, S2, S103, S4, S5, S106,
These are control signals for S7, S8, S9, and S110.

A switch S10 having the same configuration as that of the prior art
1, S103, S106, and S110 are from the LSB (= DS1) of the 4-bit digital ladder resistor string RR to the MSB.
Each node N1, N2, N3, N4 of the R-2R ladder resistor string RR corresponding to the bit string heading to (= DS4) is converted into constant current source circuits I1, I2, and I4 in accordance with the digital input signals DS1, DS2, DS3, DS4. It is configured to connect to I3 and I4. That is, the constant current source circuit I1 is connected to the node N1 for the LSB (= DS1) input, the constant current source circuit I2 is connected to the node N2 for the DS2 input, and the constant current source circuit I3 for the DS3 input. At the node N3 and the MSB (= D
S4) For the input, by connecting the constant current source circuit I4 to the node N4, the respective nodes N1, N2, N3,
The constant current from the constant current source circuits I1, I2, I3, I4 is input to N4 to obtain the output voltage Vo.

On the other hand, switches S2, S4, S
5, S7, S8, and S9 represent nodes N1, N2, and N3, respectively.
The constant current source circuits I2, I3,... Corresponding to the nodes N2, N3, N4 higher than the corresponding constant current source circuits I1, I2, I3.
It is configured to connect to I4.

More specifically, one end of the switch S2 is connected to the node N1 to which a constant current is input to the LSB (= DS1) input together with the switch S101, and the other end is connected to the node N2 one bit higher. It is connected to a constant current source circuit I2 for supplying a current. Further, regarding the node N1,
One end of each of the switches S4 and S7 is connected, and the other end of each of them is connected to the node N, which is two bits higher than
The switch S7 is connected to a constant current source circuit I4 for supplying a constant current to a higher-order node N4 of 3 bits.

Similarly, one end of each of the switches S5 and S8 is connected to a node N2 to which a constant current is to be input to the DS2 input together with the switch S103, and the other end is connected to a node one bit higher in the switch S5. The switch S8 is connected to a constant current source circuit I4 for supplying a constant current to a node N4, which is two bits higher, with a constant current source circuit I4 for supplying a constant current to N3.

Further, the switch S9 has one end connected to a node N3 to which a constant current is input to the DS3 input together with the switch S106, and the other end supplying a constant current to a node N4 one bit higher. To the constant current source circuit I4.

Each switch S101, S2, S103, S
The control signals of 4, S5, S106, S7, S8, S9, and S110 are 4-bit digital input signals DS1, DS
2, DS34, DS4. For example, 4
Bit digital input signals DS1, DS2, DS34,
DS4 is replaced with ten types of switches S101, S2, S10
3, S4, S5, S106, S7, S8, S9, S11
To make 0 a signal to be individually controlled, the 4-bit digital input signals DS1, DS2, DS34, DS4 are set to 1
A decoding circuit D for decoding 0-bit internal control signals DDS1 to DDS10 is required.

FIG. 3 shows the decoding circuit D and its input / output characteristics. As a circuit system of the decoding circuit D, in addition to being constituted by a logic circuit, a conversion table of input / output characteristics is stored in a built-in or external memory, and the conversion table is stored in accordance with digital input signals DS1, DS2, DS3, and DS4. Various configurations are conceivable, such as an output device and a device configured by a PLA or the like.

As is clear from the input / output characteristics shown in FIG. 3, the supply of a constant current to each of the nodes N1, N2, N3, N4 is limited to the upper node when there is no current input to the upper node. Constant current source circuits I2, I3, I4 to which current is to be supplied
Switches S2, S4, S
5, S7, S8 and S9 are controlled.

Specifically, for the input signal "0001", a constant current is supplied from the MSB (= DS4) constant current source circuit I4 to the node N1 of the LSB (= DS1) via the switch S7. Also, input signals “0010”, “001”
1 ", the MSB (= DS4) constant current source circuit I
4 supplies a constant current to the node N2 of DS2 via the switch S8. Further, the input signals “0100”, “010”
1 ”,“ 0110 ”and“ 0111 ”, the MSB
(= DS4) A constant current is supplied from the constant current source circuit I4 to the node N3 of DS3 via the switch S9.

The input signals "0011" and "010"
1 ”and“ 1001 ”, a constant current is supplied from the DS3 constant current source circuit I3 to the node N1 of the LSB (= DS1) via the switch S4, and the input signal“ 011 ”.
At “0”, “0111”, “1010”, and “1011”, a constant current is supplied from the DS3 constant current source circuit I3 to the node N2 of DS2 via the switch S5.

Further, the input signals "0111", "101"
In “1” and “1101”, a constant current is supplied from the DS2 constant current source circuit I2 to the node N1 of the LSB (= DS1) via the switch S2.

Next, an expression representing the output voltage Vo is derived.
As in the case of the prior art, each of the constant current source circuits I1, I2,
The output currents of I3 and I4 are I1, I2, I3 and I4,
The resistance of the R-2R ladder resistance row RR is represented by R1 = R2 = R4 =
It is assumed that R6 = R7 = r and R3 = R5 = 2r. Since the configuration of the R-2R ladder resistor string RR is the same as the configuration in the related art, the characteristic of the output voltage Vo with respect to the constant current input to each of the nodes N1, N2, N3, N4 is expressed by the following equation (1).
This is the same as (2), (3), and (4). In the first embodiment, the R-2R ladder resistor string RR and the constant current source circuit I
The switch for connecting I1, I2, I3 and I4 is different from the prior art. DS1, DS2, D in equation (5)
When S3 and DS4 are replaced with DDS1 to DDS10 to derive the output voltage Vo, Vo = (1/12) · r · (I1 · DDS1 + I2 · DDS2 + I3 · DDS4 + I4 · DDS7) + (2/12) · r · (I2 · DDS3 + I3 · DDS5 + I4 · DDS8) + (4/12) · r · (I3 · DDS6 + I4 · DDS9) + (8/12) · r · (I4 · DDS10) ... It becomes (11). If the current weights of the constant current source circuits I1, I2, I3, and I4 are all the same (I1 = I2 = I3 = I4 =
i), each digital input signal DS1, DS2, DS3, D
As a result, an output voltage Vo that is binary-weighted with respect to S4 or the internal control signals DDS1 to DDS10 is obtained.

Here, the characteristic of the differential linearity error in the first embodiment will be examined in comparison with the prior art. It is assumed that the relative variation of each of the constant current values I1, I2, I3, and I4 is expressed by Expression (7) under the same conditions as those studied in the related art. The change of the output voltage Vo when the digital input at this time changes from "0111" to "1000" is calculated.

The output of the decoder circuit with respect to the digital input "0111" is shown in FIG. 3B as DDS2 = DDS5 = DDS9 = 1 (12) ), The output voltage is calculated by using equations (7) and (12) as in equation (1).
Vo (0111) = (1/12) · r · (i · DDS2) + (2/12) · r · (i · DDS5) + (4/12) · r · (0 .875i DDS9) = (1/12) ir + (2/12) ir + (4/12) 0.875ir = (6.5 / 12) ir ...・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ （13）

From FIG. 3B, the output voltage for the digital input “1000” is DDS10 = 1. (14) Similarly, Vo (1000) = (8/12) · r · (0.875i · DDS10) = (8/12) · 0 .875i · r = (7/12) · i · r (15)

From equations (13) and (15), ΔVo = Vo (1000) −Vo (0111) = (0.5 / 12) · ir (16) and the differential linearity error is -0.5 LSB,
The differential linearity error of -1 LSB in the prior art calculated in Expression (10) can be improved by 50%, and sufficient output voltage accuracy can be obtained even with respect to the relative variation of the constant current source circuit. Can be realized.

This can be understood from the input / output characteristics shown in FIG. That is, the digital input signals DS1, DS2, DS
3 and DS4, in a multi-bit transition of 2 bits or more, in the conventional circuit, each of the constant current source circuits I1, I2, I3, and I3 corresponding to the nodes N1, N2, N3, and N4 of all the transition bit positions. Since the connection of I4 is controlled, the relative variation of each of the constant current source circuits I1, I2, I3, and I4 is directly reflected on the output voltage Vo. On the contrary,
In the first embodiment, the constant current source circuits I2, I3, and I4 connected to the nodes N2, N3, and N4 are connected to the lower nodes by the connection relationship between the internal control signals DDS1 to DDS10 decoded by the decoder circuit D and the switches. Since the connection is shared with the node, the connection switching of the constant current source circuits I1, I2, I3, and I4 is controlled to be smaller than that in the configuration in the related art. Specifically, "0001" to "0010",
“0101” to “0110”, “1001” to “1”
In the transition from “010” and “1101” to “1110”, there is no switching of the constant current source circuit itself, and the same circuit is used before and after the switching. The number of constant current source circuits to be switched is smaller than that of the conventional technology, and the switching of the constant current source circuits is performed mainly for the constant current source circuit for the lower node, and the constant current source circuit for the upper node is switched. The current source circuit has a configuration that also serves as a constant current supply to lower nodes.

Therefore, the digital input signals DS1, DS
2, the number of constant current source circuits that are switched also for bit transitions of DS3 and DS4 is limited, and a common constant current source circuit is shared between nodes on the higher-order bit side having a larger binary weight. Therefore, the differential linearity error can be reduced even with respect to the relative variation of the constant current source circuit, and the monotonous increase characteristic of the output voltage Vo can be improved to realize sufficient output voltage accuracy. it can.

In the second embodiment shown in FIG. 4, the MSB (= DSS) which has the largest influence of the relative variation of the constant current source circuit.
4) The constant current I4 output from the constant current source circuit I4 to MS is
Except for the node N4 of B (= DS4), DS 1 bit lower
Only the switch S9 is provided so that it can be used also as a constant current for input of the node N3 of the third node. For the lower nodes N2 and N1, a constant current is supplied from the corresponding constant current source circuits I2 and I1 as in the prior art. This is a configuration for inputting.

Therefore, except that the constant current input to the node N3 is the same as the configuration in the first embodiment, the configuration is the same as that of the prior art. Therefore, the equation representing the output voltage Vo is expressed by the following equation (5). And from equation (11), the digital input signal DS
1, DS2, DS3, and DS4, using the decoded signals DDS6 and DDS9 in FIG. 3, Vo = (1/12) · I1 · r · DS1 + (2/12) · I2 · r · DS2 + (4/12) · r · (I3 · DDS6 + I4 · DDS9) + (8/12) · I4 · r · DS4 (17) ) It can be expressed as. Constant current source circuits I1, I2, I3,
If the current weights of I4 are all the same (I1 = I2 =
I3 = I4 = i), each digital input signal DS1, DS
2, DS3, and DS4 are binary-weighted output voltages Vo. The decoder circuits that output DDS6 and DDS9 are digital input signals DS1, DS2, DS
3, the input of DS3 may be decoded in relation to DS4. As in FIG. 3, in addition to being constituted by a logic circuit, a conversion table of input / output characteristics is stored in an internal or external memory. Are stored, and various configurations such as a configuration in which the output is performed in accordance with the digital input signals DS3 and DS4 and a configuration in which the configuration is implemented by a PLA or the like are possible.

Here, the characteristic of the differential linearity error in the second embodiment will be examined in comparison with the prior art. Assuming that the relative variation of each of the constant current values I1, I2, I3, and I4 is expressed by Expression (7) under the same conditions as those studied in the related art, the digital input at this time is "0".
Output voltage V when changing from "111" to "1000"
Calculate the change in o.

The calculation of the output voltage Vo is the same as that of the prior art and the first embodiment, and the output voltage Vo for the digital input “0111” is calculated by the equations (7) and (1).
From 7), Vo (0111) = (1/12) .i.r.DS1 + (2/12) .i.r.DS2 + (4/12) .r. (0.875i.DDS9) = (1) / 12) · i · r + (2/12) · i · r + (4/12) · 0.875 i · r = (6.5 / 12) · i · r (18)

Similarly, the output voltage Vo for the digital input “1000” is: Vo (1000) = (8/12) · 0.875 i · r · DS4 = (7/12) · i · r. (19) From Expressions (18) and (19), ΔVo = Vo (1000) −Vo (0111) = (0.5 / 12) · ir (16) and the differential linearity error is -0.5 LSB.
As in the first embodiment, the differential linearity error of -1 LSB in the prior art calculated by equation (10) is 5
0% can be improved, and sufficient output voltage accuracy can be realized even with respect to the relative variation of the constant current source circuit.

That is, the constant current source circuit I4 for MSB is connected to DS
By providing the switch S9 which is also connected to the constant current source circuit 3, the constant current source circuit in the upper two bits having the largest binary weight can be shared, so that the output voltage sufficient for the relative variation of the constant current source circuit can be obtained. Accuracy can be achieved.

The constant current source circuit I4 is connected to the MSB (= DS
4) Only by sharing with DS3, the necessary differential linearity error can be secured without providing a switch for connecting the constant current source circuit to all nodes lower than the corresponding node. The number of switches and the circuit configuration of the decode circuit can be simplified, and a D / A converter with a compact circuit size and low current consumption can be provided.

As an example in which the D / A converter according to the first and second embodiments is incorporated in a semiconductor integrated circuit device,
A signal processor for performing signal processing of an audio signal, an image signal, or the like can be considered. In these semiconductor integrated circuit devices, the D / A in the first or second embodiment is also used.
By using the converter, the differential linearity error based on the relative variation of the built-in constant current source circuit can be improved, and a semiconductor integrated circuit device having uniform signal processing characteristics can be realized.

As described in detail above, in the D / A converter according to the first embodiment, the switches S2, S4, S
5, S7, S8, and S9 define nodes N1, N2, and N3, respectively.
Constant current source circuits I2, I3, located at nodes N2, N3, N4 higher than corresponding constant current source circuits I1, I2, I3.
I4, and the digital input signals DS1, DS2, DS3, DS4
Control signals DDS1 to DDS10 obtained by decoding
Thus, when there is no current input to the upper node, the constant current source circuits I2, I3, and I4, which should supply the constant current to the upper node, are controlled to supply the constant current. Here, the decoding circuit D may have various configurations such as a logic circuit configuration, a configuration that outputs according to a conversion table of input / output characteristics stored in a memory, and a configuration that includes a PLA or the like.

The output voltage Vo is calculated using the internal control signals DDS1 to DDS10 as follows: Vo = (1/12) .r. (I1.DDS1 + I2.DDS2 + I3.DDS 4 + I4.DDS7) + (2/12) .r. ( I2 · DDS3 + I3 · DDS5 + I4 · DDS8) + (4/12) · r · (I3 · DDS6 + I4 · DDS9) + (8/12) · r · (I4 · DDS10) If all current weights are the same, (I1 = I2
= I3 = I4 = i), each digital input signal DS1, DS
2, DS3, and DS4 are binary-weighted output voltages Vo.

In the configuration of the first embodiment, each of the constant current values I1, I2, I3, I
When the change in the output voltage Vo when the digital input changes from “0111” to “1000” under the condition of the relative variation of “4”, Vo (0111) = (6.5 / 12) · ir Vo (1000) = (7/12) · ir ΔVo = Vo (1000) −Vo (0111) = (0.
5/12) · i · r and the differential linearity error can be set to −0.5 LSB, so that it can be improved by 50% as compared with −1 LSB in the related art, and the relative current of the constant current source circuit can be improved. Even with a temporary variation, it is possible to improve the monotonous increase characteristic of the output voltage Vo and realize sufficient output voltage accuracy.

Also, in the input transition of 2 bits or more, the internal control signal DDS1 which is the output of the decoder circuit D is output.
Through the DDS 10 and the switch, the constant current source circuit I connected to each of the nodes N1, N2, N3, N4.
Since 1, I2, I3, and I4 are shared with lower nodes,
The connection switching of the constant current source circuits I1, I2, I3 and I4 themselves is reduced as compared with the configuration in the related art, and the differential linearity is maintained even with respect to the relative variation of the constant current source circuits I1, I2, I3 and I4. The error can be suppressed small, and the monotonous increase characteristic of the output voltage Vo can be improved to realize sufficient output voltage accuracy.

Further, in the D / A converter according to the second embodiment, the use of the lower node of the constant current source circuit corresponding to the upper node is determined by using the MSB (= DS4 ) Of the constant current source circuit I4,
This configuration is limited to use at the node N3 of DS3 one bit lower.

The configuration is the same as that of the prior art except that the constant current input to the node N3 is also inputted from the constant current source circuit I4 via the switch S9. Therefore, the output voltage Vo is given by the following equations (5) and (1).
From 1), Vo = (1/12) · I1 · r · DS1 + (2/12) · I2 · r · DS2 + (4/12) · r · (I3 · DDS6 + I4 · DDS9) + (8/12) ) · I4 · r · DS4, and if all the current weights are the same (I1 = I2
= I3 = I4 = i), each digital input signal DS1, DS
2, DS3, and DS4 are binary-weighted output voltages Vo.

The decoder circuit D for outputting DDS6 and DDS9 only needs to decode the digital input signal DS3 in relation to DS4, and comprises a logic circuit, a conversion table of input / output characteristics, a PLA and the like, as in FIG. Various configurations are possible.

The differential linearity error in the second embodiment is
The relative variation of each of the constant current values I1, I2, I3, and I4 is expressed by Expression (7), and the digital input is changed from “0111” to “1”.
Vo (0111) = (6.5 / 12) · ir Vo (1000) = (7/12) · ir ΔVo = Vo (1000) when the output voltage Vo changes to 000 ”. Since −Vo (0111) = (0.5 / 12) · ir, and the differential linearity error can be set to −0.5 LSB, it is necessary to improve 50% similarly to the first embodiment. As a result, it is possible to improve the monotonous increase characteristic of the output voltage Vo and realize sufficient output voltage accuracy even with respect to the relative variation of the constant current source circuit.

That is, by providing the switch S9,
Since the constant current source circuit in the upper two bits having the largest binary weight can be shared, sufficient output voltage accuracy can be realized even with respect to the relative variation of the constant current source circuit.

Further, the constant current source circuits I2, I3, I4 are
Necessary differential linearity error can be secured without providing a switch to connect to all lower nodes N1, N2, N3, so that a simple circuit configuration can be obtained, and a compact circuit scale and consumption can be achieved. A D / A converter with small current can be provided.

Further, if the D / A converter is incorporated in a semiconductor integrated circuit device such as a signal processor for performing signal processing of an audio signal, an image signal, or the like, it is based on the relative variation of the built-in constant current source circuit. Since the differential linearity error can be improved, a semiconductor integrated circuit device having uniform signal processing characteristics can be realized.

The present invention is not limited to the first and second embodiments, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention. For example, in the first embodiment, each of the nodes N1, N2,
Each of N3 and N4 has a connection relation of switches connecting the constant current source circuits I2, I3 and I4 corresponding to all upper nodes. In the second embodiment, the MSB (= DS
Although the switch S9 is provided to connect the constant current source circuit I4 corresponding to 4) to the node N3 corresponding to DS3, the D / A converter according to the present invention is not limited to this, and is required. Depending on the differential linearity error characteristic and the number of bits of the digital input signal, the constant current source circuit corresponding to the upper node can be shared by the lower node as well.

The components such as the constant current source circuit and the switch can be constituted by MOS transistors, bipolar transistors, or other devices exhibiting other desired characteristics.

As a semiconductor integrated circuit device incorporating the D / A converter according to the present invention, a signal processor for performing signal processing of audio signals, image signals, and the like has been described as an example.
The present invention is not limited to this, and it goes without saying that any semiconductor integrated circuit device having a function of performing D / A conversion can be generally used.

[0067]

According to the present invention, the differential linearity error caused by the relative variation of the constant current source circuit can be reduced, the monotonous increase characteristic of the output voltage with respect to the digital input signal can be improved, and the sufficient output can be obtained. A D / A converter capable of achieving voltage accuracy can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a conventional 4-bit input D / A converter.

FIG. 2 is a circuit diagram of a 4-bit input D / A converter according to the first embodiment.

FIG. 3 is a conceptual diagram illustrating input / output characteristics of a decoding circuit according to the first embodiment.

FIG. 4 is a circuit diagram of a 4-bit input D / A converter according to a second embodiment.

[Explanation of Symbols] D decoder circuit RR R-2R ladder resistance string I1, I2, I3, I4 Constant current source circuit N1, N2, N3, N4 R-2R Ladder resistance string nodes R1, R2, R3, R4, R5 , R6, R7R-2R The resistors constituting the ladder resistor string S101, S2, S103, S4, S5, S106, S
7, S8, S9, S110 Switch DDS1, DDS2, DDS3, DDS4 Digital input signal DDS1, DDS2, DDS3, DDS4, DDS5,
DDS6, DDS7, DDS8, DDS9, DDS10
Internal control signal

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hidenobu Ito 2-844-2 Kozoji-cho, Kasugai-shi, Aichi F-term within Fujitsu VSI Co., Ltd. 5J022 AB03 AB06 BA01 BA06 CD02 CD03 CE01 CF04 CF05 CF07 CG01 5J055 AX37 BX04 CX00 EZ03 EZ24 EZ38 GX01 GX02

Claims (5)

[Claims] 1. An R-2R ladder resistor string having a node to which a current is input corresponding to a bit string of a digital input signal, and corresponding to each node of the R-2R ladder resistor string having the same current weight. A constant current source circuit, and the constant current source circuit and the R-2R according to the digital input signal.
A D / A converter comprising: a switch circuit for appropriately connecting each node of the ladder resistor row; and two or more switch circuits each having one end connected to the same node in the R-2R ladder resistor row. The other end of one switch circuit is connected to the constant current source circuit corresponding to the same node, and the other end of the other switch circuit is connected to the constant current source circuit corresponding to a node higher than the same node. D / A converter characterized by being connected. 2. The D / A converter according to claim 1, wherein the two or more switch circuits are preferentially turned on from the other switch circuits. 3. The semiconductor device according to claim 1, further comprising: at least two nodes each including the at least two switch circuits, wherein a conduction mode of the at least two switch circuits is determined preferentially from an upper node among the at least two nodes. 3. The D / A converter according to claim 2, wherein: 4. A constant current source circuit to be connected to the node is selected according to an output signal of the decoding circuit, the decoding circuit comprising a decoding circuit for decoding a bit string of the digital input signal. 3. The D / A converter according to at least one of 3. 5. A semiconductor integrated circuit device comprising the D / A converter according to at least one of claims 1 to 4.