JP2002124617A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JP2002124617A JP2002124617A JP2000318242A JP2000318242A JP2002124617A JP 2002124617 A JP2002124617 A JP 2002124617A JP 2000318242 A JP2000318242 A JP 2000318242A JP 2000318242 A JP2000318242 A JP 2000318242A JP 2002124617 A JP2002124617 A JP 2002124617A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- lead frame
- tape
- tapes
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置用リー
ドフレーム、特にＬＯＣ（Lead on Chip）構造のリード
フレームに関するものである。The present invention relates to a lead frame for a semiconductor device, and more particularly to a lead frame having a LOC (Lead on Chip) structure.
【０００２】[0002]
【従来の技術】一般に、半導体装置の組立てに使用され
るリードフレームは、インナーリード（電極接続用の内
部配線部分）の前方に、タブと呼ばれる部分を持ってお
り、そのタブに半導体素子を載置して固定するようにな
っている。タブとインナーリードとの間には若干の隙間
が形成されており、半導体素子の電極端子（ボンディン
グパット）とインナーリードとの間の結線は、その隙間
を跨いでボンディングワイヤにより行われている。その
ため、上記隙間の分だけリードフレームに空間的余裕を
設ける必要があるが、最近のように半導体集積回路の大
容量化に伴って半導体素子の寸法が大きくなると、この
種の隙間を形成する余裕がなくなると共に、樹脂封入に
必要な長さをインナーリードの部分に確保することが困
難になって来ている。2. Description of the Related Art Generally, a lead frame used for assembling a semiconductor device has a portion called a tab in front of an inner lead (an internal wiring portion for connecting an electrode), and a semiconductor element is mounted on the tab. It is designed to be placed and fixed. A slight gap is formed between the tab and the inner lead, and the connection between the electrode terminal (bonding pad) of the semiconductor element and the inner lead is made by a bonding wire across the gap. For this reason, it is necessary to provide a space margin in the lead frame by the amount of the above-described gap. And it is becoming difficult to secure the length required for resin encapsulation in the inner lead portion.
【０００３】そこで、ＩＣ或いはＬＳＩを搭載するリー
ドフレームにおいては、リード先端部の段差やシフトを
防止するため、リードフレームのリード先端部に短冊状
に切断したフィルムから成るテープを貼り付けることが
行われている。Therefore, in a lead frame on which an IC or LSI is mounted, in order to prevent a step or a shift at the leading end of the lead, a tape made of a strip-cut film is attached to the leading end of the lead frame. Have been done.
【０００４】図２に従来のＬＯＣリードフレームを用い
たＩＣパッケージの断面構造を示す。プレス打抜きやエ
ッチングによって製造されたリードフレームのインナー
リード１の先端部に、予め接着剤が片面又は両面に塗布
された絶縁性フィルムから成る半導体チップ搭載用の接
着剤付テープ２が貼り付けられる。次いで、このテープ
２の下に半導体チップ３が搭載される。即ち、このテー
プ２の一面がリードフレームの裏側に接着され、他面に
半導体チップ３が接着されて、相互に固定される。そし
て、半導体チップ３の電極端子とインナーリード１との
間がボンディングワイヤ５によって結線され、レジン４
でモールドされる。FIG. 2 shows a cross-sectional structure of an IC package using a conventional LOC lead frame. An adhesive tape 2 for mounting a semiconductor chip, made of an insulating film having an adhesive applied to one or both sides in advance, is attached to the tip of the inner lead 1 of the lead frame manufactured by press punching or etching. Next, the semiconductor chip 3 is mounted under the tape 2. That is, one surface of the tape 2 is adhered to the back side of the lead frame, and the semiconductor chip 3 is adhered to the other surface and fixed to each other. The electrode terminals of the semiconductor chip 3 and the inner leads 1 are connected by bonding wires 5, and the resin 4
Is molded.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、チップ
シュリンクによりリードフレームは狭ピッチ化し、イン
ナーリードの幅が細くなってきている。このようなＬＯ
Ｃリードフレームに半導体チップを搭載し、モールドを
行うと、インナーリードが細く剛性がなく、また半導体
チップが小さく軽くなっているために、レジン流し込み
時に半導体チップが浮き上がってしまう。そのため半導
体チップの上下のレジン体積が均等にならず、パッケー
ジの反りが発生する。However, the pitch of the lead frame has been reduced due to the chip shrink, and the width of the inner lead has been reduced. Such LO
When a semiconductor chip is mounted on a C lead frame and molded, the inner lead is thin and has no rigidity, and the semiconductor chip is small and light, so that the semiconductor chip floats when the resin is poured. For this reason, the resin volumes above and below the semiconductor chip are not equalized, and the package is warped.
【０００６】このパッケージの反りを防止するために
は、半導体チップ上のレジンと半導体チップ下のレジン
体積を均一にする必要がある。In order to prevent the package from warping, it is necessary to make the resin volume on the semiconductor chip and the resin volume under the semiconductor chip uniform.
【０００７】従来は、この半導体チップ上下のレジン体
積を均一にするために、図３に示す様に、インナーリー
ド１にデプレス加工を行い、半導体チップ位置を下げ
て、上下のレジンバランスが均等になる様な方法を用い
る。しかし、インナーリードが細くなると、デプレス加
工精度を維持することが困難になる。Conventionally, in order to make the resin volume above and below the semiconductor chip uniform, as shown in FIG. 3, the inner lead 1 is depressed to lower the position of the semiconductor chip so that the resin balance between the upper and lower parts becomes even. The method used is as follows. However, when the inner lead becomes thinner, it becomes difficult to maintain the depressing accuracy.
【０００８】そこで、本発明の目的は、上記課題を解決
し、インナーリードにデプレス加工を行わないで、半導
体チップ上下のレジン体積を均一に保ち、モールドした
際のパッケージ反りを防止することにある。Accordingly, an object of the present invention is to solve the above-mentioned problems, to keep the resin volume above and below the semiconductor chip uniform without depressing the inner leads, and to prevent package warpage when molded. .
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するた
め、本発明の半導体装置用リードフレームは、次のよう
に構成したものである。In order to achieve the above object, a semiconductor device lead frame according to the present invention is configured as follows.
【００１０】（１）請求項１に記載の発明は、リードフ
レームのインナーリード先端部に、半導体チップを接着
するためのテープを貼り付けた構造のリードフレームに
おいて、前記テープを２枚以上貼り重ねて厚く構成した
ことを特徴とする。(1) According to the first aspect of the present invention, in a lead frame having a structure in which a tape for bonding a semiconductor chip is bonded to a tip of an inner lead of the lead frame, two or more tapes are laminated. It is characterized by having a thick structure.
【００１１】本発明によれば、テープを２枚以上積層し
て半導体チップの搭載位置を下げたので、半導体チップ
上下のレジンバランスを同一にすることが可能になり、
モールドした際のパッケージ反りを防止することができ
る。According to the present invention, since two or more tapes are stacked to lower the mounting position of the semiconductor chip, it is possible to make the resin balance above and below the semiconductor chip the same.
Package warpage during molding can be prevented.
【００１２】また、テープを２枚以上貼り重ねて厚く構
成するだけで半導体チップの搭載位置を下げることがで
きるので、従来のインナーリードにデプレス加工を行っ
て半導体チップ位置を下げる構造や、接着剤層を単層又
は複数層の形で介在させて半導体チップの搭載位置を下
げる構造と比較した場合、製造が容易であり、微細ピッ
チのＬＯＣリードフレームを安価に製造することができ
る。Further, since the mounting position of the semiconductor chip can be lowered only by laminating two or more tapes to form a thicker structure, a conventional inner lead is subjected to depressing to lower the semiconductor chip position. Compared with a structure in which the layers are interposed in the form of a single layer or a plurality of layers to lower the mounting position of the semiconductor chip, manufacture is easier and a LOC lead frame with a fine pitch can be manufactured at a low cost.
【００１３】（２）請求項２に記載の発明は、請求項１
記載の半導体装置用リードフレームにおいて、前記２枚
以上貼り重ねたテープが、それぞれ両面に接着剤が塗布
された同じ接着剤付テープから成ることを特徴とする。(2) The invention according to claim 2 is the invention according to claim 1.
In the semiconductor device lead frame described above, the two or more laminated tapes are made of the same adhesive tape with an adhesive applied to both surfaces.
【００１４】この特徴によれば、両面に接着剤が塗布さ
れた同じ接着剤付テープを用いることにより、一種類の
接着剤付テープだけを用意すれば済むことになり、複数
種類のテープを用意する場合に較べて経済的となる。According to this feature, by using the same adhesive tape with adhesive applied to both sides, only one kind of adhesive tape needs to be prepared, and a plurality of types of tape are prepared. Is more economical than
【００１５】＜発明の要点＞パッケージの反りはモール
ド時における半導体チップ上下のレジン体積の不均一が
影響している。そこで本発明ではインナーリード先端部
にテープを複数枚貼り付けて半導体チップの搭載位置を
下げる様にする。<Summary of the Invention> The warpage of a package is affected by uneven resin volumes above and below a semiconductor chip during molding. Therefore, in the present invention, a plurality of tapes are attached to the tips of the inner leads to lower the mounting position of the semiconductor chip.
【００１６】テープで半導体チップ位置を下げるために
は、半導体チップ厚又はテープ厚を厚くする方法も考え
られるが、この場合テープが特注品となり、ＬＯＣリー
ドフレームの単価が高くなってしまう、というデメリッ
トがある。また極端にテープが厚いものは、テープの製
造ができない場合もある。In order to lower the position of the semiconductor chip with the tape, it is conceivable to increase the thickness of the semiconductor chip or the tape. However, in this case, the tape becomes a custom-made product, and the unit cost of the LOC lead frame increases. There is. If the tape is extremely thick, it may not be possible to manufacture the tape.
【００１７】これに対し、本発明は、インナーリード先
端部にテープを複数枚貼り付けて半導体チップの搭載位
置を下げるものであり、上記のような欠点が無いため、
モールドした際のパッケージ反りを防止する手段とし
て、非常に簡便で有効な手段となる。On the other hand, according to the present invention, a plurality of tapes are attached to the tips of the inner leads to lower the mounting position of the semiconductor chip.
This is a very simple and effective means for preventing package warpage during molding.
【００１８】[0018]
【発明の実施の形態】以下、本発明を図示の実施形態に
基づいて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the illustrated embodiment.
【００１９】図１に本実施形態のＬＯＣリードフレーム
の断面構造を示す。プレス打抜きやエッチングによって
製造されたリードフレームのインナーリード１の先端部
に、半導体チップ搭載用の接着剤付テープ２が複数枚積
層して貼り付けられる。この各接着剤付テープ２は、予
め絶縁性フィルム（高耐熱ポリイミド系フィルム）の片
面又は両面に、接着剤（熱可塑性又は熱硬化性接着剤
等）が塗布された、同一のテープから成る。なお本実施
形態の場合、テープ２はその両面に接着剤が塗布された
いわゆる両面接着テープから成る。FIG. 1 shows a cross-sectional structure of the LOC lead frame of the present embodiment. A plurality of adhesive tapes 2 for mounting a semiconductor chip are laminated and attached to the tip of the inner lead 1 of a lead frame manufactured by press punching or etching. Each of the adhesive tapes 2 is made of the same tape in which an adhesive (a thermoplastic or thermosetting adhesive or the like) is applied to one or both surfaces of an insulating film (a high heat-resistant polyimide film) in advance. In the case of the present embodiment, the tape 2 is a so-called double-sided adhesive tape having both sides coated with an adhesive.
【００２０】上記のリードフレームには、その接着剤付
テープ２の積層体の下に、半導体チップ３が搭載され
る。即ち、この接着剤付テープ２の積層体の一面がリー
ドフレームのインナーリード１の裏側に接着され、積層
体の他面に半導体チップ３が接着されて、相互に固定さ
れる。従って、リードフレームのインナーリード１に対
する半導体チップ３の位置が、テープ２の積層体の厚味
分だけ下げられる。The semiconductor chip 3 is mounted on the lead frame under the laminate of the adhesive tape 2. That is, one surface of the laminated body of the adhesive tape 2 is adhered to the back side of the inner lead 1 of the lead frame, and the semiconductor chip 3 is adhered to the other surface of the laminated body and fixed to each other. Therefore, the position of the semiconductor chip 3 with respect to the inner leads 1 of the lead frame is lowered by the thickness of the tape 2 laminate.
【００２１】本実施形態の場合、２枚の接着剤付テープ
２を重ね合わせて、接着剤付テープ２の積層体を構成し
ている。従って、半導体チップ３の位置は、テープ２の
２枚分の厚さ相当分だけ下げられている。しかし、接着
剤付テープ２を３枚以上重ね合わせて、所定の厚さの積
層体を構成することもできる。In the case of the present embodiment, two adhesive tapes 2 are overlapped to form a laminate of the adhesive tapes 2. Therefore, the position of the semiconductor chip 3 is lowered by an amount corresponding to the thickness of two tapes 2. However, three or more adhesive tapes 2 may be stacked to form a laminate having a predetermined thickness.
【００２２】その後、半導体チップ３の電極端子とイン
ナーリード１との間がボンディングワイヤ５によって結
線され、レジン４でモールドされる。このとき、半導体
チップ３はその位置がテープ２の積層体の厚味分だけ下
げられているので、レジン４のモールド中のほぼ中央部
である所望位置に保持される。Thereafter, the electrode terminals of the semiconductor chip 3 and the inner leads 1 are connected by bonding wires 5 and molded with a resin 4. At this time, since the position of the semiconductor chip 3 is lowered by the thickness of the laminated body of the tape 2, the semiconductor chip 3 is held at a desired position which is substantially the center of the resin 4 in the mold.
【００２３】このように、本実施形態のＬＯＣリードフ
レームは、図２に示した従来構造のＬＯＣリードフレー
ムにおけるテープ２を２枚貼り付けた構造になってい
る。このようにテープ２を貼り重ねることによって、半
導体チップ３の搭載位置が下がり、モールド時のレジン
のバランスを均一にすることが可能になる。As described above, the LOC lead frame of the present embodiment has a structure in which two tapes 2 are adhered to the LOC lead frame of the conventional structure shown in FIG. By laminating the tape 2 in this way, the mounting position of the semiconductor chip 3 is lowered, and the resin balance at the time of molding can be made uniform.
【００２４】半導体チップ３の厚さはパッケージ厚に応
じて可変である。半導体チップ３をパッケージ内におい
て中央に配置することにより、上下のレジン４が１対１
になるようにすることが好ましい。The thickness of the semiconductor chip 3 is variable according to the package thickness. By arranging the semiconductor chip 3 at the center in the package, the upper and lower resins 4 are in one-to-one correspondence.
It is preferable that
【００２５】[0025]
【発明の効果】以上説明したように本発明によれば、次
のような優れた効果が得られる。As described above, according to the present invention, the following excellent effects can be obtained.
【００２６】（１）請求項１の発明によれば、テープを
２枚以上積層して半導体チップの搭載位置を下げたの
で、本リードフレームを用いることによって、半導体チ
ップ上下のレジンバランスを同一にすることが可能にな
り、モールドした際のパッケージ反りを防止することが
できる。(1) According to the first aspect of the present invention, since two or more tapes are stacked to lower the mounting position of the semiconductor chip, by using the present lead frame, the resin balance between the upper and lower parts of the semiconductor chip can be made the same. This makes it possible to prevent package warpage during molding.
【００２７】また、テープを２枚以上貼り重ねて厚く構
成するだけで半導体チップの搭載位置を下げることがで
きるので、製造が容易であり、微細ピッチのＬＯＣリー
ドフレームを安価に製造することができる。Further, since the mounting position of the semiconductor chip can be lowered only by laminating two or more tapes to form a thick layer, the manufacturing is easy and the LOC lead frame having a fine pitch can be manufactured at low cost. .
【００２８】（２）請求項２の発明によれば、上記２枚
以上貼り重ねるテープに、それぞれ両面に接着剤が塗布
された同じ接着剤付テープを用いているので、テープと
して一種類の接着剤付テープを用意すれば済むことにな
り、複数種類のテープを用意する場合に較べて経済的と
なる。(2) According to the second aspect of the present invention, since the same tape with an adhesive having an adhesive applied to both surfaces is used for the two or more tapes to be laminated, one kind of adhesive tape is used. It is only necessary to prepare a tape with an agent, which is more economical than preparing a plurality of types of tapes.
【図１】本発明のＬＯＣリードフレームの断面構造を示
す図である。FIG. 1 is a diagram showing a cross-sectional structure of a LOC lead frame of the present invention.
【図２】従来のＬＯＣリードフレームの断面構造を示す
図である。FIG. 2 is a diagram showing a cross-sectional structure of a conventional LOC lead frame.
【図３】従来のＬＯＣリードフレームにデプレスした場
合の断面構造を示す図である。FIG. 3 is a diagram showing a cross-sectional structure when depressed on a conventional LOC lead frame.
１ インナーリード ２ テープ ３ 半導体チップ ４ レジン ５ ボンディングワイヤ DESCRIPTION OF SYMBOLS 1 Inner lead 2 Tape 3 Semiconductor chip 4 Resin 5 Bonding wire
───────────────────────────────────────────────────── フロントページの続き (72)発明者 木内 誠 茨城県日立市助川町３丁目１番１号 日立 電線株式会社電線工場内 Ｆターム(参考） 5F067 AA01 AA18 AB02 BB08 BE10 CC03 CC08 DE08 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Makoto Kiuchi 3-1-1, Sukekawa-cho, Hitachi-shi, Ibaraki F-term in the electric wire plant of Hitachi Cable Co., Ltd.
Claims (2)
に、半導体チップを接着するためのテープを貼り付けた
構造のリードフレームにおいて、前記テープを２枚以上
貼り重ねて厚く構成したことを特徴とする半導体装置用
リードフレーム。1. A semiconductor device comprising: a lead frame having a structure in which a tape for bonding a semiconductor chip is bonded to a tip end portion of an inner lead of the lead frame; Equipment lead frame.
れ両面に接着剤が塗布された同じ接着剤付テープから成
ることを特徴とする請求項１記載の半導体装置用リード
フレーム。2. A lead frame for a semiconductor device according to claim 1, wherein said two or more tapes are made of the same adhesive tape having an adhesive applied to both surfaces thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000318242A JP2002124617A (en) | 2000-10-13 | 2000-10-13 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000318242A JP2002124617A (en) | 2000-10-13 | 2000-10-13 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002124617A true JP2002124617A (en) | 2002-04-26 |
Family
ID=18796896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000318242A Withdrawn JP2002124617A (en) | 2000-10-13 | 2000-10-13 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002124617A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11769714B2 (en) | 2020-09-08 | 2023-09-26 | Kabushiki Kaisha Toshiba | Semiconductor device with semiconductor chip mounted on die pad and leads of lead frame |
-
2000
- 2000-10-13 JP JP2000318242A patent/JP2002124617A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11769714B2 (en) | 2020-09-08 | 2023-09-26 | Kabushiki Kaisha Toshiba | Semiconductor device with semiconductor chip mounted on die pad and leads of lead frame |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20080108 |