JP2002124078A - Memory lsi incorporating compression expansion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory LSI which can store data exceeding physical memory capacity of a semiconductor memory. SOLUTION: It is characterized in that a logic circuit for compressing and expanding data arranged between a memory array in a semiconductor memory and an I/O circuit is integrated on a memory LSI with one chip. Also, this problem can be solved by also a method in which a processor and a ROM in which compressing and expanding program are recorded are integrated on a memory LSI with one chip instead of the logic circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates to a memory LSI.

[Prior art]

A memory LSI is a read-only ROM
And read / write RAM, and ROMs such as PROM, EPROM, EEPROM, and flash memory are known.

[0003] Of these, ROM has a different storage method depending on the format. Basically, one gate element corresponds to one data bit, and 1 and 0 are obtained by injecting electric charge into the gate element. Remember.

An SRAM (St), which is a kind of RAM, is used.
Atic RAM) is generally manufactured by forming a logic circuit such as a flip-flop circuit mainly including transistors on a semiconductor substrate (silicon wafer).

On the other hand, a DRAM (Dynamic RA)
M) is generally manufactured by forming a capacitance that holds a charge on a semiconductor substrate.

In these memories, data is input and output to and from an external data bus through an I / O circuit mounted in the same LSI.

In general, each type requires one memory element per bit (the above-described flip-flop circuit or capacitance).

FIG. 1 is a block diagram showing a form of a conventional memory LSI. This figure shows an example of an SDRAM or the like having a built-in timing generator. A normal DRAM generally does not have a built-in timing generator and command decoder.

[0009]

[Problems to be solved by the invention]

In a conventional memory LSI, one circuit memory element is required for one bit of data input from a data bus, so that only a memory capacity corresponding to the degree of integration can be obtained.

[0011] Further, in order to increase the degree of integration, very advanced manufacturing processing technology is required.
There were physical limitations.

An object of the present invention is to improve the memory capacity even when the degree of integration is kept constant.

[0013]

According to a first embodiment of the present invention, there is provided a semiconductor memory circuit as described in the prior art, and a logic for compressing and expanding data interposed between an input / output circuit and the memory. And a circuit integrated on a single chip.

A second embodiment of the present invention relates to a semiconductor memory circuit as described in the background art, a ROM storing a program for compressing and expanding input / output data to and from the memory circuit, and a program for executing the program. And a processor for performing the operations on a single chip.

[0015]

FIG. 2 is a schematic diagram showing a first embodiment of the present invention.

1 is characterized in that a compression circuit 201 and a decompression circuit 202 are interposed between an I / O (input / output) circuit 102 and a memory array 101, as compared with the conventional memory LSI shown in FIG.

In data writing, an address is interpreted by a row decoder and a column decoder, and the memory array 101
Conventionally, the bit data (1 or 0) is set for the memory element from the data bus via the I / O circuit after the memory element corresponding to the address is specified from the upper memory element. Is equivalent to

In the present invention, the I / O from the data bus
The bit data input through the circuit is first subjected to data compression by a compression circuit 201, and the memory array 10
It is characterized in that it is sent to 1.

On the other hand, in data reading, a memory element is specified from an address in the same manner as writing, and then bit data stored in the memory element is output to a data bus through an I / O circuit, which is the same as the conventional technique. It is.

The present invention is characterized in that an output from a memory element, that is, a memory array is output to an I / O circuit via a data expansion circuit 202.

Here, the compression circuit 201 employs a Huffman compression procedure or the like constituted by a logic circuit (generally called a Huffman decoder). A well-known compression procedure such as a run-length compression procedure or an LZW compression procedure is used. May be used.

The decompression circuit 202 comprises a compression circuit 201
A circuit that performs the reverse procedure of the above is used.

For data having a property that does not require reversibility (such as image data), a JPEG (DCT) encoder which is an irreversible compression algorithm, a JP
An EG (DCT) decoder or the like may be used as a compression circuit or an expansion circuit, respectively.

FIG. 3 is a schematic diagram showing a second embodiment of the present invention.

In the first embodiment shown in FIG. 2, circuits corresponding to the compression circuit 201 and the expansion circuit 202 which are constituted by logic circuits are replaced with a processor 301 (CPU or MP) in this embodiment.
U) and a ROM 302 storing a program for driving the processor.

Here, in the ROM 302, a compression and decompression circuit configured by a logic circuit in the first embodiment, such as Huffman encoding and decoding or JPEG encoding and decoding, implemented as software is used. And the processor 30 is provided by the software.
1 is driven.

Here, in addition to a non-rewritable mask ROM, a rewritable PROM, EPRO,
An M, EEPROM, flash memory, or the like may be used.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments utilizing the present memory LSI will be described below.

The memory LSI according to the present invention is a conventional memory LSI (DRAM, SRAM, flash memory,
It can be manufactured as a memory LSI that is pin-compatible with EPROM, etc.).
Basically, it can be applied to all the applications for which.

As an example, if a DRAM is used for the memory array portion of the present memory LSI and used as a main memory of a computer, it can be used as a storage device beyond its physical memory capacity by its compression function.

Further, if a flash memory is used in the memory array portion of the present memory LSI and the present invention is applied to a digital camera or the like compatible with the flash memory, the number of photographed images can be increased by exceeding the physical memory capacity of the conventional flash memory by the compression function. be able to.

[0032]

According to the present invention, it is possible to provide a memory LSI having an effective storage capacity which cannot be attained by the conventional technology due to physical limitations (such as limitations on manufacturing accuracy in manufacturing and physical limitations due to electronic properties). Will be possible.

[0033]

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing an example of a memory LSI according to a conventional technique.

FIG. 2 is a memory LSI according to the first embodiment of the present invention;
FIG. 4 is a schematic diagram showing an example of the above.

FIG. 3 is a memory LSI according to a second embodiment of the present invention;
FIG. 4 is a schematic diagram showing an example of the above.

[Explanation of symbols]

 Reference Signs List 101 memory array 102 I / O (input / output circuit) 103 address counter 104 timing generator 201 compression circuit 202 expansion circuit 301 processor 302 ROM

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03M 7/42 G11C 17/00 636A 636B

Claims (2)

[Claims] A semiconductor memory circuit; a logic circuit for compressing and expanding data interposed between an input / output circuit and the memory;
And a one-chip integrated memory L
SI. 2. A one-chip integration of a semiconductor memory circuit, a ROM storing a program for compressing and decompressing input / output data to and from the memory circuit, and a processor for executing the program. Memory LSI.