JP2002123431A - Dram and memory page operating method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an economically available DRAM and a memory page operating method therefor. SOLUTION: In a setting process, a new position to be reflected with the position of a detected defective memory page is set, choices for the operating mode of the defective memory page are defined, a page attribute is processed, processing in a normal access mode or page operating mode is instructed and an express page examination table is set. In an operating process, the defective memory page is exchanged with a normal memory page according to the result of the setting process, and the defective memory page is added to the rear-most address of a memory. The detected defective memory page is exchanged with the normal memory page. Therefore, normal operation can be maintained and the temporary stop of the entire system does not occur. Besides, since the normal memory page exists, it is not necessary to exchange the entire memory and the waste of time and money for exchanging the entire memory is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DRAM (Dyn).
Amic Random Access Memory) and a memory page operating method thereof.

[0002]

2. Description of the Related Art Conventionally, a DRAM module 1 is a memory device formed from a plurality of DRAMs 10, which are formed from continuous memory pages 11 or continuous storage grids. As shown in FIG.
When M10 is 16M, it can be partitioned into 3096 4K-sized memory pages 11 (000-FFF), the memory controller 20 of the computer system selects the DRAM 1 to access information, and the support logic 12 of the DRAM 1 Access control to the memory page 11 is performed.

[0003]

However, when a computer system is inputted, a basic input / output system (BI) is input.
After the OS 10 detects the DRAM 10 or in the process of manufacturing the DRAM 10, many errors and mistakes may occur due to defects or damages in the manufacturing process, and the memory page 11 or the storage grid of the DRAM 10 may have a defect. .
When the A03 defective memory page is executed, it affects the operation of the entire system, is suspended, normal operation is not performed, and the system cannot access the DRAM 1 having the defect.

In addition, personal digital assistants (PDs)
In A) or other small communication products, the DRAM 10 is located inside the motherboard. Internal DRAM 10
Occurs, the operation of the entire DRAM 1 is affected, the operation logic cannot acquire the memory page 11, and the system is temporarily stopped or the memory is invalidated, and the entire system is discarded. At this time, the yield of the DRAM manufacturer decreases, and the normally operable part of the system or the DRAM 10 is wasted, causing serious damage.

It is therefore an object of the present invention to provide a DRAM which can be used economically and a method of operating a memory page thereof.

[0006]

A DR according to the present invention is provided.
According to AM, it comprises one or more DRAMs having a plurality of memory pages or storage grids and a memory controller. A memory controller having a memory for controlling and accessing the memory page and internally storing a result of the setting process; and an indicator bit for storing a quick page check table and corresponding to the plurality of memory pages. And an SRAM for instructing execution of a normal page access mode or a page operation mode.

According to a method of operating a memory page of a DRAM according to the present invention, a setting process and an operating process are included. The setting process inspects the memory and detects a defective memory page in the memory page, and specifies a new position where the position of the defective memory page is reflected by setting the reflection buffer table, and determines a new position. And Further, the setting process defines the operation mode options of the defective memory page inside the reflection buffer table, and instructs the process of processing the page attribute and the normal access mode or the page operation mode of the memory page or the storage unit. , A process of setting a rapid page survey table. The operation process checks the quick page investigation table and the reflection buffer table, replaces the defective memory page with a normal memory page according to the record of the rapid page investigation table and the reflection buffer table, and adds the defective memory page to the backmost address of the memory. It is a process.

The detected defective memory page is replaced with a normal memory page on the back of the DRAM, and the defective memory page is added to an address on the back of the DRAM. For this reason,
When a defective memory page exists, smooth operation can be maintained and the entire system will not be suspended. Also, since there is a normal memory page, there is no need to replace the entire memory, and the time and money spent replacing the entire memory are reduced.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 2, according to one embodiment of the present invention, one or more DRAMs 30 are provided.
And the memory controller 20. DRA
M30 is provided with a plurality of memory pages 31 or storage grids. The memory controller 20 has a memory 21 for controlling and accessing a memory page 31 and internally storing the results of the configuration process.
And an SRAM 23 which stores a quick page check table, has instruction bits corresponding to a plurality of memory pages, and instructs execution of the normal access mode or page operation mode of the memory page 31.

As shown in FIG. 3, the memory page operation method includes a setting process and an operation process. DRAM 30
When is used or entered for the first time, a setting process is performed to determine the location of the erroneous page in the DRAM 30 according to the following process.

Step A1: Memory test step: B
The IOS is started to inspect the DRAM 30 for defects. DR
When there is no defect in the AM 30, the access of the DRAM 30 is defined as normal, and the BIOS does not execute the position determination step A2 of the erroneous page, but executes the attribute processing step A3. When detecting a defect in the DRAM 30, BIO
Activate S and execute step A2 of setting a reflection buffer table.

Step A2: Determine position of erroneous page: When detecting a defect in DRAM 30, the system sets a reflection buffer table and indicates a defect position and a new position to be reflected. Further, as shown in FIG. 2, the reflection buffer table is stored in the memory 22 inside the memory controller 20. The memory 22 is a flash memory or a RAM. As shown in FIG. 2 and Table 1, memory pages 000, 0, which are defective memory pages,
03, A02 and A03 are new memory pages FFC,
This is reflected in FFD, FFE, and FFF.

[0013]

[Table 1]

Step A3: Processing of page attributes: Within the reflection buffer table, the reflection address and the controller 21 provide a plurality of user-defined options. Options are available for defective memory pages or good memory pages. As shown in FIG. 2, the choices are read only,
Only one-time reading, two-time reading, and writing include one-time writing, two-time writing, address arrangement, and the like.

[0015]

[Table 2]

Step A4: When the setting process is completed, the system sets a quick page investigation table according to the result of the setting process, and stores it in the SRAM 23 as shown in FIG. As shown in FIG. 4, the quick page investigation table instructs the memory page 31 or the storage grid to execute in the normal access mode or the page operation mode.

The module of the 16M DRAM 30 has 3
096 have 4K memory pages 31 or storage grids. The size of the SRAM corresponds to the number of reflected memory pages (4K bits: 3096 bits),
The instruction is reflected in the memory page 31 of the DRAM 30, and the execution of the normal access mode or the page operation mode is instructed to the memory page. The operation process includes two reflection processes, and the first reflection class examines the quick page investigation table stored in the SRAM 23 as shown in FIG. 3 and step B1. As shown in step B2, when the bit designation of the SRAM 23 corresponding to the memory page 31 is 0, the memory page 31 executes the normal access mode. As shown in step B3, when the bit designation of the SRAM 23 of the memory page 31 having the second reflection level is 1, the memory page 31 executes the page operation mode and the system saves the data in the flash memory 22 in the controller 21. The reflected reflection buffer table is checked to confirm the page attribute and the actual reflection address.

[0018]

[Table 3]

Since the FPLT of page 000 is 1,
000 pages are error pages. If the user sets the page to read only or write only when there is no defect in the 008 page, the FPLT of the 008 page is also 1.

When a plurality of memory pages 31 are defective and cannot operate normally, as shown in Table 1, 000, 003,
The inspection result of the A02 and A03 memory pages becomes defective, the defective result is written to the flash memory 22, and the inspection result of the defective memory page 31 is loaded into the SRAM 23 when the computer system is input. A defect or defective portion of the memory page 31 can be quickly inspected by using a rapid page investigation table (FPLT) stored therein.

Since the access of the memory page 31 is a continuous cycling operation, the defective memory page is replaced by a normal memory page on the back of the DRAM 30, and as shown in Table 1, four memory pages are defective. You can confirm that. As shown in step B4, the defective memory page is replaced, and the reflection buffer table stores the addresses FFC, FF.
Instruct D, FFE and FFF to replace the normal memory page at the four addresses with the bad memory page.
That is, the memory page at address 000 is assigned to address F
Replace with the memory page of FC, replace the memory page of address 003 with the memory page of address FFD,
The memory page at address A02 is replaced with the memory page at address FFE, the memory page at address A03 is replaced with the memory page at address FFF, and the defective memory page is added to the backmost address of DRAM 30.
As shown in step B5, since there are four defective memory pages in the DRAM 30, the defective memory pages are replaced with normal memory pages, the memory controller 20 is sent to the total memory pages 31 of the computer system, and the defective memory pages are sent. The page is deleted, so that the next time the memory page 31 is accessed, the defective memory page is not accessed in a cyclic manner.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a conventional DRAM.

FIG. 2 is a schematic diagram showing a DRAM according to one embodiment of the present invention.

FIG. 3 is a flowchart illustrating a setting process of a method of operating a memory page of a DRAM according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating an operation process of a method of operating a memory page of a DRAM according to an embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 20 memory controller 21 controller 22 memory 23 SRAM 30 DRAM 31 memory page

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Go Kenji United States 94536, California, Fremont, Garybold Common, 38881 (72) Inventor Xu Xiuying, No. 32, No. 783, Ritsukoro, Taipei, Taiwan 7F F-term (reference) 5B018 GA04 GA10 HA21 HA40 JA21 KA01 MA06 NA02 QA13 5L106 AA01 CC01 CC14 CC21 CC32 DD12 GG05 GG07

Claims (10)

[Claims] 1. A method of operating a memory page of a DRAM having a setting process and an operating process, wherein the setting process inspects a memory and detects whether a memory page is defective. The setting of the reflection buffer table indicates a new position in which the position of the defect is reflected, and the position determination step of setting the wrong page anew, and the operation mode of the memory page inside the reflection buffer table. Defining a choice and processing a page attribute; and instructing whether the memory page or the storage unit performs processing in a normal access mode or a page operation mode, and setting a rapid page investigation table. The operating process includes the quick page survey table and the reflection buffer table. And replacing the defective memory page with a normal memory page in accordance with the records of these two tables, and adding the defective memory page to the backmost address of the memory. How it works. 2. The method as claimed in claim 1, wherein the step of testing the memory is performed by a basic input / output system (BIOS). 3. The method of claim 1, wherein the page attributes include options available for defective memory or normal memory. 4. The operating process, after performing the replacement of the defective memory page, a memory controller transmits to the computer system the number of the normal memory page reduced in the number of the defective memory page, 2. The method of claim 1, wherein when the memory page is accessed again, the defective memory page is not accessed. 5. The operation process includes a first-level reflection process and a second-level reflection process, and the second-level reflection process examines a bit reflected by a memory page of the quick page check table stored in the SRAM. 2. The method of claim 1, wherein an operation mode of the memory page is determined. 6. The first-class reflection process, wherein the bit is 0
6. The method of claim 5, wherein the memory page is in a normal access mode. 7. The second-class reflection process includes the step of:
Wherein the memory page is in a page operation mode, and the system checks a reflection buffer table stored in a flash memory in a controller to check page attributes and an actual reflection address. 6. The method for operating a memory page of a DRAM according to claim 5. 8. A system comprising: one or more DRAMs having a plurality of memory pages or storage grids; a controller having a memory for controlling and accessing said memory pages and storing therein a result of a setting process; And a memory controller having an instruction bit corresponding to the plurality of memory pages and having an SRAM instructing execution of a normal access mode or a page operation mode of the memory page. 9. The DRAM according to claim 8, wherein the memory is an erasable memory. 10. The DRAM of claim 8, wherein the capacity corresponds to the number of said memory pages reflected.