JP2002118240A - Semiconductor storage device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device wherein high level integration is made possible while adopting a gain cell structure. SOLUTION: This semiconductor storage device having a gain cell structure is provided with a semiconductor substrate, a trench which reaches a lower diffusion layer from a surface of the semiconductor substrate, a vertical type first transistor which is positioned along a side wall of the trench, a plane type second transistor which is positioned on the semiconductor substrate being adjacent to the trench, a diode positioned in the uppermost part of the trench, and a strap for connecting the diode and the second transistor. As the diode, e.g. a PN diode, a heterojunction diode, a Schottky diode, etc., can be used. Thereby a vertical type gain cell structure having two transistors and one diode can be realized, restraining the increase of occupation area per a unit cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device having a gain cell structure in which a signal characteristic is improved by using a diode, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, dynamic RAM (DRAM)
It is becoming difficult to secure the storage capacitance Cs of the cell capacitor with the miniaturization of the device. In a DRAM, a unit memory cell for storing 1-bit information has a 1T1C structure including one transistor and one capacitor. However, in order to secure the operation during the sensing operation and reduce the soft error rate, Regardless of the miniaturization of the memory cell, it is necessary to secure a storage capacitance Cs of a certain value or more. However, as the memory cell becomes finer, the storage capacity is limited even if a structure having a trench capacitor as shown in FIG. 7 is used, and a sufficient storage capacity cannot be secured.

Also, in order to prevent off-leakage of a cell transistor, junction leakage occurs when the impurity dose to the P-well is increased, which further reduces the accumulated charge and causes a malfunction.

[0004] For this reason, alternative devices having a new structure have been proposed. One of them is gain cell (gain cel)
l) There is a structure. As a gain cell, a normal DRAM
Various structures have been proposed, such as a device in which an element for amplifying the cell signal (Cs signal) is added, and a device in which an applied voltage and a current can be read at the time of reading by devising a circuit. These are ordinary 1T1C DRAMs
There is a problem that the number of elements increases as compared with the structure, which leads to an increase in the area and complexity of the structure.

As an example of a gain cell, a planar CMO
There is a planar gain cell manufactured by the S process (W.
H. Krautschneider, et.al. "Planar Gain Cell for Low
Voltage Operation and Gigabit Memories ", Symp.VLS
I tech., P140, 1995). In the planar gain cell, a unit cell is formed by two MOS transistors and one diode, and the transistor is formed by a planar transistor.

[0006]

FIG. 6 shows a cross-sectional shape and a planar shape of such a conventional planar gain cell. As shown in FIG. 6A, a transfer-side transistor Mtr and a storage-side transistor Mst are formed side by side in the same plane, and an n-type polysilicon 62 and a p-type A PN diode 65 composed of a laminate with a mold polysilicon 63 is formed. As described above, in a structure in which a PN junction is formed on the gate of one transistor Mst, it is difficult to match the formation process of the adjacent transistor Mtr and the transistors of the peripheral cells.

The titanium silicide (TiSi) strap 64 that connects the PN diode to the source / drain 61 of the adjacent transistor Mtr is formed by lithographic alignment, and alignment accuracy poses a processing problem.

Further, as shown in FIG. 6B, the transistor Mst on the storage side has an isolated remaining pattern, which causes a problem in processing the transistor gate using the lithography technique. In addition to the word line 68, a bit line node (contact) and a V _DD node (contact)
Wiring is required to connect to each other.
There is also a problem that the number of wirings is increased by one layer as compared with the above.

Therefore, a first object of the present invention is to replace the gain cell structure of a two-transistor one-diode with a conventional DRA.
It is an object of the present invention to provide a semiconductor memory device that can be realized without changing the structure of M or increasing the area.

A second object of the present invention is to provide a method of manufacturing a semiconductor memory device having a gain cell structure which eliminates the problem of matching with peripheral transistors and the adverse effect of misalignment.

[0011]

In order to achieve the first object, a semiconductor memory device having a gain cell structure according to the present invention comprises: a semiconductor substrate; a trench formed in the semiconductor substrate; Vertical first located along
A transistor, a planar second transistor located on the semiconductor substrate adjacent to the trench groove, a diode located at the top of the trench groove, and a strap connecting the diode and a diffusion region of the second transistor. .

The vertical first transistor is a storage-side transistor, which is a first diffusion region adjacent to the trench, a lower diffusion layer connected to the bottom of the trench, and a semiconductor material filled in the trench. And parts.

The planar-type second transistor includes, as a transfer-side transistor, a part of a word line extending in a first direction on a semiconductor substrate, and first and second diffusion regions located on both sides of the word line. . Among these, the first diffusion region adjacent to the trench is shared with the diffusion region of the first transistor.

The diode located at the top of the trench is
For example, a PN diode. In this case, the filling of the trench is a semiconductor material of the first conductivity type.
A second conductive material, opposite to the first conductive type, is formed on the conductive type semiconductor material.
The semiconductor device further includes a conductive semiconductor material.

[0015] The diode is also a heterojunction diode. In this case, the strap is a strap of a different kind of semiconductor material than the filling of the trench. A heterojunction is formed at the interface between the strap and the filling in the trench (that is, the interface between the different types of semiconductors), thereby forming a heterojunction diode.

The diode is also a Schottky diode. In this case, the strap is a metal strap. A Schottky junction is formed at the interface between the strap and the filling in the trench (metal-semiconductor interface) to form a Schottky diode.

This semiconductor memory device further includes a bit line connected to the second diffusion region of the planar second transistor and extending orthogonally to the word line.

Each unit cell of the semiconductor memory device having such a configuration has two transistors and one diode. One of the diodes is arranged vertically in the trench groove, and the diode is placed above the trench. Because of the layout, the area is almost the same as that of the conventional 1T1C type DRAM.
A gain cell structure excellent in signal performance can be realized.

By arranging a vertical transistor in the depth direction in the trench, a two-transistor, one-diode gain cell structure can be realized without increasing the unit cell area.

Further, the lower wiring connected to the lower portion of the trench can be used, and an extra wiring layer is not required.

By employing such a gain cell structure, a semiconductor memory device having excellent signal performance on a conventional DRAM scale is provided.

In order to achieve the second object, in a method of manufacturing a semiconductor memory device according to the present invention, a trench is formed in a semiconductor substrate to reach a lower diffusion layer. The trench is filled with a semiconductor material and a diode is formed at the top of the trench. Impurity is implanted into a predetermined position of the semiconductor substrate to form a first diffusion region adjacent to the trench groove, and a first diffusion region located on the same side of the trench groove as the first diffusion region and farther from the trench groove than the first diffusion region. Two diffusion regions are formed. A word line is formed on a substrate along a predetermined direction. The word line extends between the first diffusion region and the second diffusion region. After that, a strap connecting the diode and the first diffusion region is formed. Finally, a bit line connected to the second diffusion region and extending in a direction orthogonal to the word line is formed.

In the step of filling the trench, the semiconductor material of the first conductivity type is filled up to near the top of the trench,
The step of forming a diode forms a PN diode by filling a material of a second conductivity type opposite to the first conductivity type on the first conductivity type material.

Alternatively, the strap is formed of a semiconductor different from the semiconductor filled in the trench, and a heterojunction diode is formed at the interface between the strap and the filling in the trench.

Alternatively, the strap is formed of metal, and a Schottky diode is formed at the interface between the strap and the filling in the trench.

Thus, a semiconductor memory device having a 2T1D structure can be manufactured through substantially the same steps as those of the conventional DRAM manufacturing process.

The other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> FIG. 1 is a diagram showing a gain cell according to a first embodiment of the present invention, and FIG. 1 (a) shows a gain cell structure to be realized by the present invention. FIG. 1B is a cross-sectional view of the gain cell according to the first embodiment.

As shown in FIG. 1A, the gain cell is
Two transistors (transistor M on the transfer side)
tr and the storage-side transistor Mst) and one diode. As an operation of the 2T1D gain cell, at the time of writing, the transistor Mtr on the transfer side is turned ON and "0" and "1" are written as in the conventional DRAM, but the operation at the time of writing "1" is the same as that of the conventional DRAM. This is different from charge retention in a capacitor in a DRAM. That is, when a voltage is applied to the bit line BL, the diode becomes forward-biased and the storage-side transistor Mst
Is turned on. Once the storage side transistor Mst
Is turned on, VDD is always applied in the forward bias direction of the diode, and the ON state of the storage-side transistor Mst is maintained.

In the read operation, when reading "1", a ground potential is applied to the bit line. The electric charge accumulated in the gate of the storage-side transistor Mst turns on this transistor, a drain current obtained by subtracting the resistance from the storage-side transistor flows, and V is applied to the bit line BL.
The resistance drop of _DD is output. When reading “0”, the storage-side transistor Mst is OFF,
Zero output is read to the bit line BL.

In such a gain cell, V _DD is directly drawn out to the bit line, so that sufficient signal charges can be obtained, and the cell signal can have a margin.

FIG. 1B shows a diagram in which the 2T1D gain cell of FIG. 1A is realized in a trench type DRAM.

The gain cell type semiconductor device according to the first embodiment includes a semiconductor substrate 1, a trench 5 formed in the semiconductor substrate 1, and a vertical first transistor located along a side wall of the trench 5. A planar second transistor located on the semiconductor substrate adjacent to the trench 5, a diode located at the top in the trench 5,
A metal strap 16 is provided for connecting the diode to the diffusion region of the planar second transistor. The lower part of the trench 5 is a lower wiring (lower diffusion layer) connected to V _DD
14.

The first vertical type along the depth direction of the trench
The transistor is a storage-side transistor Mst. This first transistor has n
It is composed of a type diffusion region 11, a lower diffusion region connected to the V _DD node, and a part of a filling material (n-type polysilicon in the first embodiment) which forms an interface with the gate insulating film on the trench side wall.

The planar second transistor is a transfer-side transistor Mtr, and is composed of a part of the word line 8 and n-type diffusion layers 11 located on both sides thereof.

In the first embodiment, the diode located at the top of the trench is a PN diode, and the metal strap 16 is a TiSi strap. In order to form a PN diode at the uppermost part of trench groove 5, for example, n-type polysilicon 2 is filled inside trench groove 5, and p-type polysilicon layer 15 is arranged at the uppermost part.

The trench gain cell of the first embodiment shown in FIG. 1B has the following characteristics when compared with the conventional 1T1C trench DRAM shown in FIG. 7B.

(1) A p-type (or n-type) polysilicon 15 is buried in the upper part of the trench, and has a PN junction at an interface with the n-type (or p-type) polysilicon 2 inside the trench.

(2) Transfer-side transistor and PN
As a strap connecting the diode, the trench 5
And a n-type diffusion layer 11.

(3) A thin gate oxide film 18 is provided along a part of the trench sidewall, instead of the isolation collar oxide film 74 provided on the upper sidewall of the trench in the conventional trench DRAM.

The TiSi strap 16 is in contact with both the n-type silicon diffusion layer 11 of the transfer-side transistor (second transistor) and the p-type silicon layer 15 of the diode, and forms a good ohmic contact therewith.

In the vertical first transistor located along the trench side wall, a part of the trench side wall in the depth direction is used as a gate, so that a sufficient channel length can be obtained. As a result, the short channel effect can be prevented despite the miniaturization of the cell.

In such a trench type gain cell,
Unlike the planar gain cell shown in FIG. 6, the area per unit cell can be effectively reduced.

As a method of manufacturing such a vertical gain cell, first, a lower wiring (diffusion wiring) 14 is formed on a semiconductor substrate 1.
Is formed.

Next, n-type polysilicon 2 is deposited inside the trench by a CVD method, and the upper surface is planarized by CMP.
Etching is performed by RIE to a predetermined depth from the uppermost end of the trench groove. A p-type polysilicon 15 is deposited on the n-type polysilicon 2 in the trench, and is flattened by CMP.
The p-type polysilicon 15 is removed to the surface of the substrate 1 by RIE.

Thereafter, PEP (photo Engraving Processes)
s: photolithography step) and subsequent RIE to form shallow trenches. The shallow trench is buried with an oxide film such as SiO ₂ and the surface is polished by CMP to form an STI (shallow trench insulator: trench isolation insulating film). At this time, the mask material at the time of forming the trench 5 remains, which is used for filling the shallow trench and performing CMP.

Next, the mask material is removed, and a gate oxide film (not shown) is formed on the entire surface. An n-type impurity is ion-implanted into a predetermined region of the substrate 1 to form a diffusion region (source / drain) 1.
Form one. After that, a gate wiring material is deposited. This wiring material is subjected to PEP processing to simultaneously form a password line 8 ′ and a word line 8 extending in the first direction on the substrate 1.

Next, the n-type diffusion region 11 on the side adjacent to the trench 5 and the p-type polysilicon layer 1
5, a TiSi strap 16 is formed between the word line 8 and the password line 8 'in a self-alignment manner.

Finally, an interlayer insulating film is deposited to cover the word lines 8, 8 ', the TiSi strap 16, and the semiconductor substrate 1. A contact hole reaching the n-type diffusion region 11 far from the trench groove 5 is formed in the interlayer insulating film, and the hole is filled with tungsten or the like to form a plug (bit line contact) 17. Finally, the bit line 1 connected to the plug 17 and extending in the second direction orthogonal to the word line
0 is formed.

In this manufacturing method, the gate oxide film 18
It can be formed as part of the step of depositing n-type polysilicon 2 inside the trench groove. Therefore, FIG.
As compared with the conventional trench DRAM having the 1T1C structure shown in (b), the step of forming the trench side wall oxide film 74 is omitted, and instead, a step of re-burying the p-type polysilicon 15 into the trench is added, and Adjacent n-type diffusion layer 7
1 instead of the n-type polysilicon 72 covering
6 may be deposited. Therefore, a gain cell having a PN diode can be manufactured by a relatively easy process change.

Also, the password line 8 'can be formed by the recess of the polysilicon in the trench.
Unlike the conventional flat gain cell shown in (b), there is no need to form an isolated gate electrode pattern by lithography.

Further, in the conventional planar gain cell shown in FIG. 6, it is necessary to form a PN diode on the gate electrode of the storage-side transistor, and the PN diode is required to be compatible with the process of forming the transfer-side transistor Mtr and peripheral transistors. Although there is a problem, in the present invention, the diode is embedded inside the trench. Therefore, it is independent of the process of forming the transistor Mtr on the transfer side and the peripheral transistors, and there is no problem of matching.

In addition, when the TiSi strap 16 is formed, it can be formed by self-alignment between the gate electrode (word line 8) of the transfer-side transistor and the password line 8 '. Therefore, unlike the conventional flat gate cell of FIG. 6B, alignment by lithography is not required, and the adverse effect of misalignment can be eliminated.

<Second Embodiment> FIG. 2 is a sectional view of a gain cell according to a second embodiment of the present invention. In the second embodiment, a heterojunction diode or a Schottky diode is used instead of the PN diode of the first embodiment. That is, the necessity to bury polysilicon 15 of a different conductivity type (for example, p-type) in the upper portion of the trench is omitted,
The trench is filled with only one conductivity type polysilicon. A strap 17 of a heterogeneous semiconductor or metal layer is provided for this polysilicon.

When the strap 17 is formed of, for example, SiC (silicon carbide) which is an IV-IV compound, the interface between the polysilicon 2 and the strap 17 inside the trench groove is formed as follows.
A heterojunction diode is formed. In this case, the strap 17 connects the heterojunction diode and the transfer transistor Mtr.

When the strap 17 is made of metal,
A metal-semiconductor Schottky diode is formed at the interface between the strap and silicon. It has been known that, in a metal-silicon contact, the barrier height changes depending on the dose on the silicon side. A Schottky junction is formed between the strap 17 and the polysilicon inside the trench, and the strap 17 is connected to the transfer side. It is necessary to set the impurity dose so as to form an ohmic junction with the transistor.

For example, the inside of the trench may be made of p-type polysilicon to easily form a Schottky junction with the strap 17, and the source / drain 11 of the transfer-side transistor may be made n-type to form an ohmic junction. Alternatively, a Schottky junction may be formed by using n-type polysilicon inside the trench, and the source / drain 11 of the transfer-side transistor may be made n ⁺ type to form an ohmic junction. Further, the Schottky junction and the ohmic junction may be reversed.

As with the first embodiment, such a gain cell can realize a gain cell in which one element is added without increasing the area per cell.

Further, compared with the first embodiment, the step of re-burying the trench for the PN junction can be omitted.

Third Embodiment A third embodiment provides a semiconductor memory device having a gain cell structure, in which a folded sense amplifier and a password line associated therewith are omitted.

FIG. 3A is a plan view of a semiconductor memory device having a gain cell structure according to the third embodiment, and FIG. 3B is a cross-sectional view taken along line AA of FIG. 3A. In the third embodiment, as in the first embodiment, a PN diode is provided above the trench groove, and a vertical storage-side transistor is provided along the side wall of the trench groove. Except for omitting the password line, the other configuration is the same as that of the first embodiment, and the description is omitted.

In a conventional DRAM, as shown in FIG.
Two bit lines 79 are connected to one sense amplifier S / A in a folded structure, and the word line potential varies (noise).
Is equally distributed to the two bit lines, thereby canceling the noise between the bit lines. This is because a conventional D signal is used to detect and amplify a small signal voltage from a memory cell.
This is a configuration required for the RAM. At this time, when one word line is selected, adjustment is performed using the password line 78 'so that data is not output to both bit lines connected to the folded sense amplifier.

On the other hand, in the present invention, since the gain cell structure is employed, a margin is generated in the cell signal, and the noise is relatively small. Therefore, the folded sense amplifier becomes unnecessary, and the password line can be omitted.

Since the storage-side transistor and the diode are formed inside the trench as in the first embodiment, it is necessary to form an isolated gate pattern unlike the conventional planar gain cell shown in FIG. 6B. Absent. There is an advantage that the area of the cell itself can be reduced, while the area of the strap 36 on the trench side can be sufficiently increased.

<Fourth Embodiment> FIG. 4 shows a semiconductor memory device according to a fourth embodiment of the present invention. FIG. 4 (a)
FIG. 4B is a plan view in which bit lines extending perpendicularly to the word lines are omitted in the upper layer of the word lines 48 in order to make the cell arrangement easy to see, and FIG. 4B is a plan view in which the bit lines 49 are drawn.

In this layout, with a cell size of 8F ² (2F × 4F) generally used in a DRAM,
A layout offset by a half pitch can be used as it is. Here, F represents the minimum dimension of processing. The layout is such that a folded sense amplifier (not shown) and a password line can be used.

The half-pitch layout can increase the cell density, so that the degree of integration of the semiconductor memory can be improved. In the layout of FIG. 4, one bit line contact 47 is shared by two adjacent cells to further increase the degree of integration.

In FIG. 4, a trench 45 shown by an oval is shown.
A storage-side transistor having the structure shown in FIG. 1 or FIG. 2 is formed therein, and a PN diode, a heterojunction diode, or a Schottky diode above the trench is connected to a transfer-side transistor (not shown) by a strap 46. . One source / drain of the transfer transistor is connected to a bit line contact 47.

In the layout of the fourth embodiment, the gain cell structure can be applied as it is to the 1/2 pitch layout of the conventional 1T1C DRAM, and it is possible to improve the signal quality while keeping the occupied area.

<Fifth Embodiment> FIG. 5 shows a semiconductor memory device according to a fifth embodiment of the present invention. FIG. 5 (a)
FIG. 5B is a plan view in which bit lines extending perpendicularly to the word lines are omitted in a layer above the word lines 58 so as to make the cell arrangement easy to see, and FIG. 5B is a plan view in which the bit lines 59 are drawn.

The fifth embodiment has a layout in which the folded sense amplifier and the password line are omitted with the improvement of the cell signal by the gain cell structure. In this layout, one side of the strap 56 is formed in a self-aligned manner with the word line 58, and the other side (trench side) does not require relatively high alignment accuracy, so that the alignment margin is increased and the workability is improved. It has the advantage that.

Also in the fifth embodiment, the storage-side transistor is formed in the vertical direction in the trench 55, and the diode above the trench may be any one of a PN diode, a heterojunction diode, and a Schottky diode. .

[0073]

As described above, according to the semiconductor memory device of the present invention, the gain cell structure, which is difficult to realize due to the increase in the number of elements and the number of wirings, has a structure similar to that of a conventional DRAM by utilizing a trench groove structure. Thus, it can be realized without increasing the area.

Further, according to the method of manufacturing a semiconductor memory device of the present invention, a semiconductor memory device having a gain cell structure can be manufactured through substantially the same manufacturing process as that of a conventional DRAM.

[Brief description of the drawings]

FIG. 1 is a sectional view of an equivalent circuit of a gain cell realized by the present invention and a vertical gain cell according to a first embodiment for realizing the equivalent circuit.

FIG. 2 is a sectional view of a vertical gain cell according to a second embodiment of the present invention.

FIG. 3 is a plan layout of a semiconductor memory device having a gain cell structure according to a third embodiment of the present invention, and a cross-sectional view of a vertical gain cell used in the semiconductor memory device.

FIG. 4 is a plan layout of a semiconductor memory device having a gain cell structure according to a fourth embodiment of the present invention.

FIG. 5 is a plan layout of a semiconductor memory device having a gain cell structure according to a fifth embodiment of the present invention.

FIG. 6 is a cross-sectional view and a plan view showing a structure of a conventional planar gain cell.

FIG. 7 is a plan layout and a cell cross-sectional view of a conventional 1T1C DRAM.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 n-type polysilicon 3 p-type polysilicon 5, 45, 55 trench groove 8, 38, 48, 58 word line 10, 39, 49, 59 bit line 11, 31 n-type diffusion region (source / drain) 13, 33, 42 STI insulating film 14 _VDD node (lower diffusion layer) 15 p-type polysilicon 16, 36, 46, 56 strap 17, 37, 47, 57 bit line contact 18 gate insulating film

Claims (15)

[Claims] A semiconductor substrate; a lower diffusion layer in the semiconductor substrate; a trench extending from the surface of the semiconductor substrate to the lower diffusion layer; and a first vertical transistor positioned along a sidewall of the trench. A planar second transistor located on the semiconductor substrate adjacent to the trench, a diode located at the top of the trench, and a strap connecting the diode and the second transistor. Semiconductor storage device. 2. The semiconductor device according to claim 1, further comprising a word line extending in a predetermined direction on the semiconductor substrate, wherein the planar second transistor has a first diffusion region adjacent to the trench on one side of the word line, and a word line. 2. The semiconductor memory device according to claim 1, further comprising a second diffusion region located on the opposite side of the first diffusion region with respect to the first diffusion region. 3. The semiconductor memory device according to claim 2, further comprising a bit line connected to a second diffusion region of said second transistor and extending in a direction orthogonal to said word line. 4. The semiconductor memory device according to claim 1, wherein said diode is a PN diode. 5. The trench according to claim 1, wherein the trench is filled with a semiconductor material of a first conductivity type to a portion near an uppermost portion of the trench.
2. The semiconductor memory device according to claim 1, wherein an uppermost portion of the trench is charged with a second conductive material opposite to the conductivity type. 6. The semiconductor memory device according to claim 1, wherein said diode is a heterojunction diode. 7. The semiconductor memory device according to claim 1, wherein the trench is filled with a semiconductor material, and the strap is formed of a semiconductor material different from the semiconductor material. 8. The semiconductor memory device according to claim 1, wherein said diode is a Schottky diode. 9. The semiconductor memory device according to claim 1, wherein the trench is filled with a semiconductor material, and the strap is formed of a metal. 10. The semiconductor memory device according to claim 1, further comprising a gate insulating film in a part of a side wall of said trench along a depth direction. 11. forming a trench in the semiconductor substrate to reach the lower diffusion layer; filling the trench with a semiconductor material; forming a diode on an uppermost portion of the trench; A first diffusion region adjacent to the trench groove at a predetermined position on the substrate; and a second diffusion region further away from the trench groove than the first diffusion region on the same side of the trench groove as the first diffusion region. Forming a word line extending in a predetermined direction on the substrate; forming a strap connecting the diode and the first diffusion region on the semiconductor substrate; Forming a bit line connected to the second diffusion region and extending in a direction orthogonal to the word line. 12. The step of filling the trench groove includes filling the trench with a semiconductor material of a first conductivity type to a position near an uppermost portion of the trench groove. Converse second
12. The method of claim 11, further comprising: filling a conductive semiconductor material. 13. The step of forming the strap includes forming the strap with a semiconductor material different from the semiconductor material filling the trench, and forming a strap at an interface with the semiconductor material filling the trench. The method according to claim 11, wherein a junction is formed. 14. The method of claim 11, wherein forming the strap comprises forming a strap with metal, and forming a Schottky junction at an interface with a semiconductor material filled in the trench. 6. The method for manufacturing a semiconductor memory device according to claim 1. 15. The word line forming step forms a password line extending in parallel with the word line together with the word line, and the strap forming step includes a step of self-aligning a strap between the word line and the password line. The method according to claim 11, wherein the semiconductor memory device is formed.