JP2002118200A - Semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package capable of executing a test by easily connecting the package to a test pin even after mounting on a board while preventing an increase in size. SOLUTION: The semiconductor package comprises a plurality of first external pads 16 arranged in an array-like state to supply signals to a silicon chip 13. The package further comprises a second external pad 24 to be supplied with a test signal to test the chip 13, and formed on the surface in the same direction as that of the pads 16 and in a height capable of inserting a probe pin for a test different from the pads 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a surface mount type semiconductor package capable of performing an operation test before and after mounting on a substrate.

In recent years, electronic devices such as personal computers, mobile phones, and portable information terminals have been reduced in thickness and size. Accordingly, semiconductor devices used in these electronic devices are:
BGA has been reduced in size and packaging density has been increased.
Surface-mounted packages of substantially the same size as semiconductor chips, such as (Ball Grid Array) and LGA (Land Grid Array), have been used.

In general, various tests are performed on a semiconductor device before the product is shipped, and those that pass the test are shipped as a product. In addition, with the advancement of functions in recent years, a test of a semiconductor device is required even after mounting on a substrate. For this reason, even in a surface mount type package, it is required to easily perform a test after mounting on a substrate.

[0004]

2. Description of the Related Art Conventionally, various semiconductor devices have been proposed in which test pins are provided on a package for testing before product shipment.

For example, Japanese Unexamined Patent Application Publication No. 9-22929 discloses that a test pad electrically connected to each terminal of a semiconductor chip in a one-to-one manner is provided on a substrate on which the semiconductor chip is mounted. A provided BGA package semiconductor device is disclosed. The test pad is provided on the surface on which the solder ball is formed or on the surface opposite to the surface, and enables an electrical characteristic test to be performed without causing appearance defects such as scratches, dents, and defects in the solder ball.

However, in a package in which test pads are provided on a surface on which solder balls are formed, a test probe pin cannot be brought into contact with the test pads after the package is mounted on the board, so that a test cannot be performed after the board is mounted. On the other hand, a package in which test pads are provided on the surface opposite to the surface on which the solder poles are formed can be subjected to a test after mounting on the board. However, as the size of the internal circuit of the semiconductor device increases, the number of solder balls increases accordingly. For this reason, forming the test pads one-to-one with the solder balls increases the area of the semiconductor chip and cannot reduce its size.

Japanese Unexamined Patent Application Publication No. 11-354677 discloses a package that allows probing of solder balls after mounting on a substrate. In this package, a semiconductor chip (LSI) is mounted on an upper surface of a substrate, a plurality of solder balls are arranged in a matrix on a lower surface, and each solder ball is connected to the semiconductor chip through a plurality of current-carrying portions provided inside the substrate. The power is on. A hole is formed on at least one side of the substrate and communicates with a plurality of current-carrying portions inside the substrate. A contact rod for inspection is inserted into this hole, and the tip thereof is brought into contact with each current-carrying portion.
Thereby, even after the package is mounted on the substrate, the probing can be freely performed on the solder balls.

[0008]

However, since a hole into which the contact rod can be inserted must be formed in the substrate, there is a problem that the package becomes large with the increase in the number of pins. In addition, since a contact rod is inserted into the hole to make contact with each of the conductive portions, there is a problem that it is difficult to make a reliable contact with a target terminal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor package which can be connected to a test pin even after mounting on a substrate and can be easily tested, while preventing an increase in size. Is to provide.

[0010]

According to a first aspect of the present invention, there is provided a semiconductor device having a plurality of first terminals arranged in an array to supply signals to a semiconductor substrate. In a surface-mount type semiconductor package in which a first terminal is formed on a surface facing a surface of a substrate on which the package is mounted, a second terminal to which a test signal for testing the semiconductor substrate is supplied is connected to the first terminal. And a height different from that of the first terminal. Therefore, in the test before mounting on the substrate, the first terminal and the second terminal
The signal probe pins and the test probe pins can be brought into contact with the terminals from the same direction.

According to a second aspect of the present invention, a step is provided between a lower surface of a peripheral portion of the package and a lower surface of a portion inside the package, and the first terminal is formed on a lower surface of the inner portion. Two terminals were formed on the lower surface of the peripheral portion. Therefore, the height (step) of the first and second terminals can be easily set.

According to a third aspect of the present invention, the second
The height of the terminal is a height at which a test probe pin for supplying the test signal after mounting on the board can be inserted. Therefore, the test probe pins can be easily brought into vertical contact with the second terminals after the board is mounted.

According to a fourth aspect of the present invention, the first
Are formed on a lower surface of a package substrate for fixing the semiconductor substrate, a molding material for sealing the semiconductor substrate is formed larger than the package substrate, and the second terminal is exposed from a lower surface of the molding material. Formed. Therefore, the first and second terminals having different heights can be easily formed.

According to a fifth aspect of the present invention, an internal circuit and a test circuit for testing the internal circuit are formed on the semiconductor substrate, and the first terminal is connected to the internal circuit. The second terminal is connected to the test circuit. Therefore, there is no need to provide a test terminal connected to the first terminal, thereby preventing an increase in the size of the package.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1A is a sectional view of a semiconductor package according to the present embodiment, and FIG. 1B is a bottom view thereof.

The semiconductor package 10 is formed in a substantially square plate shape, and a step is provided between the lower surface of the central portion and the lower surface of the peripheral portion by making the peripheral portion thinner than the central portion. still,
In the present embodiment, the semiconductor package 10 includes an upper layer portion 11.
And a lower layer portion 12 having a smaller horizontal shape.

The upper portion 11 includes a silicon chip 13 and a molding material 14 for sealing the same, and the lower portion 12
Includes a package substrate 15. The package substrate 15 has a planar shape slightly larger than the silicon chip 13, and the molding material 14 has a planar shape slightly larger than the package substrate 15.

The package substrate 15 is made of an insulator, and has a plurality of first pins as signal pins arranged in a lattice on the lower surface thereof.
External pads 16 are formed. The plurality of first external pads 16 are connected to a plurality of internal pads 17 formed on the upper surface of the package substrate 15 via a plurality of through holes 18, respectively.

An insulating layer 19 is formed at the center of the upper surface of the package substrate 15 so as to cover (embed) the plurality of internal pads 17, and a silicon chip 13 is formed on the insulating layer 19.
Are fixed by the bonding paste 20.

A stage 21 is provided on the upper surface of the package substrate 15. The stages 21 are arranged along the periphery of the package substrate 15, and the number thereof is larger than the number of the first external pads 16.

Each stage 21 is connected to a bonding pad 23 formed on the upper surface of the silicon chip 13 via a bonding wire 22. The bonding pads 23 are arranged on the periphery of the chip 13 and are connected to an internal circuit 31 and a test circuit 32 (see FIG. 3) built on the upper side of the chip 13.

A plurality of stages 21 are connected to internal pads 17 via a pattern (not shown) formed on the upper surface of package substrate 15. In this way,
The internal circuit formed in the silicon chip 13 is electrically connected to the first external pad 16 via the bonding wire 22, the stage 21, the internal pad 17, and the through hole 18.

Some of the stages 21 not connected to the internal pads 17 (eight in this embodiment,
A second external pad 24 as a test pin is connected to the stage connected to the test circuit). Each of the second external pads 24 is embedded in the molding material 14 such that the lower surface of the tip portion is exposed at a predetermined position.

Therefore, the semiconductor package 10 has the first external pad 16 connected to the internal circuit 31 of the silicon chip 13 and the second external pad 24 connected to the test circuit 32 of the chip 13. The heights of the first and second external pads 16 and 24 are different.

Next, mounting of the semiconductor package 10 configured as described above will be described. As shown in FIG. 2, a plurality of lands (not shown) corresponding to the plurality of first external pads 16 are formed on the mounting surface of the substrate 41, and a predetermined amount of the solder paste 42 is supplied on the lands. Then, after mounting the semiconductor package 10 on the substrate 41, the solder paste 42 is melted by reflow, and the first land is formed on the land.
The external pads 16 are soldered.

Next, an operation test of the semiconductor package 10 will be described.
This will be described with reference to FIGS. FIG. 3 is a block diagram showing connections at the time of testing the semiconductor package 10.

In a test before board mounting such as before shipping, as shown in FIG. 3A, the first and second external pads 16 and 24 of the semiconductor package 10 are connected to a first inspection device 51. You.

The first inspection device 51 has a test head (measurement socket) 52 shown in FIG. The test head 52 includes a socket 53, a first probe pin 54 for a plurality of signal pins, and a second probe pin 55 for a test pin. The first probe pins 54 are arranged in an array, and the first external pads 1
Touch 6. The second probe pins 55 are formed longer than the first probe pins 54 by the steps of the first and second external pads 16 and 24 of the semiconductor package 10, and come into contact with the second external pads 24. That is, by changing the length of the first and second probe pins 54 and 55,
They are in contact with the first and second external pads 16 and 24 at the same time.

The inspection device 51 includes an internal circuit 31 and a test circuit 32 through the first and second external pads 16 and 24.
To the internal circuit 31 and the test circuit 3
The quality of the semiconductor package 10 is determined based on the signal received from the semiconductor package 10.

As described above, the first and second signals for supplying signals are provided.
Since the external pads 16 and 24 are provided in the same direction of the semiconductor package 10, the first probe pins 54 connected to the first external pads 16 and the second probe pins 55 connected to the second external pads 24 are provided. Can be contacted from the same direction, and only one test head 52 needs to be provided, so that the configuration of the inspection device 51 can be simplified and the inspection cost can be reduced. This is the second
When the external pads 24 are formed on the side surface or the upper surface of the package 10, a test head is required separately from the test head having the first probe pins 54 to connect the second probe pins to them. Or, a test head (measurement socket) having a complicated shape is required, which increases the inspection cost.

Incidentally, with respect to a normal semiconductor package in which the second external pad 24 as a test pin is omitted,
The test of the internal circuit 31 can be performed using the test socket of FIG. This is because the arrangement of the first external pads 16 does not change, and the inspection cost is reduced. In the case of a conventional normal package, if the test pads are omitted, the arrangement of signal pins for supplying signals to the internal circuit is changed, or the outer dimensions of the package are changed (reduced), and the arrangement of signal pins is reduced. Is changed. This requires a test head (measurement socket) having a different shape from that of a test head (measurement socket) for testing a package having test pins, and increases the inspection cost.

In the test after mounting on the board, FIG.
1, the first and second external pads 16 and 24 of the semiconductor package 10 are connected to a second inspection device 56. The second inspection device 56 includes a test head 57 shown in FIG. The test head 57 includes a socket 58,
Probe pins 5 for a plurality of test pins suspended therefrom
9 is comprised. The probe pin 59 is formed in a substantially fishhook shape, and the tip of the probe pin 59 is in the upper layer portion 1 of the semiconductor package 10.
It is formed so as to be able to be inserted into the gap between 1 and the substrate 41. The plurality of probe pins 59 are arranged so as to be in contact with the second external pad 24. The test head 57 is configured to be urged vertically upward by, for example, a spring or the like, so that the probe pin 59 contacts the second external pad 24 with a predetermined pressure. As a result, the probe pins 59 are reliably brought into contact with the second external pads 24.

The second inspection device 56 supplies a test signal to the test circuit 32 via the second external pads 16 and 24, and judges the quality of the internal circuit 31 based on the signal received from the test circuit 32.

The test circuit 32 mounted on the silicon chip 13 of FIG. 1 is connected to the first and second inspection devices 51 and 56.
A circuit for performing a so-called built-in self-test that generates a signal for performing a self-diagnosis of the internal circuit 31 in response to a test mode signal received from the controller may be used.

As described above, the present embodiment has the following advantages. (1) a plurality of first external pads 16 arranged in an array to supply signals to the silicon chip 13;
The second external pad 24 to which a test signal for testing the silicon chip 13 is supplied is connected to the first external pad 16
And at a height different from that of the first external pad 16. As a result, in the test before mounting on the board, the signal probe pin and the test probe pin can be brought into contact with the first external pad 16 and the second external pad 24 from the same direction. Therefore, the configuration of the test head 52 is simplified, and the inspection cost can be reduced.

(2) A step is provided between the lower surface of the peripheral portion of the semiconductor package 10 and the lower surface of a portion inside the semiconductor package 10, the first external pad 16 is formed on the lower surface of the inner portion, and the second external pad 24 is connected to the peripheral portion. Formed on the lower surface. As a result, the height (step) of the first and second external pads 16 and 24 due to the step
Can be easily set.

(3) The height of the second external pad 24 is such that a test probe pin 59 for supplying a test signal after mounting on the board can be inserted. As a result, the test probe pins 59 can be easily vertically and easily contacted with the second external pads 24 after the board is mounted.

(4) The first external pads 16 are formed on the lower surface of the package substrate 15 on which the silicon chip 13 is fixed.
The molding material 14 for sealing the silicon chip 13 was formed larger than the package substrate 15, and was formed such that the second external pad 24 was exposed from the lower surface of the molding material 14. As a result, the first and second external pads 16 and 24 having different heights can be easily formed.

(5) The silicon chip 13 has an internal circuit 3
1 and a test circuit 32 for testing the internal circuit 31 thereof, the first external pad 16 is connected to the internal circuit 31, and the second external pad 24 is connected to the test circuit 3
2 are connected. As a result, the first external pad 16
There is no need to provide external test pads connected to
An increase in the size of the semiconductor package 10 can be prevented.

(6) Since the second external pads 24 for testing are provided on the lower surface of the semiconductor package 10, foreign substances and the like can be prevented from adhering to the second external pads 24 after mounting on the substrate.

The above embodiment may be modified as follows. In the above embodiment, the silicon chip 13 is mounted face-up with the surface on which the semiconductor integrated circuit is formed facing up, but the so-called face-up where the surface on which the semiconductor integrated circuit is formed is positioned on the package substrate 15 side. The present invention may be embodied in a semiconductor device mounted down. In this case, since the pad 23 is connected to the stage 21 via a bump or the like, the size of the package substrate 15 and thus the size of the semiconductor package 10 can be further reduced.

In the above embodiment, the semiconductor package 1
0 is embodied in an LGA package, but as shown in FIG. 6, B in which balls 61 connected to the substrate are arranged in an array.
The present invention may be embodied in another surface mount package such as a GA package 60 and the like.

In the above embodiment, a high-density wiring board such as a printed wiring board or a build-up wiring board may be used for the package substrate 15, so that a semiconductor package having more pins can be handled.

In the above embodiment, the planar shape of the upper layer portion 11 may be changed according to the place where the second external pad 24 for testing is provided.
The side where no 4 is provided may be formed substantially the same as the side of the package substrate 15. Further, the shape of the upper layer portion 11 may be changed as appropriate, for example, to a trapezoidal cross section, or the like.

In the above embodiment, the number of the second external pads 24 for supplying a test signal is set to at least one.
Any number may be set. In the above embodiment, the arrangement of the first external pads 16 as signal pins may be changed to an arbitrary arrangement such as a houndstooth check. Also, in FIG. 1B, the shape of the first external pad 16 is shown as a square,
The shape may be changed to an arbitrary shape such as a square shape. Similarly, the shape of the second external pad 24 may be arbitrarily changed.

[0046]

As described in detail above, according to the present invention,
It is possible to provide a semiconductor package that can be easily connected to a test pin and tested after mounting on a substrate while preventing an increase in size.

[Brief description of the drawings]

FIG. 1 is a schematic view illustrating a semiconductor package according to an embodiment.

FIG. 2 is an explanatory view of mounting on a substrate.

FIG. 3 is a block diagram showing connections at the time of inspection.

FIG. 4 is an explanatory diagram of an inspection before mounting on a substrate.

FIG. 5 is an explanatory diagram of an inspection after mounting on a substrate.

FIG. 6 is a cross-sectional view of another semiconductor package.

[Explanation of symbols]

 Reference Signs List 10 semiconductor package 13 semiconductor substrate 14 molding material 15 package substrate 16 first terminal 24 second terminal 31 internal circuit 32 test circuit 55 test probe pin

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA00 AK01 AK02 AL00 4M109 AA01 BA04 CA21 DA01 DA03 DA10 DB15 DB16

Claims (5)

[Claims] 1. A semiconductor device comprising: a plurality of first terminals arranged in an array to supply signals to a semiconductor substrate; wherein the first terminals are formed on a surface facing a surface of a substrate on which a package is mounted; In the surface-mount type semiconductor package, a second terminal to which a test signal for testing the semiconductor substrate is supplied may be on a surface in the same direction as the first terminal and at a different height from the first terminal. A semiconductor package characterized by being formed. 2. A step is provided between a lower surface of a peripheral portion of the package and a lower surface of a portion inside the package, the first terminal is formed on a lower surface of the inner portion, and the second terminal is formed on a lower surface of the peripheral portion. The semiconductor package according to claim 1, wherein the semiconductor package is formed. 3. The semiconductor package according to claim 1, wherein the height of the second terminal is a height at which a test probe pin for supplying the test signal after mounting on a substrate can be inserted. . 4. The semiconductor device according to claim 1, wherein the first terminal is formed on a lower surface of the package substrate for fixing the semiconductor substrate, and a molding material for sealing the semiconductor substrate is formed larger than the package substrate. The semiconductor package according to claim 1, wherein the second terminal is formed so as to expose the second terminal. 5. The semiconductor substrate according to claim 1, wherein an internal circuit and a test circuit for testing the internal circuit are formed on the semiconductor substrate.
5. The semiconductor package according to claim 1, wherein the terminal is connected to the internal circuit, and the second terminal is connected to the test circuit. 6.