JP2002118140A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2002118140A
JP2002118140A JP2000307271A JP2000307271A JP2002118140A JP 2002118140 A JP2002118140 A JP 2002118140A JP 2000307271 A JP2000307271 A JP 2000307271A JP 2000307271 A JP2000307271 A JP 2000307271A JP 2002118140 A JP2002118140 A JP 2002118140A
Authority
JP
Japan
Prior art keywords
pads
pad
semiconductor chip
inspection
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000307271A
Other languages
Japanese (ja)
Inventor
Masami Funabashi
正美 船橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000307271A priority Critical patent/JP2002118140A/en
Publication of JP2002118140A publication Critical patent/JP2002118140A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor bare chip which enables minimizing the area and suppress a crosstalked noise that generates between adjacent I/O pads due to the miniaturization of the semiconductor chip. SOLUTION: I/O pads 210, 211, which are required for practical use, are placed so that they meet the wire arrangement rules of a substrate to be mounted, and test I/O pads 220, 221 are placed between 210 and 211. The number of I/O pads that can be placed is decided by the equation: (the number of placeable pads)=(Dpad-Ypad-B)÷(Ypad+B).

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体チップを基
板上に高密度にベアチップ実装するための半導体装置に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for mounting a semiconductor chip on a substrate at a high density with bare chips.

【０００２】[0002]

【従来の技術】近年、半導体チップの高機能化が進んで
いる。また、半導体を搭載する機器等もますます高性能
・多機能を要求されている一方、更なる小型・軽量化が
求められている。それに伴い、半導体チップもさらなる
高性能かつ面積の縮小化、基板への高密度な実装が要求
されている。2. Description of the Related Art In recent years, the functions of semiconductor chips have been advanced. In addition, while devices and the like on which semiconductors are mounted are increasingly required to have high performance and multiple functions, further reductions in size and weight are required. Along with this, semiconductor chips are also required to have higher performance, smaller area, and higher density mounting on substrates.

【０００３】従来は、より小さな、より薄型パッケージ
を用いることで、基板への高密度実装に対応してきた。
しかし、近年では携帯機器をはじめとして、半導体を搭
載する機器の更なる小型・軽量化が求められている。Conventionally, a smaller and thinner package has been used to support high-density mounting on a substrate.
However, in recent years, there has been a demand for further reduction in size and weight of devices including semiconductors, including portable devices.

【０００４】こうした背景から半導体チップの実装方法
は、より集積度の高いベアチップ実装が用いられるよう
になってきた。この実装方法の場合、半導体チップの面
積が実装面積に反映する。[0004] From such a background, a mounting method of a semiconductor chip has come to use a bare chip mounting with a higher degree of integration. In the case of this mounting method, the area of the semiconductor chip reflects on the mounting area.

【０００５】半導体チップ面積の縮小を実現するには、
内部面積の縮小とＩ／Ｏパッドの縮小や高密度な配置が
考えられる。実装基板へ半導体チップを高密度に実装す
る方法としては、ベアチップを直接基板上に実装する方
法が用いられている。この方法は、ベアチップのＩ／Ｏ
パッドと実装基板の配線とを直接電気的に接続をするも
のである。In order to reduce the semiconductor chip area,
Reduction of the internal area, reduction of the I / O pad, and high-density arrangement are conceivable. As a method of mounting a semiconductor chip on a mounting substrate at a high density, a method of directly mounting a bare chip on a substrate is used. This method uses bare chip I / O.
The pad and the wiring on the mounting board are directly electrically connected.

【０００６】この実装方法を実現するためには、半導体
チップの隣接するＩ／Ｏパッドとの間隔を実装基板の配
線ルールに合わせる必要があった。In order to realize this mounting method, it is necessary to match the distance between adjacent I / O pads of the semiconductor chip with the wiring rules of the mounting substrate.

【０００７】しかし、実装基板の配線間の距離は、隣接
する半導体チップのＩ／Ｏパッド間の距離と比較して広
いものである。従来は、図３のように実装基板側の配線
ルールに従い実使用上必要なＩ／Ｏパッド３１０〜３１
６を配置していた。実装基板の配線間隔は、実使用上必
要なＩ／Ｏパッド３１０〜３１６の配置間隔よりも広
い。However, the distance between the wirings of the mounting board is wider than the distance between the I / O pads of adjacent semiconductor chips. Conventionally, as shown in FIG. 3, I / O pads 310 to 31 actually required according to the wiring rules on the mounting board side.
6 had been arranged. The wiring interval of the mounting board is wider than the arrangement interval of the I / O pads 310 to 316 necessary for practical use.

【０００８】本来、Ｉ／Ｏパッドはプリント配線の間隔
に比べて十分に狭く高密度に配置できるのだが、ベアチ
ップ実装を行う場合はプリント配線のルールの制約を受
け、Ｉ／Ｏパッドを配置する面積は余計に必要となって
いた。また、半導体チップの製造工程には検査工程が不
可欠であり、検査用のＩ／Ｏパッドも同一半導体チップ
上に実使用上必要なＩ／Ｏパッドとは他に設ける必要も
あった。Originally, the I / O pads are sufficiently narrower than the intervals between the printed wiring lines and can be arranged at a high density. However, when a bare chip is mounted, the I / O pads are arranged due to the restrictions of the rules of the printed wiring lines. More area was needed. In addition, an inspection process is indispensable in the manufacturing process of the semiconductor chip, and it is necessary to provide an I / O pad for inspection on the same semiconductor chip in addition to an I / O pad actually required.

【０００９】また、半導体チップのさらなる微細化に伴
い隣接するＩ／Ｏパッドの間隔も狭くなっている。速い
周波数で動作する半導体チップの場合、隣接するＩ／Ｏ
パッドの入出力信号がお互いに影響しあい、クロストー
クノイズの発生という問題が生じる。一般的にクロスト
ークノイズ対策としては、実使用上必要なＩ／Ｏパッド
の配置間隔を広げて配置する。または、その間にＬ固
定、もしくはＨ固定の信号を流す配線（または、Ｉ／Ｏ
パッド）をおくことにより対応している。[0009] Further, with further miniaturization of semiconductor chips, the distance between adjacent I / O pads has also been reduced. In the case of a semiconductor chip operating at a high frequency, adjacent I / O
The input / output signals of the pads affect each other, causing a problem of generation of crosstalk noise. In general, as a countermeasure against crosstalk noise, an arrangement interval of I / O pads necessary for practical use is widened. Alternatively, a wiring (or an I / O
(Pad).

【００１０】しかし、これも半導体チップの面積を有効
に活用できないために、半導体チップの面積縮小化にお
いて問題となってくる。However, this also causes a problem in reducing the area of the semiconductor chip because the area of the semiconductor chip cannot be effectively utilized.

【００１１】[0011]

【発明が解決しようとする課題】これまで半導体チップ
の内部の設計において、レイアウトのしやすさ、パッケ
ージ組立後の検査のしやすさという観点から、Ｉ／Ｏパ
ッドの配置は実使用上必要なＩ／Ｏパッド・検査用Ｉ／
Ｏパッドがそれぞれいくつかのブロックにまとめて分か
れた配置を行っていた。従って、実装基板側の配線間距
離のルールに従って配置した場合、図３に見られるよう
に検査用Ｉ／Ｏパッドの分だけ半導体チップの一辺の長
さは余計に必要になる。In the design of the inside of a semiconductor chip, the arrangement of I / O pads is necessary for practical use from the viewpoint of easiness of layout and easy inspection after package assembly. I / O pad and inspection I /
O-pads were arranged in several blocks. Accordingly, when the wiring is arranged in accordance with the rule of the distance between the wirings on the mounting substrate side, as shown in FIG. 3, the length of one side of the semiconductor chip is required for the inspection I / O pad.

【００１２】また、半導体チップの内部構成が微細化す
るにつれて、隣接したＩ／Ｏパッド間でのクロストーク
ノイズの発生という問題も生じてくる。Further, as the internal structure of a semiconductor chip becomes finer, there arises a problem that crosstalk noise occurs between adjacent I / O pads.

【００１３】そこで、本発明は、Ｉ／Ｏパッドの配置の
仕方を見直し、半導体チップのＩ／Ｏパッド間距離のル
ールと実装基板の配線ルールとを各々満たすことによ
り、Ｉ／Ｏパッドを半導体チップ上に高密度に配置し、
かつ、隣接する実使用上必要なＩ／Ｏパッドの間に実使
用時には動作しないＩ／Ｏパッドを配置することによっ
て、半導体チップ上にＩ／Ｏパッド高密度に配置し、集
積度を高めた半導体装置を提供する。また、クロストー
クノイズを軽減することのできる半導体装置を提供する
ことを目的とする。In view of the foregoing, the present invention reviews the arrangement of I / O pads and satisfies the rules for the distance between I / O pads of a semiconductor chip and the wiring rules of a mounting board, respectively. High density on the chip,
In addition, I / O pads that do not operate during actual use are arranged between adjacent I / O pads that are required for actual use, so that I / O pads are arranged at high density on a semiconductor chip, and the degree of integration is increased. A semiconductor device is provided. It is another object to provide a semiconductor device capable of reducing crosstalk noise.

【００１４】[0014]

【課題を解決するための手段】上記目的を達するために
本発明は、実使用上必要なＩ／Ｏパッドの間に実使用時
には不必要な検査用Ｉ／Ｏパッドを配置したことを特徴
とする。In order to achieve the above object, the present invention is characterized in that an inspection I / O pad unnecessary in actual use is arranged between I / O pads required in actual use. I do.

【００１５】この構成により、半導体チップにＩ／Ｏパ
ッドを高密度に配置することが可能となる。With this configuration, it is possible to arrange the I / O pads on the semiconductor chip at a high density.

【００１６】また、検査用のＩ／Ｏパッドは半導体チッ
プの実動作時には、Ｌ固定もしくはＨ固定としたので、
実使用上必要なＩ／Ｏパッド間のクロストークノイズを
軽減することができる。The I / O pads for inspection are fixed at L or H during the actual operation of the semiconductor chip.
Crosstalk noise between I / O pads required for actual use can be reduced.

【００１７】[0017]

【発明の実施の形態】以下、本発明の実施の形態につい
て説明する。Embodiments of the present invention will be described below.

【００１８】図１は本発明の一実施の形態にかかる半導
体装置の平面図を示すものである。図中１５０は、実使
用上必要なＩ／Ｏパッド１１０〜１１６と検査用Ｉ／Ｏ
パッド１２０〜１２２とを含む半導体ベアチップであ
る。また、配線１００〜１０６は実装基板１６０のプリ
ント配線である。図１のＩ／Ｏパッド周辺を拡大したの
が図２である。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. In the figure, reference numeral 150 denotes I / O pads 110 to 116 necessary for actual use and I / O for inspection.
It is a semiconductor bare chip including pads 120 to 122. The wirings 100 to 106 are printed wiring of the mounting board 160. FIG. 2 is an enlarged view of the periphery of the I / O pad of FIG.

【００１９】図２のように、Ｉ／Ｏパッド２１０と２１
１の中心から中心までの距離Ｄpadは、配線２００と２
０１の配線の中心から中心までの距離Ｄkibanと同じに
なるように実使用上必要なＩ／Ｏパッドを配置する。こ
のとき、ＤpadがＹpadに比べて広い場合には、さらに、
その間にもＩ／Ｏパッド２２０，２２１を配置すること
ができる。As shown in FIG. 2, I / O pads 210 and 21
The distance D pad from the center of 1 to the center is 200
I / O pads necessary for practical use are arranged so as to be the same as the distance D kiban from the center of the wiring 01 to the center. At this time, if D pad is wider than Y pad ,
In the meantime, the I / O pads 220 and 221 can be arranged.

【００２０】ここで配置するのは、半導体チップの検査
時に使用するＩ／Ｏパッドである。半導体チップの製造
工程の中にはできあがった半導体チップの検査工程があ
り、そのときに用いるのが検査用のＩ／Ｏパッドであ
る。スライスをダイシングする前の状態で検査を行うと
きに、検査用Ｉ／Ｏパッドを用いて検査を行う。Arranged here are I / O pads used when inspecting a semiconductor chip. In a semiconductor chip manufacturing process, there is a completed semiconductor chip inspection process, and an I / O pad for inspection is used at that time. When the inspection is performed before the slice is diced, the inspection is performed using the inspection I / O pad.

【００２１】ベアチップ実装の場合は、実装された後に
検査用のＩ／Ｏパッドが使用されることはなく、実装基
板の配線と配線の間に検査用のＩ／Ｏパッド位置するよ
うに半導体チップ表面に配置され、実装時には実装基板
のどの配線とも接続されていなくても、実用上問題はな
い。In the case of the bare chip mounting, the I / O pad for inspection is not used after the mounting, and the semiconductor chip is positioned so that the I / O pad for inspection is located between the wirings of the mounting board. Even if they are arranged on the surface and are not connected to any wiring on the mounting board during mounting, there is no practical problem.

【００２２】ここで、Ｉ／Ｏパッドが配置できるのか、
また何個配置できるのかは以下の式により決定する。Here, can I / O pads be arranged?
Also, how many can be arranged is determined by the following equation.

【００２３】 （配置できるパッドの数）＝ (Dpad−Ｙpad−Ｂ)÷(Ｙpad＋Ｂ) ［個］ Ｄpadは隣接するＩ／Ｏパッドの中心から中心までの距
離、Ｙpadは半導体チップの外周に面している側の一辺
の長さ、Ｂは隣接するＩ／Ｏパッドとのお互いに面して
いる辺との距離である。但し、Dpad＝Dkibanである。(Number of pads that can be arranged) = (D pad− Y pad− B) ÷ (Y pad + B) [pieces] D pad is the distance from the center of the adjacent I / O pad to the center, and Y pad is the semiconductor The length of one side facing the outer periphery of the chip, B, is the distance between adjacent I / O pads and the sides facing each other. However, D pad = D kiban .

【００２４】例えば、図3のような実使用上必要なＩ／
Ｏパッド３１０〜３１６と検査用Ｉ／Ｏパッド３２０〜
３２２とで構成される半導体チップ３５０と実装基板３
６０について考える。このとき、Ｂ＝Ｄpad−Ｙpadであ
る。Ｂに比べて、図１において「α(Ｙpad＋Ａ)＋Ａ」
（αは配置できる検査用Ｉ／Ｏパッドの数、ＡはＩ／Ｏ
パッドのパッド間距離のルール）が小さければ、隣接す
る実使用上必要なＩ／Ｏパッドの間に検査用Ｉ／Ｏパッ
ドを配置することができる。その結果が図１の状態であ
る。For example, as shown in FIG.
O pads 310 to 316 and inspection I / O pads 320 to
322 and semiconductor chip 350 and mounting substrate 3
Consider 60. At this time, B = D pad -Y pad . Compared with B, in FIG. 1, “α (Y pad + A) + A”
(Α is the number of test I / O pads that can be arranged, A is I / O
If the rule of the distance between the pads is small, the I / O pad for inspection can be arranged between adjacent I / O pads required for practical use. The result is the state of FIG.

【００２５】半導体チップの内部面積がもともと小さ
く、半導体チップのそれぞれの辺についても同様なＩ／
Ｏパッドを配置することができれば、図１に示すように
長さＷだけ一辺の長さを詰めることができ、半導体チッ
プ上にＩ／Ｏパッドを配置するための面積は必要最小限
に抑えることができる。The internal area of the semiconductor chip is originally small, and the same I / O is applied to each side of the semiconductor chip.
If the O pad can be arranged, the length of one side can be reduced by the length W as shown in FIG. 1, and the area for arranging the I / O pad on the semiconductor chip is minimized. Can be.

【００２６】また、検査用のＩ／Ｏパッドは、半導体チ
ップの実使用時にはＬ固定、もしくはＨ固定になってお
り、これが実使用上必要なＩ／Ｏパッドの間に配置され
ていることにより、隣接する実使用上必要なＩ／Ｏパッ
ド間でのクロストークノイズの発生を抑制することがで
きる。The I / O pads for inspection are fixed at L or H at the time of actual use of the semiconductor chip, and are arranged between I / O pads required for actual use. In addition, it is possible to suppress the occurrence of crosstalk noise between adjacent I / O pads required for practical use.

【００２７】なお、本発明は、半導体チップがベアチッ
プで実装できる基板全てについて適応できる。The present invention is applicable to all substrates on which semiconductor chips can be mounted as bare chips.

【００２８】[0028]

【発明の効果】以上のように本発明によれば、実使用上
必要なＩ／Ｏパッドの間に検査用のＩ／Ｏパッドを配置
したので、基板側のプリント配線のルールにとらわれず
にＩ／Ｏパッドを半導体チップ上に効率的に配置でき、
ノイズ対策、チップ面積の縮小化、基板への高密度な実
装に対応できる。As described above, according to the present invention, since the I / O pads for inspection are arranged between the I / O pads necessary for practical use, the rules of the printed wiring on the substrate side can be applied. I / O pads can be efficiently arranged on a semiconductor chip,
Noise countermeasures, chip area reduction, and high-density mounting on a substrate can be supported.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施の形態における半導体チップの
Ｉ／Ｏパッド配置図FIG. 1 is an I / O pad layout of a semiconductor chip according to an embodiment of the present invention;

【図２】図１の検査用Ｉ／Ｏパッド配置部分拡大図FIG. 2 is an enlarged view of an inspection I / O pad arrangement part of FIG. 1;

【図３】従来の半導体チップのＩ／Ｏパッド配置図FIG. 3 is a layout diagram of I / O pads of a conventional semiconductor chip.

【図４】図３の拡大図FIG. 4 is an enlarged view of FIG. 3;

【符号の説明】[Explanation of symbols]

１００〜１０６ 基板のプリント配線 １１０〜１１６ 実使用上必要なＩ／Ｏパッド １２０〜１２２ 検査用Ｉ／Ｏパッド １５０ 半導体チップ １６０ 実装基板 ２００，２０１ 基板のプリント配線 ２１０，２１１ 実使用上必要なＩ／Ｏパッド ２２０，２２１ 検査用Ｉ／Ｏパッド ２５０ 半導体チップ ２６０ 実装基板 100-106 Printed wiring of board 110-116 I / O pad 120-122 required for actual use 150-I / O pad for inspection 150 Semiconductor chip 160 Mounting board 200, 201 Printed wiring of board 210, 211 I required for practical use / O pad 220,221 I / O pad for inspection 250 Semiconductor chip 260 Mounting board

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】実使用時には不必要な検査用のＩ／Ｏパッ
ドを実使用上必要なＩ／Ｏパッドの間に配置したことを
特徴とする半導体装置。1. A semiconductor device wherein an I / O pad for inspection unnecessary in actual use is arranged between I / O pads required in actual use. 【請求項２】実使用上必要なＩ／Ｏパッドの間に、実使
用時には使用しない検査用のＩ／Ｏパッドを配置すると
ともに、前記検査用のＩ／Ｏパッドは、クロストークノ
イズを抑制するように半導体チップの実使用時にはＬ固
定もしくはＨ固定としたことを特徴とする半導体装置。2. An I / O pad for inspection which is not used during actual use is arranged between I / O pads required for actual use, and the I / O pad for inspection suppresses crosstalk noise. The semiconductor device is fixed to L or H when the semiconductor chip is actually used.
JP2000307271A 2000-10-06 2000-10-06 Semiconductor device Pending JP2002118140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000307271A JP2002118140A (en) 2000-10-06 2000-10-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000307271A JP2002118140A (en) 2000-10-06 2000-10-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2002118140A true JP2002118140A (en) 2002-04-19

Family

ID=18787808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000307271A Pending JP2002118140A (en) 2000-10-06 2000-10-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2002118140A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010023491A (en) * 2008-06-16 2010-02-04 Canon Inc Liquid ejection recording head

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010023491A (en) * 2008-06-16 2010-02-04 Canon Inc Liquid ejection recording head

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