JP2002117682A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve write-in characteristic operations of a static type memory cell and to improve the lower limiting voltage characteristic and stability. SOLUTION: Adjusting circuits (10a-10c) are provided corresponding to each row of memory cells (MCA-MCC) at write-in of data, data-holding characteristic at write-in of data of the memory cell is made to be degraded, conforming to a row-selecting signal and a write-in indicating signal on a word line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a configuration of a memory cell of a static semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 27 is a diagram showing an example of a configuration of a conventional static memory cell (SRAM cell: static random access memory cell). FIG.
, The memory cell includes a high resistance element R1 connected between a power supply node receiving power supply voltage VCC and storage node SN1, and a high resistance resistance element R2 connected between the received power supply node and storage node SN2. And the storage node S
An N-channel MOS transistor (insulated gate field effect transistor) Tr1 connected between N1 and a ground node and having a gate connected to storage node SN2, and connected between storage node SN2 and a ground node and having a gate stored An N-channel MOS transistor Tr2 connected to node SN1 and an N-channel MOS transistor Tr3 selectively conducting according to a signal (row select signal) on word line WL and connecting storage node SN1 to complementary bit line / BIT. And an N-channel MOS transistor Tr4 selectively conducting according to a signal on word line WL and connecting storage node SN2 to bit line BIT.

[0005] Bit lines BIT and / BIT are precharged to H level by a bit line load circuit (not shown). Complementary data is held in storage nodes SN1 and SN2, and one of MOS transistors (drive transistors) Tr1 and Tr2 is turned on and the other is turned off.

Normally, in a memory cell, in order to hold data stably, a ratio of a current driving capability of an access MOS transistor Tr3 (or Tr4) to a corresponding drive transistor Tr1 (or Tr2), that is, The β ratio is set to a value of about 1: 3, and the current drive capability of the drive transistors Tr1 and Tr2 is determined by the access MOS transistor (access transistor).
The current driving capability of Tr3 and Tr4 is made larger. The current drivability of the MOS transistor is the channel width W
And the length of the channel length L, which is given by W / L.

At the time of data writing, bit line BIT
And / BIT are driven to the ground voltage level of L level, and the other maintains the precharge voltage level (H level). At the time of selection according to a row selection signal on word line WL, access transistors Tr3 and Tr
4 conducts, and one of storage nodes SN1 and SN2 attains an L level according to the voltage on bit lines BIT and / BIT driven by a write driver (not shown). At the time of this data writing, the drive transistor whose gate is connected to the storage node to which the data of H level has been transmitted is in the ON state, and a small current from the corresponding high resistance resistor element should be discharged to L level. The storage node is driven to the L level at high speed. When the voltage levels of storage nodes SN1 and SN2 are set to H level and L level, thereafter, the memory cell enters a latch state.

At the time of data reading, the bit line maintains the precharge voltage level, while the voltage level of the bit line from which the L level data has been read decreases. The L-level read voltage level of the bit line is a voltage level determined by the ratio of the load resistance of the bit line to the sum of the channel resistance of the access transistor and the channel resistance of the conductive drive transistor. The voltage difference appearing on bit lines BIT and / BIT is transmitted to a sense amplifier circuit via a column selection gate, and differentially amplified by a sense amplifier to read data.

The memory cell includes a drive transistor Tr
1 and Tr2, the data is held by a flip-flop. At the time of data holding, although a minute current flows through a high-resistance resistor element, the data can be reliably held while power is supplied. (Dynamic random access memory) Compared with a cell, refresh for rewriting data is not required, and a wait time of the refresh system is not required, so that a high-speed processing system can be constructed.

[0008]

FIG. 28 schematically shows a state of a memory cell at the time of data reading. FIG.
Shows a state in which L-level data is stored in storage node SN1 and H-level data is stored in storage node SN2. When the word line WL is selected,
Access transistors Tr3 and Tr4 are rendered conductive, and storage nodes SN1 and SN2 are connected to bit lines BIT and / BIT, respectively. Bit lines / BIT and BIT are precharged to H level, respectively, and column current Ir flows from bit line / BIT via access transistor Tr3 via the bit line precharge element. The drive transistor Tr1 is
The voltage level of storage node SN2 is at the H level and is in a conductive state, and current Ir is applied to drive transistor T2.
Discharged to the ground node via r1. Therefore, the voltage level of bit line / BIT is lower than the precharge voltage level. On the other hand, drive transistor Tr2 is off, and storage node SN2 is at H level.
Level, and no current flows from bit line BIT to storage node SN2. Therefore, bit line BI
A voltage difference ΔV occurs between T and / BIT, and this voltage difference ΔV
Is amplified by a differential amplification type sense amplifier to read data.

FIG. 29 schematically shows a state of a memory cell at the time of data writing. In FIG. 29, L-level data is transmitted to bit line BIT. Bit line / BI
H level data is transmitted to T. Word line WL
Is selected, access transistors Tr and Tr4 conduct, and storage nodes SN1 and SN2 are connected to bit line BI.
T and / BIT respectively. The bit line BIT is driven to the ground voltage level L level by a write driver not shown. Bit line / BIT is at H level. Therefore, storage node SN2 is driven to L level by the write driver via bit line BIT, and storage nodes SN2 and SN1 are held at L level and H level by drive transistors Tr1 and Tr2, respectively. .

However, L of storage node SN2
The level voltage level is determined by the high-resistance resistor R2, the bit line load resistance of the bit line BIT, and the channel resistance of the access transistor Tr4 during data writing. When the resistance value of resistance element R2 is low, a large amount of current is supplied from the power supply node to storage node SN2, and storage node SN2 cannot be driven to a sufficiently low voltage level of L level, and drive transistors Tr1 and Tr2 are not driven.
2 does not enter the conduction / non-conduction state according to the write data.
In this state, when word line WL is driven to a non-selected state and access transistors Tr3 and Tr4 are set to a non-conductive state, the voltage levels of storage nodes SN1 and SN2 attain an intermediate voltage level or drive transistors It is kept at a voltage level determined by the characteristics of Tr1 and Tr2. Therefore, in this case, the H level data and the L level data cannot be stored accurately, and a writing failure occurs.

When resistance elements R1 and R2 are made of, for example, polysilicon resistors, it becomes difficult to provide a sufficient resistance value in a small occupied area with miniaturization of a memory cell. Can occur. Also,
If a micro short exists between the power supply node and one of the storage nodes SN1 and SN2 due to particles (foreign matter) or the like in the manufacturing process, the resistance value of such a resistance element becomes equivalently small.

FIG. 30 schematically shows a state of a memory cell when data is held. In FIG. 30, L level data is held in storage node SN1, and storage node SN
2 holds H level data. The word line WL is
In the unselected state at L level, the access transistor T
r3 and Tr4 are non-conductive. Drive transistor Tr1 has storage node SN2 at H level and is in a conductive state, and discharges current Ia supplied from resistance element R1 to the ground node as current Ib.

On the other hand, drive transistor Tr2 is off (O) because storage node SN1 is at L level.
FF), and only the current Ic corresponding to the leak current Id of the drive transistor Tr2 is supplied from the resistance element R2. However, this resistance element R
2, the supply current Ic becomes smaller than the leak current Id of the drive transistor Tr2, the voltage level of the storage node SN2 decreases from the H level, and the conductance of the drive transistor Tr1 accordingly decreases. And the discharge current Ib decreases, and accordingly, the voltage level of storage node SN1 increases,
The data stored in the memory cell becomes unstable.

When the voltage level of power supply voltage VCC is low, the voltage level of storage node SN2 is low,
Drive transistor Tr1 is not sufficiently turned on, supply current Ia from resistance element R1 is relatively increased as compared with discharge current Ib, and the voltage level of storage node SN1 is increased. Therefore, an operation failure (lower limit voltage operation failure) occurs under such a low power supply voltage, and an accurate data holding operation cannot be performed.

That is, in the conventional SRAM cell, when the data is written, the higher the resistance value of the load resistance element, the more accurate the data writing can be assured. There was a contradictory feature that the lower the resistance value of the resistance element, the more stable operation can be guaranteed. Therefore, when stabilizing the memory cell and guaranteeing the writing characteristics with respect to miniaturization of the element and lowering of the power supply voltage, it is difficult to guarantee these characteristics at the same time. However, there is a problem that it is difficult to realize an SRAM cell having an excellent write margin.

An object of the present invention is to provide a semiconductor memory device capable of holding data stably.

Another object of the present invention is to provide a semiconductor memory device which can hold data accurately even under a low power supply voltage and can accurately write data to a memory cell.

Still another object of the present invention is to provide a semiconductor memory device having an SRAM cell excellent in stability and writing characteristics.

[0019]

A semiconductor memory device according to a first aspect of the present invention has a plurality of memory cells. Each of the memory cells includes a first load element connected between the first power supply node and the first storage node, and a first load element connected between the second power supply node and the second storage node. A second drive element, a first drive transistor connected between the first storage node and the second power supply node and selectively conducting according to the voltage level of the second storage node;
A second drive transistor connected between the second power supply node and the second storage node and selectively turned on according to the voltage level of the first storage node; A first access transistor responsively connecting the first storage node to the first bit line; and a second access node responsive to a row select signal on the word line for connecting the second storage node to the second bit line.
A second access transistor connected to the bit line of
And an adjustment circuit for increasing an equivalent resistance between each of the first and second storage nodes and the first power supply node at the time of data writing.

This adjusting circuit is preferably connected between the first power supply node and the first storage node in parallel with the first load element, and has a row select signal and a write instruction for instructing data write. A first auxiliary transistor that is turned off when both signals are activated, and a second load element connected in parallel with the second load element between the first power supply node and the second storage node; A second auxiliary transistor that is turned off when both instruction signals are activated.

The semiconductor memory device according to the second aspect has a plurality of memory cells. Each of the memory cells includes a first load element connected between the first power supply node and the first storage node, and a first load element connected between the second power supply node and the second storage node. A second drive element, a first drive transistor connected between the first storage node and the second power supply node and selectively conducting according to a voltage on the second storage node; A second drive transistor connected between the second power supply node and the second storage node and selectively turned on according to the voltage of the first storage node; and a second drive transistor responsive to a row selection signal on the word line. A first access transistor connecting the first storage node to the first bit line, and a second access transistor connecting the second storage node to the second bit line in response to a row selection signal on the word line. Transistors and the first and And a regulating circuit for reducing second storage node and the amount of drive current between the second power supply node respectively.

This adjusting circuit is preferably connected between the first storage node and the second power supply node in parallel with the first drive transistor, and has a row select signal and a write instruction for instructing data write. A first auxiliary transistor which is turned off when both signals are activated, and a second selection transistor connected in parallel with a second drive transistor between a second storage node and a second power supply node; And a second auxiliary transistor which is turned off when both of the write instruction signals are activated.

A semiconductor memory device according to a third aspect has a plurality of memory cells. Each of the plurality of memory cells includes a first load element connected between the first power supply node and the first storage node, and a connection between the second power supply node and the second storage node. A second load element, a first drive transistor connected between the first storage node and the second power supply node, and selectively turned on in accordance with the voltage level of the second storage node; , A second drive transistor connected between a second power supply node and a second storage node and selectively turned on according to a voltage on the first storage node; A first connecting a first storage node to a first bit line in response to a signal
And a second access transistor that connects the second storage node to the second bit line in response to a row selection signal on the word line.

A semiconductor memory device according to a third aspect of the present invention further comprises an adjustment circuit for increasing the equivalent resistance between the first and second storage nodes and the first power supply node during data writing. including.

Each of the first and second load elements is constituted by an insulated gate transistor. The adjusting circuit preferably includes a switching circuit for increasing the back gate bias of these insulated gate transistors when both a write instruction signal instructing data writing and a row selection signal are activated.

A semiconductor memory device according to a fourth aspect has a plurality of memory cells. Each of the memory cells includes a first load element connected between the first power supply node and the first storage node, and a first load element connected between the second power supply node and the second storage node. A second drive element, a first drive transistor connected between the first storage node and the second power supply node, and selectively turned on according to the voltage of the second storage node; A second drive transistor connected between the power supply node and the second storage node and selectively turned on according to the voltage of the first storage node, and in response to a row selection signal on the word line A first access transistor connecting the first storage node to the first bit line, and a second access transistor connecting the second storage node to the second bit line in response to a row select signal on the word line And

The semiconductor memory device according to the fourth aspect of the present invention further includes an adjustment for increasing an equivalent resistance between the first and second storage nodes and the second power supply node during data writing. Including circuits.

Preferably, each of the first and second drive transistors comprises an insulated gate transistor. In this case, the adjustment circuit preferably includes a switching circuit for increasing the back gate bias of the insulated gate transistor in response to activation of both a write instruction signal instructing data writing and a row selection signal.

A semiconductor memory device according to a fifth aspect of the present invention includes a plurality of memory cells. Each of the memory cells
A first load element connected between the first power supply node and the first storage node, a second load element connected between the second power supply node and the second storage node, A first transistor which is connected between the first storage node and the second power supply node and which is selectively turned on according to the voltage of the second storage node.
A second drive transistor connected between the second power supply node and the second storage node and selectively conducting according to the voltage level of the first storage node; A first access transistor connecting a first storage node to a first bit line in response to a row selection signal of the first bit line, and a second access node connecting a second storage node to a second bit line in response to a row selection signal on the word line. A second access transistor connected to the line.

The semiconductor memory device according to the fifth aspect of the present invention further includes an adjustment circuit for reducing the channel resistance of the first and second access transistors during data writing.

Preferably, each of the first and second access transistors comprises an insulated gate transistor. The adjustment circuit preferably includes a switching circuit for reducing the back gate bias of the insulated gate transistor in response to activation of both the row selection signal and the write instruction signal for instructing data writing.

In the semiconductor memory devices according to the first to fifth aspects, preferably, the voltage of the first power supply node is lower than the voltage of the second power supply node.

Instead of this, preferably, in the semiconductor memory device according to the first to fifth aspects, the voltage of the first power supply node is set higher than the voltage of the second power supply node.

Preferably, the switching circuit for switching the bias of the load transistor preferably has an absolute value lower than the voltage of the first power supply node when the write instruction signal and the row selection signal are both activated. And a voltage of the same voltage level as the voltage of the first power supply node when at least one of the write instruction signal and the row selection signal is inactive is applied to the back gate.

Instead of this, the switching circuit for changing the bias of the drive transistor includes a second power supply node which supplies the absolute value to the back gate of the insulated gate transistor when both the write instruction signal and the row selection signal are activated. And a voltage at the same voltage level as the voltage of the second power supply node when at least one of the write instruction signal and the row selection signal is inactive is applied to the back gate.

Preferably, the switching circuit for making the back gate of the access transistor shallow includes a voltage of the second power supply node applied to the back gate of the insulated gate transistor when both the write instruction signal and the row selection signal are activated. A first bias voltage having the same voltage level as the first bias voltage is applied to the back gate, and a voltage having at least one of a write instruction signal and a row selection signal whose inactive absolute value is larger than the first bias voltage is applied to the back gate.

A semiconductor memory device according to a sixth aspect of the present invention has a plurality of memory cells. Each of the plurality of memory cells includes a first load circuit connected between the first power supply node and the first storage node, a second power supply node and a second power supply node.
And a second load circuit connected between the first storage node and the second power supply node and selectively turned on according to the voltage level of the second storage node. A first drive transistor that is in a state, a second drive transistor that is connected between the second power supply node and the second storage node, and that is selectively turned on according to the voltage of the first storage node; A first access transistor connecting a first storage node to a first bit line in response to a row selection signal on a word line, and a second access node connecting a second storage node in response to a row selection signal on a word line. And a second access transistor connected to the corresponding bit line.

The semiconductor memory device according to the sixth aspect of the present invention further includes an adjustment circuit for increasing the equivalent resistance of the first and second load circuits during data writing.

Preferably, the first load circuit includes a first load element connected between the first power supply node and the first storage node, and a first power supply node and the first storage node. And a first transistor element which receives the output signal of the adjustment circuit at its gate. The second load circuit includes a second load element connected between the first power supply node and the second storage node, and a first power supply node and a second load element connected in parallel with the second load element. A second transistor element connected to the storage node and receiving at its gate the output signal of the adjustment circuit. The adjustment circuit renders the first and second transistor elements non-conductive in response to activation of both the row selection signal and a write instruction signal for instructing data writing.

Alternatively, the first load circuit is connected between the first power supply node and the first storage node,
A first insulated gate transistor receiving an output signal of the adjustment circuit at a back gate, the second load circuit being preferably connected between a first power supply node and a second storage node; A second insulated gate transistor that receives the output signal of the second transistor at its back gate. The adjustment circuit is
The back gate bias of the first and second insulated gate transistors is increased in response to the activation of both the data write instruction signal and the row selection signal.

A semiconductor memory device according to a seventh aspect of the present invention has a plurality of memory cells. Each of the plurality of memory cells includes a first load element connected between the first power supply node and the first storage node, and a connection between the second power supply node and the second storage node. Connected between the second load element and the first storage node and the second power supply, and connects the first storage node to the voltage level of the second power supply node according to the voltage level of the second storage node. And a second drive node connected between the second power supply node and the second storage node and driven in accordance with the voltage level of the first storage node. A second drive circuit that drives and holds the voltage level of the second power supply node, a first access transistor that connects the first storage node to the first bit line in response to a row selection signal on the word line, and , In response to a row selection signal on the word line, And a second access transistor connecting the 憶 node to the second bit line.

The semiconductor memory device according to the seventh aspect of the present invention further includes an adjustment circuit for reducing the amount of drive current of the first and second drive circuits during data writing.

Preferably, the first drive circuit comprises:
A first insulated gate transistor connected between the storage node and a second power supply node, and having a gate connected to the second storage node, and further having a back gate receiving an output voltage of the adjustment circuit. The second drive circuit is preferably connected between the second storage node and the second power supply node, has a gate connected to the first storage node, and further receives an output voltage of the adjustment circuit on a back gate. 2
Insulated gate transistors. The adjusting circuit preferably deepens the back gate bias of the first and second insulated gate transistors when both the row selection signal and the write instruction signal for instructing data writing are activated.

Alternatively, preferably, the first drive circuit is connected between the first storage node and the second power supply node, and has its gate connected to the second storage node. A first drive transistor and a first auxiliary transistor connected between the first storage node and the second power supply node and having a gate receiving an output signal of the adjustment circuit are included. A second drive circuit, preferably connected between the second storage node and the second power supply node, and having a gate connected to the first storage node; A second auxiliary transistor connected between the storage node and the second power supply node and receiving at its gate the output signal of the adjustment circuit. The adjustment circuit is
Preferably, the first and second auxiliary transistors are rendered non-conductive in response to activation of both a row selection signal and a write instruction signal instructing data writing.

In a semiconductor memory device according to an eighth aspect of the present invention, each of the plurality of memory cells includes a first load element connected between the first power supply node and the first storage node; A second load element connected between the first power supply node and the second storage node; a second load element connected between the first storage node and the second power supply node; A first drive circuit for driving the first storage node to the voltage level of the second power supply node according to the voltage, and a first storage circuit connected between the second storage node and the second power supply node; A second drive circuit for driving the second storage node to the voltage level of the second power supply node according to the voltage of the node, and a first bit for storing the first storage node in response to a row selection signal on the word line. Back gate bias shallow during data writing Including a first access transistor, the second access transistor connects the second storage node in response to a row selection signal on the word line to the second bit line and the data write time back gate bias is shallower.

By increasing the equivalent β ratio of the memory cell or the resistance value of the load resistance during data writing, the data writing characteristics of the memory cell can be improved. That is, by selectively increasing the resistance value of the load resistor during data writing, L-level data can be reliably written and the write margin can be increased. Further, by reducing the current driving force between the first and second storage nodes and the second power supply node at the time of writing, the resistance value of the load resistance is equivalently increased to limit the current, An L-level voltage can be reliably written to the storage node. Further, by reducing the on-resistance of the access transistor at the time of data writing, the equivalent β ratio can be reduced at the time of writing to write L-level data at high speed. In an operation mode other than the data write operation mode, such as the data holding mode, the data can be stably held by setting the state opposite to the above.

[0047]

[First Embodiment] FIG. 1 schematically shows a structure of a main portion of a semiconductor memory device according to the present invention. FIG. 1 representatively shows memory cells MCA,... MCC arranged in a plurality of rows and one column. Bit lines BIT and / BIT are arranged corresponding to the columns of memory cells MCA-MCC. Memory cells MCA-MCC
Are word lines WL1A, WL1B,... WL1C, respectively.
Connected to.

For bit lines BIT and / BIT, these bit lines BIT and / BIT are set to a predetermined H level.
Load circuits 1a and 1b for precharging to the level voltage level are provided. Load circuits 1a and 1b are formed of MOS transistors (insulated gate type field effect transistors), and these bit lines BIT and / BIT may be precharged to power supply voltage VCC level, or may be diode-connected. , And these bit lines BIT and / BIT may be precharged to a voltage level of VCC-Vth. Here, Vth indicates a threshold voltage of a diode-connected MOS transistor included in bit line load circuits 1a and 1b. Bit line load circuits 1a and 1b may be set to a non-conductive state during a data write operation.

These bit lines BIT and / BIT
Are coupled to a write driver 3 and a sense amplifier 4 via a column selection gate 2. Column select gate 2 is selectively turned on in response to a column select signal Y from a column decoder (not shown) and an output signal of inverter 5 for inverting column select signal Y. Column select gate 2 is provided for each of bit lines BIT and / BIT and has a CMO responsive to column select signal Y and an output signal of inverter 5.
Includes S transmission gates 2a and 2b.

Write driver 3 responds to activation of write driver enable signal WDE from write control circuit 6 to convert complementary write data (H level and L level) from internal write data from a data input circuit (not shown). Of the bit line BI via the column selection gate 2
Give to T and / BIT. The write driver 3 drives the bit line BIT or / BIT precharged to the H level to the L level according to the write data.

This write driver enable signal WDE
Are generated from the write control circuit 6 receiving the chip select signal / CS and the write enable signal / WE. When the chip select signal / CS is at the L level and the write enable signal / WE is at the L level, the write control circuit 6 issues a write driver enable signal WDE at a predetermined timing.
Activate. The sense amplifier activation signal SAE is activated according to the address change detection signal when the chip select signal / CS is at L level and the write enable signal / WE is at H level.

A word line WL1A- corresponding to a write instruction signal W from write control circuit 6 corresponding to each row of memory cells
Adjustment circuits 10a-10c are provided for adjusting the data holding characteristics of memory cells MCA-MCC of the corresponding row according to a row selection signal on WL1C. Write instruction signal W may be the same signal as write driver enable signal WE. The write instruction signal W only needs to be activated when the write driver 3 operates.

In each of word lines WL1A-WL1C, one row of memory cells MC (MCA, MCB, MC
C) is connected. Adjustment circuits 10a-10c are provided corresponding to each row (word line). Each of adjustment circuits 10a-10c supplies a memory cell M in a corresponding row when a corresponding row is selected and write instruction signal W is activated.
Adjust the data write characteristics of the CA-MCC (decrease the β ratio or equivalently increase the resistance value of the load resistor). Adjustment circuits 10a-10c improve data retention characteristics of memory cells in a corresponding row when one of write instruction signal W and a row selection signal on a corresponding word line is in a non-selected state. Next, specific configurations of adjustment circuits 10a-10c and memory cells MCA-MCC will be described.

[First Embodiment] FIG. 2 shows a configuration of adjustment circuit 10 and memory cell MC according to a first embodiment of the present invention. FIG. 2 shows one-bit memory cell MC and one adjustment circuit 10. In FIG. 2, a memory cell MC includes a high-resistance resistance element R1 connected between a power supply node receiving a power supply voltage and storage node A1.
1 and an N-channel M connected between storage node A1 and the ground node and having its gate connected to storage node B1
OS transistor (drive transistor) Tr11
A high resistance element R21 connected between the power supply node and storage node B1, and an N-channel MOS transistor (drive) connected between storage node B1 and the ground node and having its gate connected to storage node A1. Transistor) Tr21 conducts when a signal (row select signal) on word line WL11 is activated to connect storage node A1 to bit line / B.
An N-channel MOS transistor (access transistor) Tr31 connected to IT and an N-channel MOS transistor (access transistor) Tr41 that conducts when a row selection signal on word line WL11 is activated and connects storage node B1 to bit line BIT. including. Load resistance element R
Each of 11 and R21 is formed of, for example, a high-resistance element such as polysilicon. However, as these load resistance elements, MOS transistors may be connected by resistance.

Memory cell MC further includes a P-channel MOS transistor Tr51 connected between the power supply node and storage node A1 and receiving at its gate the output signal L11 of adjustment circuit 10, and a memory cell MC between the power supply node and storage node B1. Output signal L of the adjustment circuit 10
11 includes a P-channel MOS transistor Tr61. These P-channel MOS transistors Tr51
Each of Tr 61 and Tr 61 has a sufficiently large on-resistance (channel resistance) or a sufficiently small current driving capability, and functions as a pull-up element when conducting.

Adjustment circuit 10 includes a NAND gate 11a receiving write instruction signal W11 and a row selection signal on word line WL11, and an inverter 11b for inverting the output signal of NAND gate 11a to generate signal L11. In other words, adjustment circuit 10 is equivalently an AND circuit, and when write instructing signal W11 and the row selection signal on word line WL11 are both activated, output signal L11 is set to the H level and MOS transistor Tr51 is set. And T
r61 is set to a non-conductive state (OFF). Next, the operation of memory cell MC shown in FIG. 2 will be described.

First, referring to FIG. 3, an operation for writing data to memory cell MC will be described. Now, bit lines BIT and / BIT are precharged to H level. As shown in FIG. 2, the bit line BIT is now
Consider a data write operation driven to the L level. In the holding state, word line WL11 is in a non-selected state, and write instruction signal W11 is also in an inactive state.
0 output signal L11 is at L level, MOS transistors Tr51 and Tr61 are both on, and storage nodes A1 and B1 are pulled up to H level. In this case, the current driving capabilities of MOS transistors Tr51 and Tr61 are sufficiently small, and storage node A
1 and B1 hold the data written in the previous cycle.

At the time of data writing, first, write instruction signal W11 attains H level. Then, word line WL11 is selected according to an external address signal, access transistors Tr31 and Tr41 are turned on, and storage nodes A1 and B1 are coupled to bit lines / BIT and BIT, respectively. When the voltage level of word line WL11 rises to H level, signal L11 from adjustment circuit 10 attains H level, and MOS transistor Tr51
And Tr61 are both turned off.

In this state, MOS transistors Tr51 and Tr61 equivalently have channel resistances sufficiently larger than the resistance values of load resistors R11 and R21, and are equivalently connected to the power supply node and storage nodes A1 and B1. , High resistance elements R11 and R21, respectively.
Is connected. In this case, the MOS transistor Tr51
If the ON resistance (channel resistance) of Tr61 and Tr61 is substantially the same as the resistance value of resistance elements R11 and R21, the resistance value between the power supply node and storage nodes A1 and B1 is about twice as large. Therefore, in this state, bit line BI
When T is driven to the L level by the write driver 3 shown in FIG. 1, the voltage level of the storage node B1 becomes equal to the resistance value of the resistance element R21 between the power supply node and the storage node B1.
MOS which is sufficiently larger than the parasitic resistance of bit line BIT and MOS
Since the ON resistance of the transistor Tr21 is sufficiently higher, the voltage level of the storage node B1 is reliably driven to the L level. The storage node A1 is connected to the bit line / B
It becomes H level according to the precharge voltage level of IT or H level data from the write driver 3 shown in FIG.

When the write cycle is completed, word line WL
11 is in a non-selected state, and the write instruction signal W11 is
Becomes L level, and the MOS transistors Tr51 and T51
r61 is turned on.

The resistance value between the power supply node and storage nodes A1 and B1 at the time of data writing is represented by the following equations, respectively.

For storage node A1: R11.RT51 (OFF) / (R11 + RT51 (O
FF)), for the storage node B1: R21 · RT61 (OFF) / (R21 + RT61 (O
FF)).

Here, RT51 (OFF) and RT6
1 (OFF) indicates the off resistance (resistance of the channel region in the off state) of the transistors Tr51 and Tr61, respectively, and R11 and R21 indicate the resistance values of the resistance elements R11 and R21.

FIG. 4 shows a state in an operation mode other than the time of data writing to memory cell MC. In FIG. 4, in an operation mode other than the data writing, write instruction signal W11 is at L level. Therefore, output signal L11 of adjustment circuit 10 is at the L level regardless of the state of the row selection signal on word line WL, and MOS transistors Tr51 and Tr61 are both conductive (ON). MOS transistors Tr51 and Tr61 are:
Its on-resistance (channel resistance in the on-state) is sufficiently large and functions as a pull-up element like the resistance elements R11 and R21. In this state, as shown in FIG. 5, word line WL11 is driven to the selected state. In this state, when write instruction signal W11 is at L level and data reading is performed, access transistors Tr31 and Tr41 are turned on. State and storage nodes A1 and B1
Are connected to bit lines / BIT and BIT, respectively. Even in this state, the output signal L1
1 is at the L level, and the MOS transistors Tr51 and Tr61 are conducting. Therefore, since the resistance element is connected in parallel between the power supply node and each of storage nodes A1 and B1, the resistance value is smaller than that during data writing. Even when the resistance values of the pull-up resistors of these storage nodes A1 and B1 become smaller, at the time of data reading, one of drive transistors Tr11 and Tr21 causes one of bit lines / BIT and B
Since one of the ITs is discharged, the data reading operation is not affected at all.

When data reading is completed, word line WL1
1 is driven to the non-selected state, and the access transistor Tr
31 and Tr41 are turned off. In this data holding state, MOS transistors Tr51 and T51
r61 is both conductive, one of storage nodes A1 and B1 attains an H level in accordance with the stored data, one of drive transistors Tr11 and Tr21 is reliably turned on, and storage nodes A1 and B1 are driven in accordance with the stored data. Therefore, it is reliably held at H level and L level. Therefore, even when power supply voltage VCC is low, resistance values of load resistance elements R11 and R21 are equivalently reduced, so that one of storage nodes A1 and B1 is reliably pulled up to the power supply voltage level, and MOS
One of the transistors Tr11 and Tr21 is reliably turned on, and the stability of the memory cell is guaranteed.

The resistance values of the resistance elements of storage nodes A1 and B1 in an operation mode other than the write operation are represented by the following equations.

For storage node A1: R11.RT51 (ON) / (R11 + RT51 (O
N)), for the storage node B1: R21.RT61 (ON) / (R21 + RT61 (O
N)).

Here, RT51 (ON) and RT61
(ON) indicates the ON resistance (channel resistance) of each of the MOS transistors Tr51 and Tr61.

MOS transistors Tr51 and Tr6
In No. 1, the channel resistance during conduction is sufficiently smaller than the channel resistance during non-conduction. That is, the following equation is established.

RT51 (OFF) >> RT51 (ON), RT61 (OFF) >> RT61 (ON).

That is, the pull-up resistance of storage nodes A1 and B1 at the time of data writing is sufficiently larger than the resistance value of the pull-up resistance at the time other than writing. That is, at the time of data writing, the resistance values of the pull-up resistors of storage nodes A1 and B1 are sufficiently high, and at other times, the resistance values of the pull-up resistors of storage nodes A1 and B1 are low. At the time of writing, since the L level of the storage node is set to a sufficiently low voltage, the write margin increases, and the resistance value of the pull-up resistor is equivalent in operation modes other than data writing. Therefore, the voltage level of the H-level data can be sufficiently increased, and the operation lower limit voltage characteristic and the data holding characteristic (hold characteristic) can be improved.

As described above, according to the first embodiment of the present invention, at the time of data writing, the MOS transistor having a high on-resistance connected in parallel with the load resistance element is turned off, and is otherwise turned on. Therefore, at the time of writing, the resistance value of the pull-up resistor of the storage node can be increased, and at other times, the resistance value of the pull-up resistor can be decreased, and the write margin, the lower limit operation voltage characteristic and the data holding characteristic can be improved. Can be improved.

[Second Embodiment] FIG. 6 shows a configuration of an adjustment circuit 10 and a memory cell MC according to a second embodiment of the present invention. Also in the second embodiment, adjustment circuit 10 is arranged corresponding to each word line. This adjustment circuit 10 is provided with a write instruction signal W12 and a word line WL12.
Includes NAND circuit 12 receiving the above signal (row select signal). This NAND circuit 12 outputs an adjustment signal L12.

Memory cell MC is electrically connected to high-resistance resistance elements R12 and R22 connected between a power supply node and storage nodes A2 and B2 when a row selection signal on word line WL12 is activated, and stores data. Nodes A2 and B
2 to bit lines / BIT and BIT, respectively, and access transistor Tr32 and Tr42, and drive transistor Tr12 for driving storage node A2 to the ground voltage level according to the voltage level of storage node B2.
And storage node B2 according to the voltage on storage node A12.
Is driven to the ground voltage level.
r22.

The memory cell MC further includes a storage node A
N channel MOS transistor Tr52 connected between storage node B2 and ground node and receiving output signal L12 of adjustment circuit 10 at its gate, output signal L12 of adjustment circuit 10 connected between storage node B2 and the ground node and connected to its gate.
Receiving N channel MOS transistor Tr62. These MOS transistors Tr52 and Tr6
2 has a large channel resistance and functions as a pull-down element when conducting. Here, the MOS transistor has a channel formed only during conduction, and has a significant channel resistance. At the time of non-conduction, no channel is formed in the MOS transistor, and the source-drain resistance becomes extremely large. Next, the operation of memory cell MC shown in FIG. 6 will be described. First, the operation at the time of data writing will be described with reference to FIG.

Now, as shown in FIG. 6, bit line / BIT
And BIT are precharged to the H level, respectively, and data writing for driving bit line BIT to the L level is performed. At the time of this data writing, first, write instruction signal W12 attains H level, and subsequently, the row selection signal on word line WL12 attains H level. Word line WL12 is selected, access transistors Tr32 and Tr42 are turned on, and storage nodes A2 and B2 are connected to bit lines / BIT and BIT, respectively.
Connected to. The row selection signal on word line WL12 is at H level, write instruction signal W12 is also at H level, and output signal L1 of adjustment circuit 10 (NAND circuit 12) is provided.
2 is at the L level, and the MOS transistors Tr52 and Tr62 are turned off (OFF). When the storage node B2 falls to the L level, the storage node A2 changes to the H level.
Level, drive transistor Tr22 is rendered conductive and storage node B2 is reliably driven to the ground voltage level. MOS transistors Tr12 and Tr5
2 are both non-conductive, and a parallel body of these off-resistances is connected between storage node A2 and the ground node.

In storage node B2, drive transistor Tr22 is turned on, and drives storage node B2 to the ground voltage level. In this case, MOS
Transistor Tr62 is non-conductive and is equivalently short-circuited by drive transistor Tr22. MOS transistor Tr62 has no effect on this L-level data writing. At the time of this data writing, storage node A2 is at the H level, and even when the power supply potential is lowered, storage node A2 surely has a lower current drivability than in the case where MOS transistor Tr52 is in a conductive state. Eyes of glasses "become smaller,
Storage node A2 can be maintained at the H level power supply voltage VCC level in accordance with the write data, and MOS transistor Tr2
2 can be turned on to drive storage node B2 to the ground voltage level. For storage node B2, M
Since the OS transistor Tr62 is in a non-conductive state, so-called "eyeglasses" are reduced, and data can be written reliably. The resistance value of each pull-down resistor of storage nodes A2 and B2 at the time of data writing is represented by the following equation.

For storage node A2: RT52 (OFF) / RT12 (ON / OFF) / (R
T52 (OFF) + RT12 (ON / OFF)), for the storage node B2: RT62 (OFF) / RT22 (ON / OFF) / (R
T62 (OFF) + RT22 (ON / OFF)).

Here, RT52 (OFF), RT62
(OFF) indicates the off resistance of the MOS transistors Tr52 and Tr62, respectively, and RT12 (ON / OF)
F) and RT22 (ON / OFF) indicate on-resistance or off-resistance of drive transistors Tr12 and Tr22 (depending on stored data).

FIG. 8 is a diagram showing a state of memory cell MC during an operation other than data writing. During an operation other than the data write operation, write instruction signal W12 is at L level, and output signal L12 of adjustment circuit 10 is at H level regardless of the state of the row selection signal on word line WL12. Therefore, MOS transistor Tr5 connected in parallel with drive transistors Tr12 and Tr22
2 and Tr62 become conductive (ON). The channel resistance (ON resistance) of these MOS transistors Tr52 and Tr62 is sufficiently large, and these MOS transistors Tr52 and Tr62 function as a pull-down element when conducting. In this state, as shown in FIG. 9, during data reading, the row selection signal on word line WL12 attains H level, and access transistor Tr
32 and Tr42 become conductive. At the time of data reading, drive transistors Tr12 and Tr22
Is in a conductive state, and one of bit lines / BIT and BIT precharged to H level is discharged via a drive transistor in a conductive state, and its voltage level is lowered. MOS transistor Tr52 or Tr62 is connected in parallel with the conductive drive transistor. Therefore, in this path, since a parallel body of pull-down resistors is connected, the equivalent resistance is reduced and the current driving force is increased. Similarly, also at the storage node A2, the MOS transistor Tr52 in the conductive state is connected, so that the current drivability increases. Load resistance element R1
2 becomes equivalently small, and the storage node A2 can be reliably maintained at the H level.

In the data holding state, access transistors Tr32 and Tr42 are off.
On the other hand, MOS transistors Tr52 and Tr62 are conductive. MOS transistors Tr52 and Tr
The resistance value of 62 is smaller than that at the time of data writing. If the ON resistance (channel resistance) of MOS transistors Tr52 and Tr is substantially equal to the resistance values of resistance elements R12 and R22, resistance elements R12 and R2
2 has a smaller equivalent resistance value. Therefore, in storage nodes A1 and B1, the storage nodes set to the H level can be driven to power supply voltage VCC level, and the reduction in the voltage level of the storage nodes is reliably suppressed. The pull-down resistance of storage nodes A1 and B1 other than during the data write operation is represented by the following equation.

For storage node A1: RT12 (ON / OFF) / RT52 (ON) / (RT
12 (ON / OFF) + RT52 (ON)), for the storage node B2: RT62 (ON) / RT22 (ON / OFF) / (RT
62 (ON) + RT22 (ON / OFF)).

That is, at the time of data writing, MO
S transistors Tr52 and Tr62 are turned off, and drive transistors Tr1 are turned on.
2 or Tr22, the resistance value of the corresponding load resistance element R12 or R22 is equivalently increased, and L level data can be accurately written. At the time other than writing, the MOS transistors Tr52 and Tr62 are set to the conductive state, the pull-down resistance of the storage nodes A2 and B2 is reduced, the current driving force is increased, and the resistance values of the resistance elements R12 and R22 are increased. Is equivalently reduced. Therefore, the power supply voltage V
Even when CC drops, storage nodes A2 and B
2, the voltage level of the H level can be sufficiently increased,
The operation lower limit voltage margin can be improved. Also,
During data holding, one of storage nodes A2 and B2 can be reliably held at the voltage level of power supply voltage VCC level, and the other can be held substantially at the ground voltage level, thereby ensuring the stability of memory cells. Can be.

As described above, according to the second embodiment of the present invention, a MOS transistor having a large channel resistance (on resistance) is provided in parallel with a drive transistor, and this MOS transistor is turned on except during data writing. Since the state is set, equivalently, the resistance value of the load resistance element is increased during data writing, and during other operations,
The resistance value of the load resistor can be reduced, and the write margin, the operation lower limit voltage operation characteristics, and the stability of the memory cell can be improved.

[Third Embodiment] FIG. 10 shows a structure of a memory cell MC and an adjusting circuit 10 according to a third embodiment of the present invention. In FIG. 10, memory cell MC
Is a P-channel MO connected between the power supply node and storage node A3 and having its gate connected to storage node B3.
S transistor (drive transistor) Tr53,
A P-channel MOS transistor (drive transistor) Tr63 connected between the power supply node and storage node B3 and having a gate connected to storage node A3, and a high-resistance resistance element connected between storage node A3 and the ground node R13, a high-resistance resistor R23 connected between the storage node B3 and the ground node, and an adjustment circuit 10 connected between the storage node A3 and the ground node and connected to the gate thereof.
An N-channel MOS transistor Tr13 receiving between the storage node B3 and the ground node and receiving at its gate the output signal L13 of the adjustment circuit 10, and a signal on the word line WL13. (Row selection signal),
Storage nodes A3 and B4 are connected to bit line / B, respectively.
P-channel MOS transistors (access transistors) Tr33 and Tr43 connected to IT and BIT
including.

Bit lines BIT and / BIT are precharged to L level. The row selection signal on word line WL13 is at the L level when selected, and is at the H level when not selected.

Adjustment circuit 10 includes an inverter circuit 13a receiving a row selection signal on word line WL13, and a NAND circuit 13b receiving output signal of inverter circuit 13a and write instruction signal W13 to output signal L13. MO
S transistors Tr13 and Tr23 have sufficiently large on-resistance (channel resistance) and function as pull-down elements when conducting. Next, an operation at the time of data writing of the memory cell shown in FIG. 10 will be described with reference to a signal waveform diagram shown in FIG.

At the time of data writing, write instructing signal W
13 goes high, and the row selection signal on the selected word line WL13 goes low. In this state, signal L13 from adjustment circuit 10 attains an L level, and MOS transistors Tr13 and Tr23 are turned off.
When word line WL13 is selected, access transistors Tr33 and Tr43 become conductive, and bit line BIT /
BIT is connected to storage nodes B3 and A3, respectively. Bit lines / BIT and BIT are precharged to L level, respectively, and at the time of data writing, bit line BIT is driven to H level. In this state, the voltage level of storage node B3 rises, and storage node A3 goes to L level. Drive transistor Tr53 is non-conductive, drive transistor Tr6
3 is turned on, and storage node B3 is connected to power supply voltage VC.
The C level and the storage node A3 are discharged by the resistance element R13 to attain the L level. When the bit line is driven to the H level, MOS transistors Tr13 and Tr2 are driven.
3 is a non-conductive state (OFF), equivalently, a state where high resistance elements R13 and R23 are connected to storage nodes A3 and B3, and a large pull-down resistance is applied to storage nodes A3 and B3. Connected. Therefore, storage node B3 is reliably driven to the level of power supply voltage VCC, and no H-level write failure occurs.

When data writing is completed, word line WL1
The row selection signal on line No. 3 goes high, and the write instruction signal W13 also goes low. The pull-down resistance between storage nodes A3 and B3 and the ground node at the time of data writing is represented by the following equation.

For storage node A3: R13.RT13 (OFF) / (R13 + RT13 (O
FF)), for the storage node B3: R23 / RT23 (OFF) / (R23 + RT23 (O
FF)).

Here, R23 and R13 are resistance elements R
13 and the resistance value of R23, and RT13 (OFF)
And RT23 (OFF) are MOS transistors Tr
13 and 13 show the off resistance of Tr23.

FIG. 12 shows a state in an operation mode other than the write operation of memory cell MC in the third embodiment of the present invention. As shown in the signal waveform diagram of FIG. 13, in an operation mode other than the write operation, write instruction signal W13 is at the L level, and adjustment is performed regardless of selection / non-selection of word line WL13. The output signal L13 of the circuit 10 maintains the H level. Therefore,
MOS transistors Tr13 and Tr23 maintain a conductive state (ON). In this state, a high resistance element R13 and M
The channel resistance of the OS transistor Tr13 is connected in parallel, and the resistance element R23 and the channel resistance of the MOS transistor Tr23 are connected in parallel between the storage node B3 and the ground node. The channel resistance (ON resistance) of the MOS transistors Tr13 and Tr23 is sufficiently large. Therefore, the resistance value of the pull-down resistor between each of storage nodes A3 and B3 and the ground node becomes smaller due to the parallel connection of these resistors as compared with the time of data writing. Therefore, L of storage nodes A3 and B3
The level is reliably driven to the ground voltage level, and even when the power supply voltage VCC is low, one of the drive transistors Tr53 and Tr63 can be reliably turned on, and the data can be reliably held without causing an operation lower limit voltage defect. can do.

Since the resistance value between each of storage nodes A3 and B3 and the ground node is low, all the leak currents from non-conductive drive transistors Tr53 and Tr63 can be discharged, and the voltage level of L level data can be reduced. Can be suppressed. Further, the resistance value of the pull-down resistor between each of storage nodes A3 and B3 and the ground node is surely one of storage nodes A3 and B3 because the channel resistance (on-resistance) of drive transistors Tr53 and Tr63 is sufficiently large. Can be held at the H level of the power supply voltage VCC level. The resistance value of the pull-down resistor between each of storage nodes A3 and B3 and the ground node in an operation mode other than the write operation is expressed by the following equation.

For storage node A3: R13.RT13 (ON) / (R13 + RT13 (O
N)), for the storage node B3: R23 / RT23 (ON) / (R23 + RT23 (O
N)).

Here, RT13 (ON) and RT23
(ON) indicates the on-resistance of the MOS transistors Tr13 and Tr23, respectively.

Therefore, in the configuration of the memory cell for bit line L level precharge and H level write,
At the time of data writing, the ground node and storage node A3
And B3 can be made sufficiently larger than the resistance value at the time of writing, to increase the write margin, and to improve the operation lower limit voltage characteristic and the data holding characteristic. Can be.

[Fourth Embodiment] FIG. 14 shows a configuration of an adjustment circuit 10 and a memory cell MC according to a fourth embodiment of the present invention. In FIG. 14, memory cell MC
Is a P-channel MO connected between the power supply node and storage node A4 and having its gate connected to storage node B4.
S transistor (drive transistor) Tr54,
A P-channel MOS transistor (drive transistor) Tr64 connected between a power supply node and storage node B4 and having a gate connected to storage node A4, and high resistances connected between storage nodes A4 and B4 and a ground node, respectively. Channel transistors (access transistors) connected between storage elements A4 and B4 and bit lines / BIT and BIT, respectively, and having a gate receiving a signal (row select signal) on word line WL14. Tr34 and Tr4
4, a P-channel MOS transistor Tr14 connected between the power supply node and storage node A4 and receiving at its gate the output signal L14 of adjustment circuit 10, an adjustment circuit connected between the power supply node and storage node B4 and having its gate connected 1
A P-channel MOS transistor Tr24 receiving output signal L14 of 0 is included.

Adjustment circuit 10 includes an inverter circuit 13b receiving a row selection signal on word line WL14, a NAND circuit 13b receiving an output signal of inverter circuit 13a and a write instruction signal W14, and an output signal of NAND circuit 13b. Includes inverter circuit 14 receiving and generating signal L14.

In the structure shown in FIG. 14, the voltage level of word line WL14 is set to L level in the selected state, and the voltage level is set to H level in the non-selected state. . Bit lines BIT and / BIT are precharged to L level, and at the time of data writing, bit lines BIT or / BIT precharged to L level are driven to H level. Next, the operation of memory cell MC shown in FIG. 14 will be described.

First, the operation at the time of data writing will be described with reference to FIG. At the time of data writing, when word line WL14 is selected, its voltage level goes low, and write instruction signal W14 goes high. Write instruction signal W14 attains H level, and word line W
When the row selection signal on L14 goes to L level, the output signal of NAND circuit 13b goes to L level, and in response, output signal L14 of inverter circuit 14 goes to H level.
The transistors Tr14 and Tr24 are turned off (O
FF). In this case, the drive transistor Tr5
4 and Tr64 have a channel resistance sufficiently smaller than the resistance values of resistance elements R14 and R24 when conducting, so that when writing this H-level data, storage node A4
Alternatively, B4 can be reliably driven to the power supply voltage VCC level. L of storage nodes A4 and B4
Since the corresponding drive transistor is rendered non-conductive, the storage node receiving the level data is reliably pulled down to the ground voltage level by resistance element R14 or R24. Storage node A at the time of data writing
4 and B4 and the resistance value between the power supply node are represented by the following equations.

For storage node A4: RT54 (ON / OFF) / RT14 (OFF) / (R
T54 (ON / OFF) + RT14 (OFF)), for the storage node B4: RT64 (ON / OFF) / RT24 (OFF) / (R
T64 (ON / OFF) + RT24 (OFF)).

Here, RT14 (OFF) and RT2
4 (OFF) indicates that the MOS transistors Tr14 and T
r24 represents the channel resistance in the off state, and is denoted by RT54.
(ON / OFF) and RT64 (ON / OFF)
Drive transistors Tr54 and Tr64 respectively
Shows the ON resistance / OFF resistance. Depending on the stored data,
These drive transistors Tr54 and Tr64
Is determined.

FIG. 16 shows a state other than the time of the write operation of memory cell MC in the fourth embodiment. Hereinafter, the state of the memory cell other than during the data write operation will be described with reference to a signal waveform diagram shown in FIG.

In FIG. 17, during a data read operation or a data holding state, write instruction signal W14 is at L level.
On the level. At the time of data reading, word line WL
14 is in the L-level selection state,
Signal L14 from adjustment circuit 10 maintains the L level. Therefore, regardless of the state of the row selection signal on word line WL14, MOS transistors Tr14 and Tr24 are turned on, and each operate as a pull-up element. In drive transistors Tr54 and Tr64, a conductive MOS transistor is connected in parallel with the non-conductive drive transistor, so that the resistance value between the power supply node and the corresponding storage node is reduced. The resistance value of the element becomes equivalently small. A conductive MOS transistor is connected between the power supply node and the storage node in parallel with the conductive drive transistor. In this case, the MOS transistor for pull-up is short-circuited by the drive transistor in the conductive state, and does not significantly affect data retention. For example, when storage node A4 is at H level and storage node B4 is at L level, drive transistor Tr54 is conductive, and
Storage node A4 is driven to power supply voltage VCC level. On the other hand, drive transistor Tr64 is off. In this case, if the channel resistance (ON resistance) of MOS transistor Tr24 is sufficiently larger than high resistance element R24 or the current driving force is sufficiently small, the channel of MOS transistor Tr24 is connected between the power supply node and the ground node. Even when the resistance and the resistance element R24 are connected in series, the voltage level of the storage node B4 can be maintained at the L level, and the drive transistor Tr54 can be reliably maintained in the conductive state.
The resistance values of the MOS transistors Tr14 and Tr24 and the resistance values of the resistance elements R14 and R24 satisfy the following expression.

[0105]

That is, at the time of writing, the resistance values of load resistance elements R14 and R24 are equivalently reduced, and the storage nodes storing L level of storage nodes A4 and B4 are reliably held at the ground voltage level.

In operation modes other than the data write operation, the pull-up resistors of storage nodes A4 and B4 are:
It is expressed by the following equation.

For storage node A4: RT14 (ON) / RT54 (ON / OFF) / (RT
14 (ON) + RT54 (ON / OFF)), for the storage node B4: RT24 (ON) / RT64 (ON / OFF) / (RT
24 (ON) + RT64 (ON / OFF)).

Here, RT24 (ON) and RT14
(ON) indicates the on-resistance of the MOS transistors Tr24 and Tr14, respectively.

As described above, according to the fourth embodiment of the present invention, a MOS transistor is provided in parallel with a pull-up drive transistor driven to an H level, and this MOS transistor is turned off during data writing. In other words, since the resistance value of the load resistance element at the H level at the time of data writing is made equivalently high at the time of data writing, and at other operation modes, Equivalently, the resistance value is reduced, or
The "eyeglasses" are equivalently reduced during writing and the "eyeglasses" are increased except during writing, so that L-level data and H-level data can be reliably written. Further, L level data of the storage node at the time of data holding can be reliably held at L level data, and
The level data can be held at the power supply voltage level, and the write margin, the lower limit operation voltage characteristic, and the data hold characteristic can be reliably improved.

[Fifth Embodiment] FIG. 18 shows a structure of an adjustment circuit 10 and a memory cell MC according to a fifth embodiment of the present invention. In FIG. 18, the adjustment circuit 10
Is a NAND circuit 15a receiving a write instruction signal W15 and a signal (row select signal) on word line WL15,
Inverter circuit 15b receiving an output signal of D circuit 15a
And a multiplexer 15c for selecting one of the power supply voltage VCC1 and the high voltage VCC2 according to the output signal of the inverter circuit 15b and outputting the selected signal as the adjustment signal L15.

The inverter circuit 15b has a high voltage VCC2
As one operation power supply voltage, and converts the signal of amplitude VCC1 from the NAND circuit 15a into a signal of amplitude VCC2. That is, the inverter circuit 15b has a level conversion function.

Memory cell MC is connected between a power supply node receiving power supply voltage VCC1 and storage node A5, has its gate connected to storage node B5, and further has an output signal (adjustment voltage) of adjustment circuit 10 connected to its back gate. ) L1
5, a P-channel MOS transistor (load transistor) Tr55 connected between storage node A5 and the ground node, an N-channel MOS transistor having its gate connected to storage node B5 and a back gate connected to the ground node (Drive transistor) Tr
15, an adjustment signal (voltage) from the adjustment circuit 10 connected between the power supply node and the storage node B5, the gate of which is connected to the storage node A5, and further connected to its back gate.
A P-channel MOS transistor (load transistor) Tr65 receiving L15; an N-channel MOS transistor Tr25 connected between storage node B5 and the ground node and having its gate connected to storage node A5 and a back gate connected to the ground node And the word line WL1
In accordance with the signal (row select signal) on memory cells A5 and B5, storage nodes A5 and B5 are connected to bit lines / BIT and BIT, respectively.
And N-channel MOS transistors (access transistors) Tr35 and Tr45 connected to the memory cell.

Access transistors Tr35 and Tr
The back gate of 45 is connected to the ground node.

The load transistors Tr55 and T55
r65 is formed of, for example, a thin film transistor, and only flows a leak current when not conducting. Bit lines BIT and / BIT are precharged to H level, and are driven to L level in accordance with write data at the time of data writing. Next, the operation of adjustment circuit 10 and memory cell MC shown in FIG. 18 will be described.

First, an operation at the time of data writing will be described with reference to FIG. At the time of data writing, first, write instruction signal W15 rises to the H level of power supply voltage VCC1, and then the row selection signal on word line WL15 rises to the level of power supply voltage VCC1. Accordingly, the output signal of inverter circuit 15b attains an H level, and multiplexer 15c selects high voltage VCC2 and outputs load signal transistors Tr55 and Tr55 as adjustment signal L15.
Give to 65 back gates. Therefore, in this state, the back gates of load transistors Tr55 and Tr65 are in a deep bias state, the threshold voltage increases, and the conductance (channel resistance) increases. In this state, one of storage nodes A5 and B5 is driven to L level according to write data via access transistors Tr35 and Tr45.

Since the channel resistance of load transistors Tr55 and Tr65 is increased due to the deep bias state, one of storage nodes A5 and B5 can be reliably driven to L level. When one of storage nodes A5 and B5 is reliably driven to the L level, one of load transistors Tr55 and Tr65 is reliably turned on even when the back gate bias is deep, and power supply voltage VCC1 is reduced. It can be transmitted to the corresponding storage node, and even when power supply voltage VCC1 is low, the voltage level of power supply voltage VCC1 is not less than the absolute value of the threshold voltage of load transistors Tr55 and Tr65 in a deep bias state. If so, data can be written accurately.

Next, an operation other than data writing will be described with reference to FIG. FIG. 20 shows a waveform at the time of data reading. At the time of data reading, even if word line WL15 is driven to the selected state, write instruction signal W
Reference numeral 15 denotes an L level, the output signal of the NAND circuit 15a maintains the H level, and the output signal of the inverter circuit 15b changes to the L level. Accordingly, multiplexer 1
5c selects the power supply voltage VCC1 and applies it to the back gates of the load transistors Tr55 and Tr65. Therefore, the back gate biases of load transistors Tr55 and Tr65 become shallower than at the time of data writing, and their conductance becomes larger than that at the time of data writing (the absolute value of the threshold voltage becomes smaller). Regardless of the conduction / non-conduction state, the load transistors Tr55 and Tr65 have a larger conductance (reduced channel resistance) than the data write when the sub-threshold region is also taken into consideration. Therefore,
The leakage current of the drive transistors Tr15 and Tr25 is reliably guaranteed, and the load transistor Tr in the conductive state is
55 or Tr65 to supply current,
It is possible to prevent the voltage level of the level data from lowering.

Drive transistor Tr15 or Tr
When 25 is conductive, its corresponding load transistor Tr55 or Tr65 is nonconductive, corresponding storage node A5 or B5 is reliably held at the ground voltage level, and the rise of the voltage level of L level data is ensured. Can be prevented. Therefore, it is possible to reliably prevent the voltage level of the storage node of the memory cell from reaching the intermediate voltage level and the memory cell from becoming unstable.

At the time of data reading, access transistors Tr35 and Tr45 are on, and bit lines BIT and / BI precharged to H level are attained.
One of T is the drive transistor Tr15 or Tr
25, discharge is performed and the voltage level is lowered, so that stored data can be reliably read.

As described above, according to the fifth embodiment of the present invention, since the back gate bias of the load transistor is made deep during data writing, the write margin and the stability of the memory cell can be improved. it can.

In the above description, bit line B
IT and / BIT are precharged to H level,
At the time of data writing, these bit lines BIT and / BIT
Is driven to the L level. However, bit lines BIT and / BIT are precharged to L level, and when writing data, these bit lines BI
One of T and / BIT may be driven to the H level (the voltage level of the selected word line becomes the L level). In this case, the access transistor Tr3
5 and Tr45 are each formed of a P-channel MOS transistor, and have a power supply voltage VCC
Receive 1 Word line WL15 is driven to L level when selected.

[Sixth Embodiment] FIG. 21 shows a configuration of an adjustment circuit 10 and a memory cell MC according to a sixth embodiment of the present invention. In FIG. 21, the adjustment circuit 10
Are the row selection signal on the word line WL16 and the write instruction signal W
16 and a NAND circuit 16a receiving the same.
a level conversion circuit 16b for converting the level of the output signal
And a multiplexer 16c for selecting one of the ground voltage GND1 and the negative voltage GND2 according to the output signal of the level conversion circuit 16b. Level conversion circuit 16b receives power supply voltage VCC1 and negative voltage GND2 as operation power supply voltages, and converts the L level of the output signal of NAND circuit 16a to the level of negative voltage GND2. Multiplexer 16c
Selects the negative voltage GND2 when the output signal of the level conversion circuit 16b is at the H level,
Is low, the ground voltage GND1 is selected.

Memory cell MC is connected between the power supply node and storage node A6 and has its gate connected to storage node B.
6, a P-channel MOS transistor (load transistor) Tr56 connected to storage node A6, an N-channel MOS transistor (drive transistor) Tr16 connected between storage node A6 and the ground node and having its gate connected to storage node B6, A P-channel MOS transistor (load transistor) Tr66 connected between storage node A and storage node B6 and having its gate connected to storage node A6, and a gate connected between storage node B6 and the ground node and having its gate connected to storage node N connected to A6
Channel MOS transistor (drive transistor)
Tr26 is included. Load transistors Tr56 and Tr
The back gate of 66 is connected to a power supply node receiving power supply voltage VCC. The back gates of drive transistors Tr16 and Tr26 are connected to the ground node.

The memory cell MC further includes a word line WL
16 includes N-channel MOS transistors (access transistors) Tr36 and Tr46 which are rendered conductive in accordance with a row selection signal and connect storage nodes A6 and B6 to bit lines / BIT and BIT, respectively. Output voltage L16 of multiplexer 16c of adjustment circuit 10 is applied to the back gates of access transistors Tr36 and Tr46.

The load transistors Tr56 and T
r66 is formed of, for example, a thin film transistor. Next, adjustment circuit 10 and memory cell M shown in FIG.
The operation of C will be described.

First, the operation at the time of data writing will be described with reference to FIG. Bit lines BIT and / BIT
Are precharged to an H level, and at the time of data writing, bit lines BIT and / BIT are set according to write data.
Is driven to L level. At the time of data writing, when write instruction signal W16 attains an H level and word line WL16 attains a selected state, the output signal of NAND circuit 16a attains an L level of the ground voltage level.
The output signal of level conversion circuit 16b attains the voltage level of negative voltage GND2. In response, multiplexer 16c outputs ground voltage GND1. Therefore, in this state, access transistors Tr36 and Tr46
The back gate bias becomes shallow and the channel resistance decreases, that is, the current driving force increases. Therefore, in this state, the β ratio decreases, the transfer characteristics of the CMOS inverter of memory cell MC deteriorate, and the voltage levels of storage nodes A6 and B6 can be changed at high speed in accordance with the write data. .

When data writing is completed, word line WL1
6 goes low, and the write instruction signal W16 also goes low. This word line WL16 or write instruction signal W
When 16 is at L level, level conversion circuit 16b is at H level.
A level signal is output, and the multiplexer 16c selects the negative voltage GND2.

In an operation mode other than the data write operation, in the data read operation, as shown in FIG. 23, even if the row selection signal on word line WL16 attains the H level, write instruction signal W16 does not change. To maintain L level,
From the multiplexer 16c to the access transistor Tr3
6 and T46 are supplied with a negative voltage GND2 to their back gates, and these load transistors Tr36 and Tr4
6, the back gate bias becomes deeper, and its threshold voltage becomes higher. Therefore, the current drivability of access transistors Tr36 and Tr46 is reduced, and at the time of data reading, access transistors Tr36 and Tr46 and drive transistor T
When the β ratio of r16 and Tr26 increases, the transfer characteristic of memory cell MC becomes stable, and when the voltage levels of bit lines BIT and / BIT are precharged to H level, the stored data is not destroyed. One bit line can be driven to L level, and data can be read accurately.

In the data holding state, access transistors Tr36 and Tr46 are off, and
One of load transistors Tr56 and Tr66 is turned off and the other is turned on, and data is stably held in storage nodes A6 and B6. When the load transistors Tr56 and Tr66 are non-conductive, the corresponding drive transistors Tr16 and Tr26 are in a conductive state, and the voltage level of the corresponding storage node is reliably prevented from rising. Further, when the load transistors Tr56 and Tr66 are turned on, the corresponding drive transistors are in a non-conductive state, the current driving force of the corresponding drive transistors is sufficiently larger than that of the corresponding drive transistors, and the corresponding storage nodes are surely connected. It can be maintained at the H level of the power supply voltage level.

As described above, according to the sixth embodiment of the present invention, at the time of data writing, the back gate bias of the access transistor is made deep, so that the β ratio of the access transistor and the drive transistor at the time of data writing is reduced. As a result, the transfer characteristics of the memory cell deteriorate, and the storage node can be easily set to a voltage level corresponding to the write data.

The ground voltage GND1 may be a negative voltage. Voltages GND1 and GND2 are equal to GND1>
It suffices if the relationship of GND2 is satisfied and the voltage GND1 is used as the source voltage of the drive transistor.

In the structure shown in FIG. 21, P transistors are used as access transistors Tr36 and Tr46.
When channel MOS transistors are used, a power supply voltage for data writing and a high voltage higher than the power supply voltage for other operations are applied to the back gates of these access transistors. Even with this configuration, a similar effect can be obtained.

[Seventh Embodiment] FIG. 24 shows a structure of an adjustment circuit 10 and a memory cell MC according to a seventh embodiment of the present invention. In FIG. 24, the adjustment circuit 10
Includes a NAND circuit 17a receiving a signal (row select signal) on word line WL17 and write instruction signal W17,
Inverter circuit 17b for inverting the output signal of circuit 17a
And a multiplexer 17c for selecting one of the ground voltage GND1 and the negative voltage GND2 according to the output signal of the inverter circuit 17b.

The inverter circuit 17b has a power supply voltage VCC.
1 and negative voltage GND2 as an operating power supply voltage, and converts the L level of the output signal of NAND circuit 17a to the level of negative voltage GND2. That is, the inverter circuit 17b has a level conversion function, and
In step c, one of the negative voltage GND2 and the ground voltage GND1 is reliably selected. Multiplexer 17c is formed of, for example, a CMOS transmission gate and receives a ground voltage GN according to an output signal of inverter circuit 17b.
One of D1 and negative voltage GND2 is selected.

Memory cell MC is connected between the power supply node and storage node A7 and has its gate connected to storage node B.
7, a P-channel MOS transistor (load transistor) Tr57 connected to storage node A7, an N-channel MOS transistor (drive transistor) Tr10 connected between storage node A7 and the ground node and having a gate connected to storage node B7, P-channel MOS transistor (load transistor) Tr67 connected between storage node A and storage node B7 and having a gate connected to storage node A7, and connected between storage node B7 and a ground node and having a gate connected to storage node B7 N connected to A7
Channel MOS transistor (drive transistor)
Tr27 is made conductive according to a row selection signal on word line WL17, and storage nodes A and B7 are connected to bit line /
BIT and N-channel MOS transistors (access transistors) Tr37 and Tr4 connected to BIT
7 inclusive.

The back gates of load transistors Tr5 and Tr67 are connected to the power supply node, and the back gates of access transistors Tr37 and Tr47 are connected to the ground node. A multiplexer 17c is connected to the back gates of the drive transistors Tr17 and Tr27.
Is applied. Next, the operation of the multiplexer and memory cell MC shown in FIG. 24 will be described with reference to signal waveform diagrams shown in FIGS. 25 and 26.

First, an operation at the time of data writing will be described with reference to FIG. At the time of data writing, when write instructing signal W17 and the row selection signal on word line WL17 attain H level, the output signal of NAND circuit 17a attains L level, and the output signal of inverter circuit 17b accordingly changes to H level.
Level, and the multiplexer 17c outputs the negative voltage GND.
Select 2. Therefore, the back gate bias of drive transistors Tr17 and Tr27 becomes deep, and drive transistors Tr17 and Tr27 become deeper.
The current driving force of r27 decreases. Access transistors Tr37 and Tr47 are rendered conductive in accordance with a row selection signal on word line WL17, and storage nodes A7 and B7 are connected to bit lines / BIT and BIT. These bit lines BIT and / BIT are precharged to H level, and one of them is driven to L level in accordance with write data at the time of data writing. In this state, the so-called β ratio (ratio of current driving force) between access transistors Tr37 and Tr47 and drive transistors Tr17 and Tr27 is reduced, and the data holding characteristic (transfer characteristic) of memory cell MC is reduced. Accordingly, an L level voltage can be written to storage nodes A7 and B7 at a high speed. When the data writing is completed, the row selection signal goes low and the write instruction signal W17 goes low, and the output signal of inverter circuit 17b goes low accordingly.
Level, and the multiplexer 17c outputs the ground voltage GN
Select D1. Therefore, drive transistor T
The bias voltages of the back gates of r17 and Tr27 become the ground voltage GND1.

Referring to FIG. 26, description will now be given on operations other than data writing. Now, as shown in FIG.
At the time of data reading, even if word line WL17 is selected and its row selection signal rises to H level, write instruction signal W17 is at L level. In this state,
The output signal of inverter circuit 17b is at L level, and multiplexer 17c selects ground voltage GND1 as its output voltage L17, and the current drivability of drive transistors Tr17 and Tr27 is larger than that during data writing. (A large drain current can flow because the threshold voltage is low). Therefore,
When access transistors Tr37 and Tr47 are turned on in accordance with the row selection signal, access transistors Tr37 and Tr47 and drive transistor Tr1
7 and Tr27 have a large β ratio,
Data can be read stably (so-called memory cell transmission characteristics are large). Further, since the β ratio is large, data can be stably held even in the data holding state.

As described above, according to the seventh embodiment of the present invention, the back gate bias of the drive transistor is made deeper at the time of data writing, and at other times, the back gate bias is made shallower. The ratio can be reduced during writing, data can be written at high speed, and the so-called "eye" of the memory cell transfer characteristic can be increased during data reading and data holding. Data can be stably held and read.

In the structure shown in FIG. 24, access transistors Tr37 and Tr47 are formed of P channel MOS transistors, bit lines BIT and / BIT are precharged at L level, and H level data is written at the time of data writing. May be used.

The ground voltage GND1 may be a negative voltage. [Other Configurations] In the first to seventh embodiments, each example is described individually. However, Embodiments 1 and 2 may be used in combination. Further, the third and fourth embodiments may be used in combination. Further, Embodiments 5 to 7 may be used in combination.

[0143]

As described above, according to the present invention, at the time of data writing, the resistance value of the load resistor is increased or the β ratio is reduced, so that data can be written accurately at high speed. Can be performed, and data can be stably held.

That is, according to the invention of the first aspect, the structure is such that the equivalent resistance between the first power supply node and the storage node during data writing is increased. The margin can be improved, the lower-limit power supply voltage characteristics, and the stability of the memory cell can be improved.

If this equivalent resistance is constituted by an auxiliary transistor connected in parallel with the load resistance and this auxiliary transistor is turned off at the time of data writing, the resistance value of the load element can be easily reduced with a simple circuit configuration. It can be increased equivalently at the time of writing. In addition, by using both the selection signal and the write instruction signal as the resistance adjustment signal, the characteristics of the memory cells can be adjusted on a row-by-row basis, and the required characteristics of the memory cells can be adjusted using a small circuit. can do.

According to the second aspect of the present invention, the amount of drive current of the drive transistor is equivalently reduced at the time of data writing, and the resistance value of the load resistor is correspondingly reduced at the time of data writing. The data can be increased (supply current decreases), data can be accurately written, data can be stably held, and the lower-limit operation voltage characteristic can be further improved.

Further, in this configuration, by arranging an auxiliary transistor which becomes non-conductive when the write instruction signal and the row selection signal are activated in parallel with the drive transistor, it is possible to easily obtain a necessary portion with a simple circuit configuration. It is possible to control the equivalent drive current of the drive transistor of the memory cell.

According to the third aspect of the present invention, the equivalent resistance of the load element of the memory cell is adjusted by the adjustment circuit outside the cell, so that the write margin, the lower limit voltage characteristic, and the like can be easily improved. The stability of the memory cell can be improved.

Further, in this configuration, the back gate bias of the load transistor is increased when both the row selection signal and the write instruction signal are activated during data writing, so that the writing characteristics can be easily improved, the lower limit voltage characteristics and the lower limit voltage characteristics can be easily improved. It is possible to improve the stability of the memory cell.

According to a fourth aspect of the present invention, the adjustment circuit outside the memory cell increases the equivalent resistance of the drive transistor during data writing, and accordingly increases the resistance of the load element equivalently during data writing. Can be larger,
It is possible to easily improve the writing characteristics and the lower limit voltage characteristics and the stability of the memory cell.

In this configuration, by increasing the back gate bias of the drive transistor during data writing in accordance with the row selection signal and the write instruction signal, the current drivability of the drive transistor can be reduced. The ratio can be reduced, data can be written at high speed, and data can be stably held.

According to the fifth aspect of the present invention, the channel resistance of the access transistor is reduced at the time of data writing by the adjustment circuit outside the cell, and accordingly, the current driving force is increased. The ratio can be reduced, and high-speed data writing and stable data holding can be realized.

In this configuration, the back gate bias of the access transistor is made shallower at the time of writing according to the row selection signal and the write instruction signal, so that the current drivability of the access transistor can be easily increased at the time of data writing. .

When the voltage of the power supply node connected to the load element is lower than the voltage of the power supply node connected to the drive transistor, the write characteristics of the bit line L-level precharge and H-level write memory cells are improved and It is possible to improve the stability of the memory cell and the operation lower limit voltage characteristic.

Conversely, if the voltage of the power supply node connected to the load element is higher than the voltage of the power supply node connected to the drive transistor, the bit line H level precharge and L level write memory cell write Of the memory cell, stability of the memory cell, improvement of the operation lower limit voltage characteristic, and stability of the memory cell can be realized.

By adjusting the back gate bias of the load transistor at the time of writing with reference to the power supply voltage, the back gate bias of the load transistor can be easily controlled at the time of data writing and other operation modes. Can be performed.

Also, the back gate bias of the drive transistor is set with reference to the voltage of the second power supply node.
The adjustment makes it possible to easily adjust the back gate bias of the drive transistor in data writing and in other operation modes.

By adjusting the back gate bias of the access transistor with reference to the voltage of the second power supply node, the back gate bias of the access transistor during data writing and other operation modes can be easily adjusted. can do.

According to the sixth aspect of the present invention, the write characteristics can be easily improved by increasing the equivalent resistance of the load circuit by the adjustment circuit outside the memory cell at the time of data writing.
The operation lower limit voltage characteristics and the stability of the memory cell can be improved.

In this configuration, the load circuit is composed of a load element and a transistor element connected in parallel with the load element, and by setting this transistor element to a non-conductive state at the time of data writing, data can be easily obtained. The resistance value of the load circuit at the time of writing can be increased.

Further, by configuring the load circuit with an insulated gate transistor whose back gate bias is adjusted according to the operation mode, the resistance value of the load circuit can be easily adjusted according to the operation mode. Can be.

According to the seventh aspect of the present invention, the resistance value of the load element at the time of data writing is equivalently increased by reducing the amount of drive current of the drive circuit at the time of data writing. Of the memory cell, the lower limit voltage characteristic and the stability of the memory cell can be realized.

By configuring this drive circuit with an insulated gate transistor whose back gate bias is adjusted according to the operation mode, the equivalent resistance value of the drive circuit can be easily adjusted without increasing the cell area. Can be.

This drive circuit is composed of a drive transistor and an auxiliary transistor connected in parallel with the drive transistor, and the auxiliary transistor is turned off at the time of data writing, whereby The equivalent resistance can be increased, and the resistance of the load element can be equivalently increased accordingly, thereby improving the write characteristics, operating lower limit voltage characteristics, and the stability of the memory cell.

According to the eighth aspect of the present invention, the back gate bias of the memory cell is made shallow at the time of data writing, and accordingly, the β ratio of the memory cell at the time of data writing can be reduced. Data can be written accurately, and in operations other than the write mode, the back gate bias is made deeper than at the time of writing, and data can be held stably by optimizing the β ratio. it can.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a configuration of a main part of a semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing a configuration of a memory cell and an adjustment circuit according to the first embodiment of the present invention.

FIG. 3 is a signal waveform diagram representing an operation at the time of data writing of the configuration shown in FIG. 2;

FIG. 4 is a diagram showing a state in an operation mode other than the data writing of the memory cell according to the first embodiment of the present invention;

FIG. 5 is a signal waveform diagram showing an operation of the adjustment circuit shown in FIG.

FIG. 6 shows a configuration of a memory cell and an adjustment circuit according to a second embodiment of the present invention.

7 is a signal waveform diagram representing an operation of the adjustment circuit shown in FIG. 6 at the time of data writing.

FIG. 8 is a diagram showing a state during an operation other than the data writing of the memory cell according to the second embodiment of the present invention;

9 is a signal waveform diagram illustrating an operation in an operation mode other than the data writing of the configuration shown in FIG. 8;

FIG. 10 shows a configuration of a memory cell and an adjustment circuit according to a third embodiment of the present invention.

11 is a signal waveform diagram representing an operation of the adjustment circuit shown in FIG. 10 at the time of data writing.

FIG. 12 shows a state of a memory cell according to a third embodiment of the present invention in an operation mode other than the data write mode.

13 is a signal waveform diagram illustrating an operation of the adjustment circuit in a state of the memory cell illustrated in FIG.

FIG. 14 shows a structure of a memory cell and an adjustment circuit according to a fourth embodiment of the present invention.

15 is a signal waveform diagram representing an operation of the adjustment circuit at the time of data writing in the memory cell shown in FIG.

FIG. 16 is a diagram showing a state of the memory cell in an operation other than the data write mode in the fourth embodiment of the present invention;

17 is a signal waveform diagram representing an operation of the adjustment circuit for the memory cell shown in FIG.

FIG. 18 shows a structure of a memory cell and an adjustment circuit according to a fifth embodiment of the present invention.

19 is a signal waveform diagram representing an operation of the adjustment circuit shown in FIG. 18 at the time of data writing.

20 is a signal waveform diagram representing an operation of the adjustment circuit shown in FIG. 18 in an operation mode other than the data write mode.

FIG. 21 shows a structure of a memory cell and an adjustment circuit according to a sixth embodiment of the present invention.

22 is a signal waveform diagram representing an operation during data writing of the adjustment circuit shown in FIG. 21.

23 is a signal waveform diagram representing an operation in an operation mode other than the data write mode of the adjustment circuit shown in FIG. 21.

FIG. 24 shows a structure of a memory cell and an adjusting circuit according to a seventh embodiment of the present invention.

25 is a signal waveform diagram representing an operation of the adjustment circuit shown in FIG. 24 at the time of data writing.

26 is a signal waveform diagram representing an operation of the adjustment circuit shown in FIG. 24 in an operation mode other than the data write mode.

FIG. 27 is a diagram showing a configuration of a conventional memory cell.

FIG. 28 is a diagram showing an operation at the time of reading data from a conventional memory cell.

FIG. 29 is a diagram showing an operation at the time of data writing in a conventional memory cell.

FIG. 30 is a diagram schematically showing an internal current in a data holding state of a conventional memory cell.

[Explanation of symbols]

10, 10a-10c adjustment circuit, MC, MCA-MC
C memory cell, Tr11-Tr13, Tr21-Tr
23, Tr15-Tr17, Tr25-Tr27, Tr
52, Tr62 N-channel MOS transistor, Tr
51, Tr61, Tr53, Tr63, Tr54-Tr
57, Tr64-Tr67 P-channel MOS transistors, 11a, 12, 13b, 15a, 16a, 17a
NAND circuit, 11b, 13a, 14, 15b, 17
b Inverter, 15c, 16c, 17c multiplexer.

Claims (22)

[Claims] A first load element connected between a first power supply node and a first storage node; a second power supply node; a first load element connected between the first power supply node and the first storage node; A second load element connected between the second storage node and a second load element connected between the first storage node and a second power supply node, selectively connected according to a voltage of the second storage node; A first drive transistor that is turned on; a second drive transistor that is connected between the second power supply node and the second storage node and that is selectively turned on according to the voltage of the first storage node; A drive transistor, a first access transistor connecting the first storage node to a first bit line in response to a row selection signal on a word line, and a second access transistor in response to a row selection signal on the word line. Storage node to the second bit A semiconductor device comprising: a second access transistor connected to a line; and an adjustment circuit for increasing an equivalent resistance between each of the first and second storage nodes and the first power supply node during data writing. Storage device. 2. The adjustment circuit is connected between the first power supply node and the first storage node in parallel with the first load element, and instructs the row selection signal and data writing. A first auxiliary transistor that is turned off when both write instruction signals are activated, and a first auxiliary transistor that is connected in parallel with the second load element between the first power supply node and the second storage node; 2. The semiconductor memory device according to claim 1, further comprising: a second auxiliary transistor which is turned off when both said row selection signal and said write instruction signal are activated. 3. A semiconductor device comprising: a plurality of memory cells, each of the memory cells comprising: a first load element connected between a first power supply node and a first storage node; A second load element connected between the second storage node, and a second load element connected between the first storage node and the second power supply node and according to a voltage on the second storage node A first drive transistor that is selectively turned on; a first drive transistor that is connected between the second power supply node and the second storage node and that is selectively turned on according to a voltage of the first storage node; A second drive transistor that connects the first storage node to a first bit line in response to a row select signal on a word line; and a second access transistor that responds to a row select signal on the word line. To store the second storage node in the second storage node. A second access transistor connected to the bit line, and an adjustment circuit for reducing the amount of drive current between each of the first and second storage nodes and the second power supply node during data writing. A semiconductor memory device. 4. The adjustment circuit is connected between the first storage node and the second power supply node in parallel with the first drive transistor,
A first auxiliary transistor which is turned off when both the row selection signal and a write instruction signal for instructing data writing are activated; a second storage node in parallel with the second drive transistor; 4. The semiconductor memory device according to claim 3, further comprising: a second auxiliary transistor connected between the second power supply node and said second power supply node, said second auxiliary transistor being turned off when both said row select signal and said write instruction signal are activated. 5. A semiconductor device, comprising: a plurality of memory cells, wherein each of the memory cells includes a first load element connected between a first power supply node and a first storage node; A second load element connected between the second storage node, and a second load element connected between the first storage node and the second power supply node, and according to a voltage on the second storage node. A first drive transistor that is selectively turned on, connected between the second power supply node and the second storage node, and selectively depending on a voltage on the first storage node. A second drive transistor that is turned on; a first access transistor that connects the first storage node to a first bit line in response to a row selection signal on a word line; and a row selection signal on the word line In response to the second storage node A second access transistor connected to a second bit line; and an adjustment for increasing an equivalent resistance between the first and second storage nodes and the first power supply node during data writing. A semiconductor memory device including a circuit. 6. Each of the first and second load elements is constituted by an insulated gate transistor, and the adjustment circuit activates both a write instruction signal instructing data writing and the row selection signal. 6. The semiconductor memory device according to claim 5, further comprising a switching circuit for deepening a back gate bias of said insulated gate transistor. 7. A memory device, comprising: a plurality of memory cells, each of the memory cells comprising: a first load element connected between a first power supply node and a first storage node; A second load element connected between the second storage node and a second load element connected between the first storage node and a second power supply node and selected according to a voltage of the second storage node; A first drive transistor that is electrically conductive, and is selectively connected to the second power supply node between the second power supply node and the second storage node according to a voltage of the first storage node. A second drive transistor, a first access transistor connecting the first storage node to a first bit line in response to a row selection signal on a word line, and a second access transistor in response to a row selection signal on the word line. The second storage node to a second Adjusting circuit for increasing an equivalent resistance between the first and second storage nodes and the second power supply node at the time of data writing. A semiconductor storage device comprising: 8. Each of the first and second drive transistors is constituted by an insulated gate transistor, and the adjustment circuit activates both a write instruction signal instructing data writing and the row selection signal. 8. The semiconductor memory device according to claim 7, further comprising: a switching circuit for increasing a back gate bias of said insulated gate transistor in response to the control signal. 9. A semiconductor device comprising: a plurality of memory cells, each of the memory cells comprising: a first load element connected between a first power supply node and a first storage node; A second load element connected between the second storage node and a second load element connected between the first storage node and a second power supply node and selected according to a voltage of the first storage node; A first drive transistor that is electrically conductive, and is selectively connected to the second power supply node between the second power supply node and the second storage node according to a voltage of the first storage node. A second drive transistor, a first access transistor connecting the first storage node to a first bit line in response to a row selection signal on a word line, and a second access transistor in response to a row selection signal on the word line. The second storage node to a second And a second access transistor connected to Tsu preparative lines, further, the data write operation, and a regulating circuit for reducing the channel resistance of the first and second access transistors, the semiconductor memory device. 10. Each of said first and second access transistors is constituted by an insulated gate transistor, and said adjustment circuit activates both said row selection signal and a write instruction signal instructing data writing. 10. The semiconductor memory device according to claim 9, further comprising: a switching circuit for reducing a back gate bias of said insulated gate transistor in response to the control signal. 11. The voltage of the first power supply node is lower than the voltage of the second power supply node.
10. The semiconductor memory device according to any one of 5, 7, and 9. 12. The power supply node according to claim 1, wherein a voltage of said first power supply node is higher than a voltage of said second power supply node.
10. The semiconductor memory device according to any one of 5, 7, and 9. 13. The switching circuit, when both the write instruction signal and the row selection signal are activated, applies a voltage whose absolute value is larger than the voltage of the first power supply node to the back gate of the insulated gate transistor. 7. The semiconductor according to claim 6, wherein a voltage having the same voltage level as the voltage of said first power supply node is applied to said back gate when said voltage is applied and at least one of said write instruction signal and said row selection signal is inactivated. Storage device. 14. The switching circuit, when both the write instruction signal and the row selection signal are activated, applies a voltage whose absolute value is larger than the voltage of the second power supply node to the back gate of the insulated gate transistor. 9. The semiconductor according to claim 8, wherein a voltage having the same voltage level as the voltage of said second power supply node is applied to said back gate when said voltage is applied and at least one of said write instruction signal and said row selection signal is inactivated. Storage device. 15. The switching circuit, when both the write instruction signal and the row selection signal are activated, applies a first voltage of the same voltage level as the voltage of the second power supply node to the back gate of the insulated gate transistor. 2. A bias voltage is applied, and a voltage having at least one of the write instruction signal and the row selection signal when inactive when the absolute value is larger than the first bias voltage is applied to the back gate.
0. A semiconductor memory device according to item 0. 16. A semiconductor device comprising: a plurality of memory cells, each of the memory cells comprising: a first load circuit connected between a first power supply node and a first storage node; A second load circuit connected between the second storage node and a second load circuit connected between the first storage node and a second power supply node, selected according to a voltage of the second storage node; A first drive transistor which is electrically conductive, and which is connected between the second power supply node and the second storage node and is selectively conductive according to the voltage of the first storage node A second drive transistor, a first access transistor connecting the first storage node to a first bit line in response to a row select signal on a word line, and a first access transistor in response to a row select signal on the word line Storing the second storage node in a second And a second access transistor connected to preparative lines, further, the data write operation, comprise an adjusting circuit for increasing the equivalent resistance of the first and second load circuits, the semiconductor memory device. 17. The first load circuit, wherein: a first load element connected between the first power supply node and the first storage node; and a first load element connected to the first power supply node and the first storage node. A first transistor element connected between the first storage node and the second storage circuit, and receiving the output signal of the adjustment circuit at its gate, wherein the second load circuit includes the first power supply node and the second storage node. A second load element connected between the node;
A second transistor element connected between the first power supply node and the second storage node in parallel with the second load element and receiving an output signal of the adjustment circuit at a gate; 17. The semiconductor memory device according to claim 16, wherein the adjustment circuit turns off the first and second transistors when both the row selection signal and a write instruction signal instructing data writing are activated. 18. A first insulated gate type circuit, wherein the first load circuit is connected between the first power supply node and the first storage node and receives an output signal backgate of the adjustment circuit. A second insulated gate type connected between the first power supply node and the second storage node and receiving an output signal of the adjustment circuit at a back gate; The semiconductor device further comprising: a transistor; wherein the adjusting circuit deepens a back gate bias of the first and second insulated gate transistors when both the row selection signal and a write instruction signal instructing data writing are activated. 17. The semiconductor memory device according to item 16. 19. A semiconductor device comprising: a plurality of memory cells, each of the memory cells comprising: a first load element connected between a first power supply node and a first storage node; A second load element connected between the first storage node and a second power supply; a second load element connected between the first storage node and a second power supply;
A first drive circuit that drives and holds the first storage node at a voltage level of the second power supply node in accordance with a voltage of the second storage node; A second storage node connected between the second storage node and the second power supply node in accordance with the voltage of the first storage node. A drive circuit, a first access transistor connecting the first storage node to a first bit line in response to a row selection signal on a word line, and a first access transistor in response to a row selection signal on the word line. And a second access transistor connecting the second storage node to the second bit line, and an adjustment circuit for reducing the amount of drive current of the first and second drive circuits during data writing. Prepare, half Conductor storage. 20. The first drive circuit, comprising:
A first insulated gate transistor connected between the storage node and the second power supply node, the gate of which is connected to the second storage node, and the back gate of which receives the output voltage of the adjustment circuit. The second drive circuit is connected between the second storage node and the second power supply node, has a gate connected to the first storage node, and further controls an output voltage of the adjustment circuit. A second insulated gate transistor received at a back gate; wherein the adjustment circuit is configured to activate the first and second transistors when both the row selection signal and a write instruction signal instructing data writing are activated.
20. The semiconductor memory device according to claim 19, wherein the back gate bias of the insulated gate transistor is deepened. 21. The first drive circuit, comprising:
A first drive transistor connected between the storage node and the second power supply node and having a gate connected to the second storage node; the first storage node and the second power supply node A second auxiliary circuit connected between the second storage node and the second power supply node, the first auxiliary transistor being connected between the second storage node and the second power supply node. A second drive transistor connected to the first storage node and having a gate connected to the first storage node; and an output of the adjustment circuit connected between the second storage node and the second power supply node. A second auxiliary transistor receiving a signal at a gate thereof, wherein the adjustment circuit responds to activation of both the row selection signal and a write instruction signal instructing data writing, and The auxiliary transistor non-conductive, the semiconductor memory device according to claim 19, wherein. 22. A semiconductor device comprising a plurality of memory cells, each of the memory cells comprising: a first load element connected between a first power supply node and a first storage node; A second load element connected between the first storage node and a second power supply; a second load element connected between the first storage node and a second power supply;
A first drive element that drives and holds the first storage node at a voltage level of the second power supply node in accordance with a voltage of the second storage node; A second storage node connected between the second storage node and the second power supply node for driving and maintaining the voltage level of the second storage node and the second power supply node according to the voltage of the first storage node. A drive element, a first access transistor for connecting the first storage node to a first bit line in response to a row selection signal on a word line, and having a shallow back gate bias during data writing; A second access transistor connecting the second storage node to a second bit line and having a reduced back gate bias during data writing in response to a row selection signal of .