JP2002111772A - Receiving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce or replace a function unit with large power consumption. SOLUTION: After a signal received by an antenna wire is passed through a receive band filter 96 and changed into a band inside signal group, an I-axis factor and a Q-axis factor are extracted by a quadrature demodulation unit 11. An unnecessary high frequency factor is removed from the signal through first and second low-pass filters 86 and 87, and the signal is inputted to first and second A/D converters 90 and 91. As to the A/d converting operation in the A/D converters 90 and 91, a sampling signal from a sampling signal generating source 92 is fed to the A/D converters 90 and 91 and sampled to obtain a base band output from an arithmetic unit 93. In this case, only one quadrature demodulator is used, so the power consumption can be reduced and the circuit can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving circuit of a mobile communication device, and more particularly to a receiving circuit capable of reducing the power of a receiving system, simplifying a circuit configuration, and reducing power consumption.

[0002]

2. Description of the Related Art One of the points of a receiving circuit of a mobile communication device is how to reduce the number of high-frequency circuits, high power consumption elements and unstable operations inherent in high-frequency circuits, manufacturing costs, and the space occupied. It is in. Among them, in order to reduce the high-frequency circuit portion, conventionally, a multiplex frequency conversion and a direct demodulation method at a carrier frequency have been proposed, and a direct conversion to a low frequency band and a direct demodulation to a baseband band have been attempted. The function of occupying the high frequency circuit is the space diversity function that requires two antennas.

[0003]

Here, considering the direct demodulation method, many methods have been developed in which a signal equal to the carrier frequency is generated by a local oscillator and mixed with a received input wave to extract a baseband signal. However, in this method,
Because it generates a high frequency signal equal to the received signal frequency, it is easily radiated into the air through the antenna of the receiver.
For this reason, interference is given to other adjacent receivers to hinder communication. Therefore, this system is exclusively used for communication of a frequency modulation system relatively resistant to single frequency interference.

[0004] On the other hand, wireless portable telephones, which have spread rapidly in recent years,
PSK, which is one of the amplitude transfer modulations, is used, and the single frequency interference causes an offset in the demodulated output, which causes the error rate of the received signal to deteriorate. That is, since the carrier frequency cannot be selected as the local oscillation frequency, direct frequency conversion or direct demodulation in this type of communication system is difficult. As a method of solving such a technical problem, assuming that the carrier frequency of the wireless mobile phone is fc and the offset frequency is fo, fc + fo and fc−fo are obtained,
There is a method of performing frequency conversion by providing a complementary local oscillation frequency with a frequency offset. In carrying out this method, fc + fo and fc-fo can be obtained by multiplying fc and fo by a mixer (frequency mixer). At this time, signals of fc + fo and fc-fo are output. Coexist. That is, the above processing requires each frequency signal independently, but does not meet this requirement. In the conventional apparatus, filters corresponding to the respective frequencies are inevitably used. However, the carrier frequency of the desired signal is variable, and the filter is required to have a variable characteristic, which is not practical. There was a problem.

The present invention solves such a conventional problem. In a digital modulation type communication system mainly having a plurality of channels, the power of a receiving system is reduced, the circuit is simplified, and the power consumption is reduced. It is an object of the present invention to provide a receiving circuit capable of reducing the noise. Another object of the present invention is to solve the problems in the usual manner as described above.
An object of the present invention is to provide a receiving circuit capable of obtaining c + fo and fc-fo.

More specifically, the present invention performs direct frequency conversion using a frequency in a valley between channels of a receiving system as a local frequency of a receiver, a frequency offset generated in an output signal thereof, and an adjacent channel. An object of the present invention is to provide a receiving circuit in which a signal is prevented from being mixed.

It is another object of the present invention to reconsider the configuration of each functional unit constituting the receiving circuit and to reduce or substitute the functional unit which consumes a larger amount of power.

[0008]

According to a first aspect of the present invention, there is provided a receiving input means for receiving a received signal from an antenna, and performing a frequency conversion process on the received signal from the receiving input means, A first and a second A / D converter for receiving one output signal from the quadrature demodulator and converting an analog signal into a digital signal; And a first sampling clock generator for generating a clock at least twice the frequency corresponding to the bandwidth of the received signal to the second A / D converter, and a pulse train from the first sampling clock generator. A first delay circuit for adding a first delay pulse train, and a pulse train from the first sampling clock generator and the first delay pulse train are connected to the first and second A / D converters. Means for providing a sampling pulse, third and fourth A / D converters for inputting the other output signal from the quadrature demodulator and converting an analog signal into a digital signal, and the third and fourth A / D converters. A second sampling clock generator for generating a clock having a frequency equal to or more than twice the frequency corresponding to the bandwidth of the received signal to the A / D converter; and a pulse train from the second sampling clock generator for delaying the second sampling clock generator. A second delay circuit for generating a second delay pulse train, and a pulse train from the second sampling clock generator and the second delay pulse train as sampling pulses for the third and fourth A / D converters. And a means for extracting a quadrature component of a desired reception channel signal from digital output data of the first to fourth A / D converters. It is obtained by a receiving circuit according to claim.

According to a second aspect of the present invention, in the receiving circuit according to the first aspect, the delay time of each of the delay circuits corresponds to π / 2 in relation to the frequency of the desired channel signal. It is characterized by a delay time of a phase difference.

According to a third aspect of the present invention, there is provided a receiving input means for receiving a received signal from an antenna, and a frequency conversion process for a received signal from the receiving input means to output two outputs having different phases. A quadrature demodulator to be obtained, first and second A / D converters for inputting one output signal from the quadrature demodulator and converting an analog signal into a digital signal, and the first and second A / D converters. A first sampling clock generator for generating a clock having a frequency equal to or higher than a frequency corresponding to the bandwidth of the received signal to the D converter, and a first delay pulse train for adding a first delay pulse train to the pulse train from the first sampling clock generator. 1 delay circuit, a pulse train from the first sampling clock generator, and the first delay pulse train as sampling pulses of the first and second A / D converters. Providing means, a third and fourth A / D converter for receiving the other output signal from the quadrature demodulator and converting an analog signal into a digital signal, and the third and fourth A / D converters. A second sampling clock generator for generating a clock of twice or more the frequency corresponding to the bandwidth of the received signal to the converter; and a second pulse generator for delaying a pulse train from the second sampling clock generator.
A second delay circuit for generating a delayed pulse train of
Means for providing the pulse train from the sampling clock generator and the second delay pulse train as sampling pulses for the third and fourth A / D converters, and the first to fourth A / D converters Means for extracting a quadrature component of a desired reception channel signal from the digital output data of the above-mentioned. The receiving circuit is characterized in that:

According to a fourth aspect of the present invention, there is provided a receiving input means for receiving a received signal from an antenna, a first A / D converter for inputting the received signal and performing A / D conversion, A / D converters, a sampling clock generator for generating a clock having a frequency equal to or higher than the bandwidth corresponding to the bandwidth of the received signal to these A / D converters, and a delay in a pulse train from the sampling clock generator A circuit for adding a pulse train, means for providing a pulse train from the sampling clock generator and a delay pulse train as sampling pulses of the A / D converter, and a desired receiving channel from digital output data of the A / D converter Means for extracting a signal.

According to a fifth aspect of the present invention, in the receiving circuit of the fourth aspect, a delay time in the circuit for adding the delay pulse train corresponds to π / 2 in relation to a frequency of a desired channel signal. Characterized in that the phase difference time is set as follows.

According to a sixth aspect of the present invention, in the receiving circuit of the fourth aspect, means for generating a plurality of the delay pulses is provided, and the delay time of the delay pulse is set to
In particular, the delay time is set to a delay time other than the phase difference corresponding to π in relation to the frequency of the desired channel signal.

According to a seventh aspect of the present invention, there is provided a reception input means for receiving a reception signal from an antenna, a single A / D converter for inputting the reception signal and performing A / D conversion, A sampling clock generator for generating a clock having a frequency equal to or higher than a bandwidth corresponding to the bandwidth of a received signal to an A / D converter, a circuit for adding a delay pulse train to a pulse train from the sampling clock generator, and the sampling clock generator A circuit for adding a delay pulse train to the pulse train from the A / D converter, means for providing the pulse train and the delay pulse train from the sampling clock generator as sampling pulses of the A / D converter, and digital output data of the A / D converter And a means for extracting a desired receiving channel signal from the receiving circuit.

According to an eighth aspect of the present invention, a reception input means for receiving a reception signal from an antenna, and a frequency conversion process for a reception signal from the reception input means, to output two outputs having different phases. A quadrature demodulator to be obtained, a first A / D converter that receives one output signal from the quadrature demodulator and converts an analog signal into a digital signal, and receives another output signal from the quadrature demodulator. A second A / D converter for converting an analog signal into a digital signal, and a sampling circuit for supplying the first and second A / D converters with a clock having a frequency equal to or higher than the bandwidth corresponding to the bandwidth of the received signal. A clock generator; a delay circuit for delaying a pulse train from the sampling clock generator to generate a delayed pulse train; a pulse train from the sampling clock generator and the delay circuit; Wherein a scan sequence first and second A /
Means for providing both as sampling pulses of the D converter, and means for extracting a quadrature component of a desired reception channel signal from digital output data of the first and second A / D converters. This is a receiver circuit.

According to a ninth aspect of the present invention, in the receiving circuit according to the eighth aspect, the delay time of the delay circuit is set to a phase difference corresponding to π / 2 in relation to the frequency of the desired channel signal. , Which is characterized by a delay time of

According to a tenth aspect of the present invention, a reception input means for receiving a reception signal from an antenna, and performing a frequency conversion process on a reception signal from the reception input means,
A quadrature demodulator that obtains two outputs having different phases, a first A / D converter that receives one output signal from the quadrature demodulator and converts an analog signal into a digital signal, A second A / D converter for inputting another output signal to convert an analog signal into a digital signal, and a frequency corresponding to a bandwidth of a received signal to the first and second A / D converters. A sampling clock generator for supplying the above clock, a delay circuit for delaying a pulse train from the sampling clock generator to generate a delay pulse train, and a pulse train from the sampling clock generator and the delay pulse train for the first clock. And the second A
Means for providing both as sampling pulses of a / D converter and means for extracting a quadrature component of a desired reception channel signal from digital output data of the first and second A / D converters, wherein the delay circuit Is a delay time other than the phase difference corresponding to π in relation to the frequency of the desired channel signal.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described below, but before that, the theoretical basis of the present invention will be described. First, binary PSK, that is, BPSK, which is frequently used in the digital modulation method, will be described.

The BPSK signal SB at the base frequency, that is, at the baseband, can be expressed as follows. SB = Acos (θk) where A is amplitude, θk is a phase representing BPSK information, θk = 0, π The modulation output SC obtained by modulating this baseband signal at the carrier angular frequency ωC can be expressed as follows.

(Equation 1) This modulated signal is received, and the local frequency for frequency conversion ωC
, The frequency conversion output SR is expressed as follows.

[0020]

(Equation 2) When the high-frequency component 2ωC is removed by passing this frequency conversion output SR through a low-pass filter, the output SRF
Is as follows, and a binary PSK, that is, a BPSK signal can be demodulated.

[0021]

(Equation 3) However, since the local oscillation frequency is set to the same ωC as the carrier frequency in the frequency conversion for reception, the local oscillation frequency signal is radiated from the receiver into the air, and interferes with other nearby receivers.

According to the present invention, in order to solve such a problem, the local oscillation frequency is set as follows. FIG. 20 shows a method for setting the local oscillation frequency according to the present invention. FIG.
At 0, A indicates the band of the desired channel and the carrier frequency is ωC. B indicates the band of the upper adjacent channel, and the carrier frequency is ωCU. C indicates the band of the lower adjacent channel, and the carrier frequency is ωCL. The interval between carriers of each channel is the base frequency ωb of BPSK.
About 4 times.

The band of each channel is ±
2ωb. Therefore, a position apart from each carrier frequency by the amount of the base frequency 2ωb is a valley when viewed from any channel, and even if an interference wave of the line spectrum exists at this position, the interference is small for any channel. That is, the present invention pays attention to this point, and sets the local oscillation frequency of the receiver at an intermediate value between adjacent channel carrier frequencies as a main method for solving the problem.

Next, when the local oscillation frequency of the receiver is set as described above, another point of the present invention, that is, how to construct a subsequent circuit so that demodulation can be obtained in the same manner as before, is described. The description will be given again by using mathematical expressions.

As described above, the local oscillation frequency for receiving the modulated signal and performing frequency conversion of the receiver is ωC + ωO
, The frequency conversion output SR is as follows.

[0026]

(Equation 4) When this frequency conversion output SR is passed through a low-pass filter to remove the high-frequency component 2ωC, the output SRF becomes

[0027]

(Equation 5) And a binary value P with an offset by the frequency ωO
An SK or BPSK signal is generated.

Next, the local oscillation frequency is set to ωC−ωO lower by ωO than the transmission frequency of the desired channel. The frequency conversion output SL in this case is as follows.

[0029]

(Equation 6) When this frequency conversion output SL is passed through a low-pass filter to remove the high-frequency component 2ωC, the output SLF becomes

[0030]

(Equation 7) And a BPSK signal having the same phase as the SRF is generated.

By the way, since the local oscillation frequency of reception is equidistant from the adjacent channel, a component of the adjacent channel is generated and mixed in the signal to be demodulated. The signal of the upper adjacent channel is represented by ωCh = ωC where the carrier frequency is represented by ωCh.
Since it is + 2ωO 2, the above-mentioned frequency conversion on the receiving side is as follows.

First, the local oscillation frequency for receiving the modulated signal and performing frequency conversion of the receiver is set to ωC as described above.
When set to + ωO, the frequency conversion output SRh is as follows.

[0033]

(Equation 8) When the high frequency component 2ωC is removed by passing the frequency conversion output SRh through a low-pass filter, the output SRFh
Is

[0034]

(Equation 9) BPSK existing in the same band as the desired channel
A signal is generated.

On the other hand, when the carrier frequency of the signal of the lower adjacent channel is represented by ωCl, ωCl = ωC−2ωO, and the above-mentioned frequency conversion on the receiving side is as follows.

First, when the local oscillation frequency of the receiver is set to ωC + ωO as described above, the frequency conversion output SR
l is as follows.

[0037]

(Equation 10) When the high-frequency component 2ωC is removed by passing the frequency conversion output SR1 through a low-pass filter, the output SRF1
Is

[0038]

[Equation 11] And B at a frequency 3ωO away from the desired channel
A PSK signal is generated.

Next, the state of frequency conversion of an adjacent channel when the local oscillation number is ωC−ωO will be verified. The signal of the upper adjacent channel has a carrier frequency of ωC
When expressed by h, ωCh = ωC + 2ωO, so that the frequency conversion when the local oscillation frequency is ωC−ωO is as follows.

First, the local oscillation frequency for receiving the modulated signal and performing frequency conversion of the receiver is set to ωC as described above.
When -ωO is set, the frequency conversion output SLh is as follows.

[0041]

(Equation 12) When the high-frequency component 2ωC is removed by passing the frequency conversion output SLh through a low-pass filter, the output SLF1
Is as follows:

[0042]

(Equation 13)

On the other hand, when the carrier frequency of the signal of the lower adjacent channel is represented by ωCl, ωCl = ωC−2ωO, so the above-mentioned frequency conversion on the receiving side is as follows.

First, when the local oscillation frequency of the receiver is set to ωC−ωO as described above, the frequency conversion output SLl
Is as follows.

[0045]

[Equation 14] When the high-frequency component 2ωC is removed by passing the frequency conversion output SL1 through a low-pass filter, the output SLF1
Is

[0046]

(Equation 15) And a BPSK signal is generated at the same frequency as the desired channel.

To summarize from the above, there are three types of outputs when the local frequency is shifted upward by ωO.

[0048]

(Equation 16) The following three types of outputs are obtained when the local frequency is shifted downward by ωO 2.

[0049]

[Equation 17]

The component common to both groups is only the desired channel. Therefore, if both are supplied to the adder as two inputs, only the desired channel can be extracted from the output. Further, the output is frequency-offset by ω0, which can be removed by a simple frequency offset circuit.

In the present invention, such a principle is realized by the following embodiments.

(Eighth Embodiment 1) FIG. 1 shows a configuration of a first embodiment of the present invention. In FIG. 1, 1 is an antenna receiving a received signal, 2 and 3 are first and second frequency conversion circuits receiving the received signal as input signals, and 4 is a radio having upper and lower channels adjacent to a radio carrier frequency of the received signal. In addition to generating an intermediate frequency with the carrier frequency, the upper frequency of the upper and lower two frequencies is supplied as a conversion frequency input of the first frequency conversion circuit 2 and the lower frequency is supplied to the second frequency conversion circuit 3. A local frequency signal generation circuit for supplying as a conversion frequency input, a common wave extraction circuit for extracting a component which is present in both the output of the first frequency conversion circuit 2 and the output of the second frequency conversion circuit 3 ,
Reference numeral 6 denotes a frequency offset circuit that removes a frequency offset remaining in the output of the common wave extraction circuit 5, reference numeral 7 denotes an offset frequency generation circuit that performs minute frequency conversion and supplies an offset amount to the frequency offset circuit 6, and reference numeral 8 denotes a frequency offset. This filter removes unnecessary frequency components remaining in the output of the circuit 6.

Next, the operation of the first embodiment will be described. According to the above formula, the received signal obtained from the antenna 1 is supplied to the first frequency conversion circuit 2 and the second frequency conversion circuit 3 and the local frequency signal generation circuit 4
, The upper and lower frequencies comparable to the median between the two channels are supplied separately to the first frequency conversion circuit 2 and the second frequency conversion circuit 3 so that the desired channel and the upper and lower channels Two output signals are generated for each of the three signals. According to the mathematical expression expansion, the only signal component that exists in common in the first frequency conversion circuit 2 and the second frequency conversion circuit 3 is the signal of the desired channel, and is supplied to the common wave extraction circuit 5 that extracts the balanced component. By doing so, an equilibrium component mainly including the desired wave is obtained. Since a frequency offset of ωO remains in the output of the common wave extraction circuit 5, a minute frequency conversion is performed in the offset frequency generation circuit 7, and the offset amount is removed in the frequency offset circuit 6. Further, unnecessary frequency components generated in this process are removed by the filter 8, and then supplied to the baseband signal processing unit as a baseband signal.

(Embodiment 2) FIG. 2 shows a configuration of a second embodiment of the present invention. In FIG. 2, reference numeral 1 denotes an antenna receiving a received signal, 2 and 3 denote first and second frequency conversion circuits which receive the received signal, and 4 denotes a radio having upper and lower channels adjacent to a radio carrier frequency of the received signal. In addition to generating an intermediate frequency with the carrier frequency, the upper frequency of the upper and lower two frequencies is supplied as a conversion frequency input of the first frequency conversion circuit 2 and the lower frequency is supplied to the second frequency conversion circuit 3. 6A is a first frequency offset circuit for removing the frequency offset contained in the output of the first frequency conversion circuit 2, and 6B is a second frequency offset circuit for removing the frequency offset contained in the output of the first frequency conversion circuit 2.
A frequency offset circuit for removing a frequency offset included in the output of the frequency conversion circuit 3; and an offset frequency generation circuit 7A for performing a minute frequency conversion and supplying an offset amount to each of the frequency offset circuits 6A and 6B. , 5A is a common wave extraction circuit for extracting a component that is present in both the outputs of the first frequency offset circuit 6A and the second frequency offset circuit 6B, and 8A is an unnecessary frequency remaining in the output of the common wave extraction circuit 5A. This is a filter that removes components.

Next, the operation of the second embodiment will be described. In the present embodiment, the process of extracting a common wave and the process of performing frequency offset in the first embodiment are replaced. That is, by preceding the process of performing the frequency offset, the signal of the desired channel becomes a baseband signal as it is, and a more stable extraction operation can be expected.

Hereinafter, the validity in the case where the frequency offset precedes will be described. The frequency offset for a signal group whose local frequency is shifted upward by ωO 2 is ωO
Is performed, and the output is of the following three types.

[0057]

(Equation 18)

The frequency offset for the signal group in which the local frequency is shifted downward by ωO will be shifted to remove ωO, and the following three types of outputs will be obtained.

[0059]

[Equation 19] Again, the only component common to both groups is the desired channel. Therefore, if both are supplied as two inputs to the adder, a BPSK signal of only the desired channel can be extracted from the output.

(Embodiment 3) FIG. 3 shows a configuration of a third embodiment of the present invention. In FIG. 3, reference numeral 1 denotes an antenna for receiving a received signal, 2 and 3 denote first and second frequency conversion circuits which receive the received signal, and 4 denotes a radio having upper and lower channels adjacent to a radio carrier frequency of the received signal. In addition to generating an intermediate frequency with the carrier frequency, the upper frequency of the upper and lower two frequencies is supplied as a conversion frequency input of the first frequency conversion circuit 2 and the lower frequency is supplied to the second frequency conversion circuit 3. 9A is a first band-pass filter for shaping the output of the first frequency conversion circuit 2, and 10A is a digital signal for outputting the output of the first band-pass filter 9A. A first A / D converter for converting to 9
B is a second waveform shaping output of the second frequency conversion circuit 3.
Of the second band-pass filter 9B convert the output of the second band-pass filter 9B into a digital signal.
The D converter 5B includes a first A / D converter 10A and a second A / D converter
6C is a common wave extraction circuit for extracting components that are present in both of the outputs of the A / D converter 10B.
A frequency offset circuit for removing the frequency offset remaining in the output of B, 7B is an offset frequency generating circuit that performs a minute frequency conversion and supplies an offset amount to the frequency offset circuit 6C, and 8B remains in the output of the frequency offset circuit 6C. This is a filter for removing unnecessary frequency components.

Next, the operation of the third embodiment will be described. In this embodiment, the outputs of the two frequency conversion circuits 2 and 3 in the first embodiment are A /
Quantization is performed by the D converters 10A and 10B, and operations equivalent to those of the first embodiment, that is, common wave extraction, frequency offset, and filtering are performed using digital operations. Common wave extraction and filtering can be performed using digital filter technology, and frequency offset can be performed using digital quadrature modulation.

Hereinafter, the principle of the present embodiment will be described for quadrature PSK, ie, QPSK or quaternary QAM, which is frequently used in digital modulation.

The base frequency, that is, the QPSK signal SB in the base band can be expressed as follows.

[0064]

(Equation 20) The modulation output SC obtained by modulating the baseband signal at the carrier angular frequency ωC can be expressed as follows.

[0065]

(Equation 21) Here, the real axis component is generally called an I-axis signal, and the imaginary axis component is called a Q-axis signal. When this modulated signal is received and subjected to quadrature demodulation at the local frequency ωC for frequency conversion, the quadrature demodulated I-axis output SI
R is expressed as follows.

[0066]

(Equation 22) When the quadrature demodulated I-axis output SIR is passed through a low-pass filter to remove the high-frequency component 2ωC, the output SIRF
Is

[0067]

(Equation 23) Thus, the quadrature PSK, that is, the I-axis signal of the QPSK signal can be demodulated.

However, similarly to the above description, in this case also, the local oscillation frequency in the quadrature demodulation is the same as that of the carrier frequency.
Because of C 1, the local oscillation frequency signal is radiated from the receiver into the air, and interferes with other nearby receivers.
Therefore, when the local oscillation frequency of the receiver is set to ωC + ωO as described above, the I-axis output SI
R is as follows.

[0069]

(Equation 24) When the quadrature demodulated I-axis output SIR is passed through a low-pass filter to remove the high-frequency component 2ωC, the output SIRF
Is

[0070]

(Equation 25) And an I-axis output of a quadrature PSK signal, that is, a QPSK signal is obtained.

Next, the local oscillation frequency is set to ωC−ωO lower by ωO than the carrier frequency of the desired channel. The frequency conversion output SIL in this case is as follows.

[0072]

(Equation 26) When the quadrature demodulated I-axis output SIL is passed through a low-pass filter to remove the high-frequency component 2ωC, the output SILF
Is

[0073]

[Equation 27] Becomes When the quadrature demodulated I-axis output SIRh is passed through a low-pass filter to remove the high-frequency component 2ωC, the output S
Obtain IRFh.

The demodulated signal of an adjacent channel which is equidistant from the local oscillation frequency of reception is as follows. The signal of the upper adjacent channel has a carrier frequency of ωCh
Since ωCh = ωC + 2ωO, when the local oscillation frequency is ωC + ωO, the quadrature demodulation I-axis output S
IRh is as follows.

[0075]

[Equation 28] When the quadrature demodulated I-axis output SIRh is passed through a low-pass filter to remove the high-frequency component 2ωC, the output SIR
Fh

[0076]

(Equation 29) And the orthogonal PS existing in the same band as the desired channel.
A K or QPSK signal is generated.

On the other hand, the signal of the lower adjacent channel is represented by ωCl = ωC−2ωO when the carrier frequency is represented by ωCl. Therefore, when the local oscillation frequency is set to ωC + ωO as described above, the reception side quadrature demodulation I The shaft output SIRl is as follows.

[0078]

[Equation 30] When this quadrature demodulated I-axis output SIR1 is passed through a low-pass filter to remove the high-frequency component 2ωC, the output SIR
Fl is

[0079]

(Equation 31) And a quadrature PSK, that is, a QPSK signal is generated at the same frequency as the desired channel.

Next, when the local oscillation frequency of the receiver is ωC + ωO as described above and its phase is delayed by π / 2, the quadrature demodulated Q-axis output SQR is obtained as follows.

[0081]

(Equation 32) When the quadrature demodulated Q-axis output SQR is passed through a low-pass filter to remove the high-frequency component 2ωC, the output SQRF
Is

[0082]

[Equation 33] And the Q-axis output of a quadrature PSK, that is, a QPSK signal is obtained.

Next, consider the case where the phase when the local oscillation frequency is set to ωC−ωO lower by ωO than the carrier frequency of the desired channel is delayed by π / 2. The quadrature demodulated Q-axis output SQL in this case is as follows.

[0084]

(Equation 34) When the quadrature demodulated Q-axis output SQL is passed through a low-pass filter to remove the high-frequency component 2ωC, the output SQLF
Is

[0085]

(Equation 35) And the orthogonal PSK signal Q having a different polarity from the SQRF
Shaft output is obtained.

Next, the quadrature demodulation Q-axis output is analyzed for adjacent channels. When the carrier frequency of the signal of the upper adjacent channel is represented by ωCh, ωCh = ωC + 2ωO. Therefore, when the local oscillation frequency is set to ωC + ωO, the quadrature demodulated Q-axis output SQRh of the upper channel is as follows. become.

[0087]

[Equation 36] When the high-frequency component 2ωC is removed by passing this frequency conversion output SQRh through a low-pass filter, the output SQL
Fh

[0088]

(37) And the orthogonal PS existing in the same band as the desired channel.
K or QPSK signal Q axis output is generated.

Similarly, the operation is performed on the signal of the lower adjacent channel. The carrier frequency ωCl is ωCl = ωC−2ω
Since it is O 2, the quadrature demodulated Q-axis output SQRl at the pole oscillation frequency ωC + ωO is as follows.

[0090]

(38) When the quadrature demodulated Q-axis output SQRl is passed through a low-pass filter to remove the high-frequency component 2ωC, the output SQR
Fl is

[0091]

[Equation 39] Thus, a quadrature PSK, that is, a QPSK signal Q-axis output is generated at a frequency 3 ωO away from the desired channel.

Next, when the local oscillation frequency is ωC−ωO, the quadrature demodulated Q-axis output SQR of the adjacent channel is as follows. Carrier frequency ωC of the signal of the upper adjacent channel
Since h is ωCh = ωC + 2ωO, the local oscillation frequency is quadrature demodulated Q-axis output SQRh at ωC−ωO.
Is as follows.

[0093]

(Equation 40) When the quadrature demodulated Q-axis output SQRh is passed through a low-pass filter to remove the high-frequency component 2ωC, the output SQRh
Fh

[0094]

[Equation 41] Thus, a quadrature PSK, that is, a QPSK signal Q-axis output existing in a band 3ω0 away from the desired channel is generated.

Similarly, the operation is performed on the signal of the lower adjacent channel. The carrier frequency ωCl is ωCl = ωC−2ω
O 2. The local oscillation frequency of the receiver is ωC−ωO, and the quadrature demodulated Q-axis output SQR1 is as follows.

[0096]

(Equation 42) When the quadrature demodulated Q-axis output SQRl is passed through a low-pass filter to remove the high-frequency component 2ωC, the output SQR
Fl is

[0097]

[Equation 43] Thus, an orthogonal PSK, that is, a QPSK signal Q-axis output is generated at the same frequency as the desired channel.

The above can be summarized as follows.

[Equation 44]

[0099]

[Equation 45]

From the above equation, as described above, it can be seen that the desired channel is commonly included in the outputs of the two orthogonal demodulation circuits on the I-axis side. It can also be seen that on the Q-axis side, the desired channels are commonly included in the outputs of the two orthogonal demodulation circuits in opposite phases. The third embodiment of the present invention is realized based on this principle.

(Embodiment 4) FIG. 4 shows a configuration of a fourth embodiment of the present invention. In FIG. 4, 1 is an antenna receiving a received signal, 2 and 3 are first and second frequency conversion circuits receiving the received signal as input signals, and 4 is a radio having upper and lower channels adjacent to a radio carrier frequency of the received signal. In addition to generating an intermediate frequency with the carrier frequency, the upper frequency of the upper and lower two frequencies is supplied as a conversion frequency input of the first frequency conversion circuit 2 and the lower frequency is supplied to the second frequency conversion circuit 3. 9A is a first band-pass filter for shaping the output of the first frequency conversion circuit 2, and 10A is a digital signal for outputting the output of the first band-pass filter 9A. A first A / D converter for converting to 9
B is a second waveform shaping output of the second frequency conversion circuit 3.
Of the second band-pass filter 9B convert the output of the second band-pass filter 9B into a digital signal.
D converter, 6D is a first frequency offset circuit for removing the frequency offset included in the output of the first A / D converter 10A, and 6E is included in the output of the second A / D converter 10B. A second frequency offset circuit for removing a frequency offset that has been removed, 7C is an offset frequency generation circuit that performs a minute frequency conversion and supplies an offset amount to each of the frequency offset circuits 6D and 6E, and 5C is a first frequency offset circuit. 6D and second frequency offset circuit 6
A common wave extraction circuit 8C extracts a component commonly present in both outputs of E. A filter 8C removes unnecessary frequency components remaining in the output of the common wave extraction circuit 5C.

Next, the operation of the fourth embodiment will be described. This embodiment replaces the process of performing common wave extraction and the process of performing frequency offset in the third embodiment. That is, by preceding the process of performing the frequency offset, the signal of the desired channel becomes the base signal as it is, and a more stable extraction operation can be expected. Further, by digitizing, the quadrature demodulation function becomes highly accurate, suitable for integration, and leads to reduction in power consumption.

(Embodiment 5) FIG. 5 shows a configuration of a fifth embodiment of the present invention. In FIG. 5, reference numeral 1 denotes an antenna receiving a received signal, 11 and 12 denote first and second quadrature demodulation circuits which receive the received signal, and 4A denotes a radio having upper and lower channels adjacent to a radio carrier frequency of the received signal. A frequency intermediate to the carrier frequency is generated, and the upper frequency of the two upper and lower frequencies is set to the first frequency.
A local frequency signal generating circuit that supplies the lower frequency as a conversion frequency input of the second quadrature demodulation circuit 3 and a local frequency signal generation circuit 5D that supplies the lower frequency as a conversion frequency input of the second quadrature demodulation circuit 11. Output and I of the second quadrature demodulation circuit 12
A first common wave extraction circuit 5E for extracting a component which is present in both of the outputs is provided to both the Q output of the first quadrature demodulation circuit 11 and the polarity inverted output of the Q output of the second quadrature demodulation circuit 12. A second common wave extraction circuit for extracting a component that is present in common, 6F is a first frequency offset circuit for removing the frequency offset remaining in the I-side output extracted by the first common wave extraction circuit 5D, 6G is A second frequency offset circuit 7D that removes a frequency offset remaining in the Q-side output extracted by the second common wave extraction circuit 5E performs a minute frequency conversion, and outputs an offset amount to each of the frequency offset circuits 6F and 6G. Offset frequency generation circuit to supply, 8D
Is a first filter for removing unnecessary frequency components remaining in the output of the first frequency offset circuit 6F, and 8E is a second filter for removing unnecessary frequency components remaining in the output of the second frequency offset circuit 6G. .

Next, the operation of the fifth embodiment will be described. In the present embodiment, the present invention is embodied with respect to quaternary PSK or QPSK in digital modulation. According to the above-described mathematical expression, the antenna 1
Is supplied to a first quadrature demodulation circuit 11 and a second quadrature demodulation circuit 12, and the local frequency signal generation circuit 4A outputs two different frequencies, ie, upper and lower frequencies equivalent to the median value between channels. First quadrature demodulation circuit 1
Separate feeds to the first and second quadrature demodulation circuits 12 produce four output signals for each of the desired channel and the three signals of the upper and lower channels. According to the mathematical expression expansion, the first quadrature demodulation circuit 11
The signal components that are commonly present in the second quadrature demodulation circuit 12 are only the signals of the desired channel, and it is possible to extract the balanced component on the I-axis side and the differential component on the Q-axis side. Therefore, the balanced component on the I-axis side is supplied to the common wave extraction circuit 5D, and the differential component on the Q-axis side is supplied to the common wave extraction circuit 5E.
, The I-axis and Q-axis signals of the desired channel are obtained. The output to the common wave extraction circuits 5D and 5E is ω
Since a frequency offset of O 2 remains, a minute frequency conversion is performed in the offset frequency generation circuit 7D, and the offset amount is removed in the frequency offset circuits 6F and 6G. Further, unnecessary frequency components generated in this process are removed by filters 8D and 8E, and then supplied to a baseband signal processing unit as baseband signals.

(Embodiment 6) FIG. 6 shows a configuration of a sixth embodiment of the present invention. In FIG. 6, reference numeral 1 denotes an antenna for receiving a received signal, 11 and 12 denote first and second quadrature demodulation circuits which receive the received signal, and 4A denotes a radio having upper and lower channels adjacent to a radio carrier frequency of the received signal. A frequency intermediate to the carrier frequency is generated, and the upper frequency of the two upper and lower frequencies is set to the first frequency.
As a conversion frequency input of the orthogonal demodulation circuit 11 of
Local frequency signal generators 6H and 6I for supplying the lower frequency as a frequency input for conversion of the second quadrature demodulation circuit 12 are frequencies commonly included in the I and Q outputs of the quadrature demodulation circuits 11 and 12, respectively. A first and second frequency offset circuit for removing the offset, an offset frequency generating circuit for performing a minute frequency conversion and supplying an offset amount to each of the frequency offset circuits 6H and 6I;
5F is the I output of the first frequency offset circuit 6H and the second
A first common wave extraction circuit for extracting a component that is present in both of the I output of the frequency offset circuit 6I and a Q output of the first frequency offset circuit 6H and a Q output of the second frequency offset circuit 6I A second common wave extracting circuit for extracting a component that is present in both of the polarity inverted outputs of
F and 8G are first and second filters for removing unnecessary frequency components remaining in the outputs of the common wave extraction circuits 5F and 5G.

Next, the operation of the sixth embodiment will be described. This embodiment replaces the process of performing common wave extraction and the process of performing frequency offset in the fifth embodiment. That is, by preceding the process of performing the frequency offset, the signal of the desired channel becomes the base signal as it is, and a more stable extraction operation can be expected.

(Embodiment 7) FIG. 7 shows a configuration of a seventh embodiment of the present invention. In FIG. 7, reference numeral 1 denotes an antenna receiving a received signal, 11 and 12 denote first and second quadrature demodulation circuits which receive the received signal, and 4A denotes a radio having upper and lower channels adjacent to a radio carrier frequency of the received signal. A frequency intermediate to the carrier frequency is generated, and the upper frequency of the two upper and lower frequencies is set to the first frequency.
As a conversion frequency input of the orthogonal demodulation circuit 11 of
Local frequency signal generators 9C and 9D for supplying the lower frequency as a conversion frequency input of the second quadrature demodulation circuit 12 are first and second waveform shaping I and Q outputs of the first quadrature demodulation circuit 11, respectively. The second band-pass filters, 10C and 10D, are first and second A / D converters for converting the outputs of the first and second band-pass filters 9C, 9D into digital signals, and 9E and 9F are the second.
Third and fourth bandpass filters 10E and 10F for shaping the I output and Q output of the quadrature demodulation circuit 12 of FIG.
The third and fourth A / D converters 5H for converting the outputs of E and 9F into digital signals extract components commonly present in the I outputs of the first and third A / D converters 10C and 10E. The first common wave extraction circuit 5I performs the second A / D
Q output of converter 10D and Q of fourth A / D converter 10E
A second common wave extraction circuit 6J for extracting a component which is present in both of the inverted polarity output of the output, and a second common wave extraction circuit 6J for removing a frequency offset remaining in the I-side output extracted by the first common wave extraction circuit 5H. 1 frequency offset circuit, 6K is the second
The second frequency offset circuit 7F for removing the frequency offset remaining in the Q-side output extracted by the common wave extraction circuit 5I, performs a minute frequency conversion, and supplies the offset amount to each of the frequency offset circuits 6J and 6K. An offset frequency generating circuit, 8H is a first filter that removes unnecessary frequency components remaining in the output of the first frequency offset circuit 6J, and 8I removes unnecessary frequency components remaining in the output of the second frequency offset circuit 6K. This is a second filter.

Next, the operation of the seventh embodiment will be described. In this embodiment, the outputs of the two orthogonal demodulation circuits 11 and 12 in the fifth embodiment are quantized by A / D converters 10C to 10F, and are equivalent to the fifth embodiment by using digital operation. , Ie, common wave extraction, frequency offset and filtering. Common wave extraction and filtering can be performed using digital filter technology, and frequency offset can be performed using digital quadrature modulation.

(Eighth Embodiment) FIG. 8 shows a configuration of an eighth embodiment of the present invention. In FIG. 8, 1 is an antenna receiving a received signal, 11 and 12 are first and second quadrature demodulation circuits receiving the received signal, and 4A is a radio having upper and lower channels adjacent to a radio carrier frequency of the received signal. A frequency intermediate to the carrier frequency is generated, and the upper frequency of the two upper and lower frequencies is set to the first frequency.
As a conversion frequency input of the orthogonal demodulation circuit 11 of
Local frequency signal generators 9C and 9D for supplying the lower frequency as a conversion frequency input of the second quadrature demodulation circuit 12 are first and second waveform shaping I and Q outputs of the first quadrature demodulation circuit 11, respectively. The second band-pass filters, 10C and 10D, are first and second A / D converters for converting the outputs of the first and second band-pass filters 9C, 9D into digital signals, and 9E and 9F are the second.
Third and fourth bandpass filters 10E and 10F for shaping the I output and Q output of the quadrature demodulation circuit 12 of FIG.
The third and fourth A / D converters 6L for converting the outputs of E and 9F into digital signals, and 6L each of the A / D converters 10C to 10C
A frequency offset circuit for removing the frequency offset remaining in the I output and the Q output of 0F. An offset frequency generation circuit 7G performs a minute frequency conversion and supplies an offset amount to each frequency offset circuit 6L.
Is a first common wave extraction circuit for extracting a component that is commonly present in the I output of the frequency offset circuit 6L, and 5K is a component that is commonly present in both the Q output and the polarity-inverted output of the Q output of the frequency offset circuit 6L. Is a first filter for removing unnecessary frequency components remaining in the I output extracted by the first common wave extraction circuit 5J, and 8K is a second common wave extraction circuit 5K. Is a second filter that removes unnecessary frequency components remaining in the Q output of the second filter.

Next, the operation of the eighth embodiment will be described. This embodiment replaces the process of performing common wave extraction and the process of performing frequency offset in the seventh embodiment. That is, by preceding the process of performing the frequency offset, the signal of the desired channel becomes the base signal as it is, and a more stable extraction operation can be expected. Further, by digitizing, the quadrature demodulation function becomes highly accurate, suitable for integration, and leads to reduction in power consumption.

(Embodiment 9) FIG. 9 shows a configuration of a ninth embodiment of the present invention. This embodiment is different from the common wave extraction circuit 5 in the third embodiment shown in FIG.
Instead of B, a correlator 13 for calculating a cross-correlation is used.

Therefore, according to the present embodiment, since the common wave is extracted by the digital filter technique, the use of the correlator 13 allows the polarity of the correlation coefficient to be changed even if the components included in common have different polarities. The advantage is that the amplitude can be secured only by reversing.

This embodiment can be similarly applied to the fourth, seventh and eighth embodiments.

(Embodiment 10) FIG. 10 shows a first embodiment of the present invention.
0 shows the configuration of the embodiment. In the present embodiment, only the first frequency conversion circuit 2 is used as the frequency conversion circuit for inputting the reception signal in the first embodiment shown in FIG. 1, and after the frequency conversion by the first frequency conversion circuit 2, The second frequency conversion circuit 15 supplied with a frequency corresponding to the inter-channel frequency 2ωO from the local frequency signal generation circuit 4B obtains a frequency conversion output on the side on which the first frequency conversion circuit 2 has not performed frequency conversion. , Two frequency conversion outputs necessary for extracting a desired channel by the common wave extraction circuit 5L are ensured.

Therefore, according to the present embodiment, by using both the outputs of the first frequency conversion circuit 2 and the second frequency conversion circuit 15, the first and second frequency conversion circuits in the first embodiment can be used. 2 when the frequency conversion circuits 2 and 3 of FIG.
Since one output matches one output, only one set of a high-frequency circuit for the carrier frequency can be used, and not only the space required for the circuit but also the power consumption can be reduced.

This embodiment can be similarly applied to the second embodiment.

(Embodiment 11) FIG. 11 shows a first embodiment of the present invention.
1 shows a configuration of an embodiment. In the present embodiment, only the first frequency conversion circuit 2 is used as the frequency conversion circuit for inputting the received signal in the third embodiment shown in FIG. A digital frequency to which only a band-pass filter 9C and an A / D converter 10C receiving an output is supplied, and a frequency corresponding to the inter-channel frequency 2ωO 2 is supplied from the digital frequency generation circuit 17 after A / D conversion by the A / D converter 10C. By performing digital frequency conversion by the conversion circuit 16, the first frequency conversion circuit 2 obtains a frequency conversion output on the side not subjected to the frequency conversion, and obtains two frequencies necessary for the extraction of a desired channel by the common wave extraction circuit 5M. The conversion digital output is ensured.

Therefore, according to the present embodiment, by using both the output obtained by A / D conversion of the first frequency conversion circuit 2 by the A / D converter 10C and the output of the digital frequency conversion circuit 16, the third frequency conversion circuit 2 is provided. 2 in the case where the first and second frequency conversion circuits 2 and 3 in the embodiment are used.
Since one output matches one output, only one set of a high-frequency circuit for the carrier frequency can be used, and not only the space required for the circuit but also the power consumption can be reduced.

This embodiment can be similarly applied to the fourth embodiment.

(Embodiment 12) FIG. 12 shows a first embodiment of the present invention.
9 shows a configuration of a second embodiment. In the present embodiment, the orthogonal demodulation circuit for inputting the received signal in the fifth embodiment shown in FIG. 5 is only one orthogonal demodulation circuit 11, and two outputs of the orthogonal demodulation circuit 11 are used as local frequency signals. By performing frequency conversion by the frequency conversion circuit 15A supplied with a frequency corresponding to the inter-channel frequency 2ωO 2 from the generation circuit 4B, a frequency conversion output on the side where quadrature demodulation has not been performed is obtained, and each common wave extraction circuit 5N and This is to secure two orthogonal demodulation outputs necessary for extracting a desired channel by 5P.

Therefore, according to the present embodiment, by using the outputs of quadrature demodulation circuit 11 and frequency conversion circuit 15A together, the first and second quadrature demodulation circuits 11 and 11 in the fifth embodiment can be used. In this case, since two quadrature demodulated outputs coincide with each other, only one set of a high-frequency circuit for the carrier frequency is required, so that not only the space required for the circuit but also the power consumption can be reduced. it can.

This embodiment can be similarly applied to the sixth embodiment.

(Embodiment 13) FIG. 13 shows a first embodiment of the present invention.
13 shows a configuration of a third embodiment. In this embodiment, the quadrature demodulation circuit for receiving the received signal in the seventh embodiment shown in FIG. 7 is only one quadrature demodulation circuit 11 and the quantizing means is one band pass filter 9.
D, 9E and A / D converters 10D, 10E only,
After A / D conversion by the A / D converters 10D and 10E, the digital frequency generation circuit 17A outputs the inter-channel frequency 2
By performing digital frequency conversion by the digital frequency conversion circuit 16A supplied with a frequency corresponding to ωO, the quadrature demodulation circuit 11 obtains a frequency conversion output on which the quadrature demodulation has not been performed.
Q and 2R ensure two orthogonal demodulation outputs necessary for extracting a desired channel.

Therefore, according to the present embodiment, the output of quadrature demodulation circuit 11 is subjected to A / D conversion by A / D converters 10D and 10E and digital frequency conversion circuit 16A.
Are used together with the two outputs when the first and second quadrature demodulation circuits 11 and 12 in the seventh embodiment are used. Only a set can be used, and not only the space required for the circuit but also the power consumption can be reduced.

This embodiment can be similarly applied to the eighth embodiment.

(Embodiment 14) FIG. 14 shows a configuration of a fourteenth embodiment of the present invention. This embodiment relates to an improvement of the common wave extraction circuit in the first embodiment shown in FIG. In FIG. 14, 1
Is an antenna, 2 is a first frequency conversion circuit, 3 is a second frequency conversion circuit, 4 is a local frequency signal generation circuit, 5 is a common wave extraction circuit, and 8 is a filter, which is the same as in the first embodiment. Configuration.

Reference numeral 20 denotes a specific configuration of the reception input unit.
21 is an input line receiving the output of the first frequency conversion circuit 2, 22 is an input line receiving the output of the second frequency conversion circuit 3, and 23 and 24 are input lines 2 respectively.
1 and 22, the first and second frequency conversion circuits 3,
4 is an integrator circuit also serving as a low-pass filter receiving the output of No. 4. Reference numerals 25 and 26 denote first and second buffer amplifiers receiving the outputs of the integrating circuits 23 and 24, respectively. Reference numerals 27 and 28 denote first and second transformers which receive respective outputs of the first and second buffer amplifiers 25 and 26 at one end of a primary coil. The other ends of the primary coils of the first and second transformers 27 and 28 are both AC grounded, and the secondary coil connects the same polarity in parallel and connects one end having the same polarity as the primary coil. The connection point 29 is used as an output, and the other end is grounded. Reference numeral 30 denotes a third buffer amplifier having a connection point 29 connected to an input, and an output 31 of the third buffer amplifier is supplied to the next-stage frequency offset circuit 6 as an output of the common wave extraction circuit 5.

Next, the operation of the common wave extracting circuit 5 in the fourteenth embodiment will be described. From the first frequency conversion circuit 2 and the second frequency conversion circuit 3, the common wave eD of the desired wave signal component and the adjacent channel wave signal component e
U is obtained. Regarding the adjacent channel wave signal component, since the component obtained from the first frequency conversion circuit 2 and the component obtained from the second frequency conversion circuit 3 have different center frequencies, the component obtained from the first frequency conversion circuit 2 Is expressed as eU1, and the component obtained from the second frequency conversion circuit 3 is expressed as eU2. That is, the signal obtained from the first frequency conversion circuit 2 is eD + eU1, and the signal obtained from the second frequency conversion circuit 3 is eD + eU2. The first frequency conversion circuit 2 and the second frequency conversion circuit 3 may include unnecessary high-frequency components other than these signals, and these high-frequency components also serve as low-pass filters. It is reduced by the integration circuits 23 and 24.

Signal eD + eU1 obtained from first frequency conversion circuit 2 passing through integration circuits 23 and 24 also serving as a low-pass filter, and signal eD + eU2 obtained from second frequency conversion circuit 3 Are supplied corresponding to the buffer amplifiers 25 and 26, respectively. The buffer amplifiers 25 and 26 have a low output impedance. A signal eD + eU1 obtained from the first frequency conversion circuit 2 through the buffer amplifiers 25 and 26;
Signal eD + eU2 obtained from the frequency conversion circuit 3 of FIG.
Are supplied to the primary coils of transformers 27 and 28, respectively. The winding ratio of the secondary coil to the primary coil of the transformers 27 and 28 is 1. As a result, the secondary coils of the transformers 27 and 28 have the signal eD + eU1 obtained from the first frequency conversion circuit 2 and the signal eD + eU2 obtained from the second frequency conversion circuit 3 respectively.
Occurs correspondingly.

Here, since the terminals of the secondary coils of the transformers 27 and 28 are connected in parallel with the primary coil with matching polarity, the secondary coils are obtained from the first frequency conversion circuit 2 generated in the secondary coil. Regarding the common component of the signal eD + eU1 and each component of the signal eD + eU2 obtained from the second frequency conversion circuit 3, that is, the desired wave signal component eD, there is no problem such that the outputs of the secondary coils collide. , The terminal obtains the signal. On the other hand, the component eU1 generated from the first frequency conversion circuit 2 generated in the secondary coil of the transformer 27 and the component eU2 generated from the second frequency conversion circuit 3 generated in the secondary coil of the transformer 28 are: Since the components are different in frequency, they mutually flow into the secondary coils of the other party. At this time, the input impedance of the transformer viewed from the secondary coil becomes equal to the output impedance of the signal source connected to the primary coil, respectively.
As described above, the buffer amplifiers 25 and 26, which are signal sources,
Since the output impedance is set to be very low, a component other than the common wave component, that is, a component e generated from the first frequency conversion circuit 2 generated in the secondary coil of the transformer 27 is obtained.
U1 and the component eU2 generated from the second frequency conversion circuit 3 generated in the secondary coil of the transformer 28 are reduced by the low impedance.

In general, a buffer amplifier can be realized by using an emitter follower formed by a transistor. When this is used, the output impedance of the buffer amplifier connected by the wiring shown in FIG. 14 is several ohms or less. This principle will be described with reference to FIG. In FIG. 15, the transformer has two windings L1,
L2, the coil L1 is a primary coil and the coil L2 is a secondary coil.

The voltage and current at each coil terminal are set as follows. That is, the primary current is I1,
The secondary current is I2, the voltage generated between the terminals of the primary coil L1 is V1, and the voltage generated between the terminals of the secondary coil L2 is V2. The primary coil L1 and the secondary coil L
2 and M is a mutual inductance. At this time, when the load Z is connected to the secondary coil L2, the primary coil L
The input impedance Zin viewed from the terminal No. 1 is expressed by the following equation (1). ω is the angular frequency, L1 L2 ·
It is assumed that M ² holds.

[0133]

[Equation 46] Here, when the load Z is short-circuited, that is, Z = 0
Is zero as described below.

[0134]

[Equation 47]

Next, when the load Z is opened, that is, when Z = ∞, the input impedance Zin is:

[0136]

[Equation 48] And the impedance is simply due to the inductance of only the primary coil.

As described above, the input impedance of the primary coil of the transformers 27 and 28 is governed by the load of the secondary coil.

Returning to FIG. 14, applying the principle according to FIG. 15, the primary coils of the transformers 27 and 28 have buffer amplifiers 25 and 26 whose loads are short-circuited and the transformers 27 and 28 have short circuits.
Each input impedance of the secondary coil of (1) acts as zero (short-circuit state). Therefore, the signal currents iU1 and iU2 in FIG. 14 do not induce a voltage between the terminals of each secondary coil.

Normally, when driving a transformer,
The signal to the transformer is handled by current, and a magnetic flux proportional to the product of the current and the inductance of the primary coil is generated in the core of the transformer. Voltage is induced. Now, the potential induced at the terminal of the secondary coil L2 is e
Putting it as 2, it can be defined as follows.

[0140]

[Equation 49]

That is, in this case, since the signal source for driving the transformer is a current source, its output impedance is ∞. When viewed from the secondary coil side, only the secondary coil Is determined by the impedance due to the inductance. One of the features of this embodiment is that, unlike this usual method, the transformers are driven by a voltage source.

Next, the integrators 23 and 24 which also serve as low-pass filters in FIG. 14 will be briefly described. In the integrators 23 and 24, 1 / C is the integral proportional coefficient when the integral capacity is C. However, if the input signal can be represented by a sine wave, and its angular frequency is ω, the integral proportional coefficient is
1 / ωC, exhibiting frequency characteristics. This frequency characteristic also has the purpose of offsetting that the differential action of the transformers 27 and 28, that is, when the inductance is L, the differential proportional coefficient ωL appears in the differential output and has the frequency characteristic. That is, the first frequency conversion circuit 2
And flatten the overall frequency characteristics from the second frequency conversion circuit 3 to the common wave extraction output. Assuming that the frequency characteristic is flat in the frequency range of the signal targeted by the other circuit elements, the total frequency characteristic H from the first frequency conversion circuit 2 and the second frequency conversion circuit 3 to the common wave extraction output is In the expression, the frequency variable ω disappears and becomes flat.

[0143]

[Equation 50]

As described above, according to the present embodiment, in the common wave extraction circuit, which is one of the components of the receiving circuit, the signal source for driving the transformer is changed from the current source to the voltage source. Furthermore, by connecting the secondary coils of the transformer in parallel, depending on the polarity of the connection of the secondary coils of the transformer, an in-phase signal that is a common wave is
Alternatively, the impedance of the transformer can be increased only for signals of opposite phases, and for non-common waves, a load effect of an impedance close to zero occurs. The difference in the circuit with the common wave,
It can be at least twice as large as the conventional one, and an unprecedented removal action can be obtained.

(Embodiment 15) FIG. 16 shows a first embodiment of the present invention.
13 shows a configuration of a fifth embodiment. This embodiment is a modification of the fourteenth embodiment shown in FIG. 14, and common components are denoted by the same reference numerals. 14th
The second embodiment differs from the first embodiment in that an input line 21 receiving an output of the first frequency conversion circuit 2 and an input line 22 receiving an output of the second frequency conversion circuit 3 are each a first input having a first input. And second non-common-wave signal removing circuits 46 and 47
And the first and second non-common-wave signal removing circuits 4
6, 47 supply the output to the common wave extraction circuit 5n. Input line 2 receiving the output of first frequency conversion circuit 2
Input line 2 receiving the outputs of first and second frequency conversion circuits 3
2 is also connected to a balance monitoring circuit 43 which takes each input as a comparison signal input. The output 31a of the common wave signal extraction circuit 5n is connected to the frequency offset circuit 6 and is supplied as a third input of the balance monitoring circuit 43. Other outputs of the common wave signal extraction circuit 5n are supplied to first and second non-common wave signal detection circuits 41 and 42, respectively. First and second non-common wave signal detection circuits 41,
Reference numeral 42 denotes an input line 21 receiving an output of the first frequency conversion circuit 2 and an input line 22 receiving an output of the second frequency conversion circuit 3 as a second input. And to the first and second combining circuits 44 and 45, respectively. Outputs of the first and second combining circuits 44 and 45 are supplied as second inputs of the first and second non-common-wave signal removing circuits 46 and 47, respectively. The other configuration is that the common wave extraction circuit is generalized as 5n instead of 5 in FIG.
The description is omitted because it is the same as FIG.

Next, the operation of this embodiment will be described. As in FIG. 14, the signal eD + eU1 is supplied from the first frequency conversion circuit 2 and the second frequency conversion circuit 3
Gives the signal eD + eU2. The outputs of the first frequency conversion circuit 2 and the second frequency conversion circuit 3 are respectively connected to the first and second non-common wave signal removal circuits 46,
7 is supplied. Here, a subtraction is performed at a second input described later, and the output is supplied to the common wave signal extraction circuit 5n. These inputs to the common wave signal extraction circuit 5n are basically signals eD + eU1 of the first frequency conversion circuit 2 side.
And the signal eD + eU2 on the second frequency conversion circuit 3 side. Therefore, in the common wave extraction circuit 5n, FIG.
4 according to the fourteenth embodiment shown in FIG.
, The common wave signal eD is extracted. However, in the common wave extraction circuit 5n, FIG.
As is clear from the example shown in FIG. 1, the non-common wave signal cannot be completely removed. That is, the common wave extraction circuit 5
If the degree of coupling between the primary and secondary coils of the transformers 27 and 28 in n is incomplete, or if the output impedance of the amplifier 25 or 26 that drives the transformer is not sufficiently low, the removal of non-common wave components Insufficient ability. Therefore, in the present embodiment, the once extracted common wave signal output 31a is fed back and compared with the signal eD + eU1 on the first frequency conversion circuit 2 side or the signal eD + eU2 on the second frequency conversion circuit 3 side. This comparator is the first
And the second non-common-wave signal detection circuits 41 and 42.

The result is obtained by combining the first and second combining circuits 4.
The input signal from the input line 21 receiving the output of the first frequency conversion circuit 2 and the input signal from the input line 22 receiving the output of the second frequency conversion circuit 3 are modified through the lines 4 and 45. The circuits that add this correction are the first and second non-common-wave signal removing circuits 46 and 47. On the other hand, regarding the common wave signal eD, the signal strength on the first frequency conversion circuit 2 side and the second
The signal strength of the frequency conversion circuit 3 side is obtained from the input line 21 receiving the output of the first frequency conversion circuit 2 and the input line 22 receiving the output of the second frequency conversion circuit 3, or There is no guarantee that they will always be equal when viewed through the entire wave extraction circuit 5n. Therefore, when there is a remarkable difference in the signal strength, the difference is treated as a non-common wave component, and even if one has a sufficient signal strength, it is not effectively used. Therefore, the common wave extraction circuit 5n
And the first and second non-common wave signal removing circuits 46,
It is useful to compare the midpoint between the outputs of 47 and correct the result by equally offsetting the entire circuit.
The part that realizes this function passes the balance monitoring circuit 43 and its output via the first and second combining circuits 44 and 45 to the first and second non-common wave signal removing circuits 46 and 4 respectively.
7 is a path to return to.

FIG. 17 is a more specific version of the fifteenth embodiment shown in FIG. 16, and the same components are denoted by the same reference numerals.

As in FIG. 16, the first frequency conversion circuit 2
Input line 21 receiving the output of the second and the second frequency conversion circuit 3
Is supplied to first and second differential amplifiers 46a and 47a each having a first input, and the output thereof is supplied to the first and second differential amplifiers 46a and 47a which also serve as low-pass filters. Are supplied in correspondence with the integration circuits 23 and 24 of FIG. The first and second integration circuits 2
3. The output of the integration circuit 24 is supplied to the first and second buffer amplifiers 25 and 26, respectively. The first and second buffer amplifiers 25 and 26 apply feedback from the output to the negative input side. The first and second buffer amplifiers 25 and 26 supply their outputs to one ends of primary coils of transformers 27 and 28, respectively. The other ends of the primary coils of the transformers 27 and 28 are AC grounded, the secondary coils have the same polarity connected in parallel, and output the connection point 29 between the one ends having the same polarity as the primary coil. The ends are at least AC grounded. Secondary coil connection point 29
Is connected to the third buffer amplifier 30, and the third buffer amplifier 30 applies feedback from the output to the negative input side. Third
The output 31a of the buffer amplifier 30 is supplied to the frequency offset circuit 6 and connected to the positive inputs of the third and fourth differential amplifiers 41a and 42a. Connected to. Negative input terminals of the third and fourth differential amplifiers 41a and 42a are connected to an input line 21 receiving an output of the first frequency conversion circuit 2 and an input line 22 receiving an output of the second frequency conversion circuit 3, respectively. Connected to each other. Fourth and fifth buffer amplifiers 48, 49
Are connected by equal resistors R, and the connection point is connected to the negative input terminal of the eighth differential amplifier 50. The outputs of the third and fourth differential amplifiers 41a and 42a are respectively connected to the sixth and seventh differential amplifiers 44a and 45a.
a of the differential amplifiers 44a, 45a
Is connected to the output of the eighth differential amplifier 50. Outputs of the sixth and seventh differential amplifiers 44a and 45a are respectively connected to the first and second differential amplifiers 46a and 46a.
47a are respectively connected to the negative input terminals.

The correspondence between FIGS. 16 and 17 is that the non-common-wave signal removing circuits 46 and 47 are the first and second differential amplifiers 46a and 47a, respectively, the common-wave extracting circuit 5n is the common-wave extracting circuit 5p, The monitoring circuit 43 includes a fourth and fifth buffer amplifiers 48 and 49, a resistor R, and a differential amplifier 50.
1, 42 are third and fourth differential amplifiers 41a, 42
a, the combining circuits 44 and 45 are the sixth and seventh
Differential amplifiers 44a and 45a.

Next, the operation of a specific example of the present embodiment will be described. As in FIG. 16, the first frequency conversion circuit 2
Supplies the signal eD + eU1, and the second frequency conversion circuit 3 supplies the signal eD + eU2. First
Of the frequency conversion circuit 2 and the output of the second frequency conversion circuit 3 are supplied to positive input terminals of differential amplifiers 46a and 47a for removing non-common wave signals. Here, a second input described later is subtracted, and the output is supplied to the common wave extraction circuit 5p. In the common wave extracting circuit 5p, the integrating circuit 23 or the integrating circuit 24 also serving as a low-pass filter
As a result, unnecessary components having a high frequency are reduced and supplied to the first and second buffer amplifiers 25 and 26. The signal eD from the buffer amplifiers 25 and 26 to the first frequency conversion circuit 2 side
+ EU1 and the signal eD + on the second frequency conversion circuit 3 side.
In transformers 27 and 28 supplied with eU2, FIG.
As described in the fourteenth embodiment shown in FIG. 5, the common wave signal eD is extracted, and at the same time, the residual for removing the non-common wave component is generated. The secondary coil outputs of the transformers 27 and 28 including the residual of the non-common wave component are output to differential amplifiers 41a and 42a.
a is supplied to the positive input. Differential amplifiers 41a and 42
a is the output 2 of the first frequency conversion circuit 2 as a comparison signal.
1 and the signal of the output 22 of the second frequency conversion circuit 3 are obtained,
Common wave signal output 31a extracted as a substantially common wave component
Is transmitted to the differential amplifiers 44a and 45a. On the other hand, the common wave extraction output 31a is fed back to the differential amplifiers 44a and 45a and compared with the signal eD + eU1 on the first frequency conversion circuit 2 side or the signal eD + eU2 on the second frequency conversion circuit 3 side. These differential amplifiers 41a and 42a are the above-mentioned non-common wave signal detection circuits 41 and 42. The result is transmitted to the positive input terminals of the differential amplifiers 44a and 45a as the combining circuits 44 and 45. On the other hand, regarding the common wave signal eD,
Signal strength or output 2 entering the first frequency conversion circuit 2 side
The circuit gain from 1 to the output 31a and the signal strength entering the second frequency conversion circuit 3 or the output from the output 22 to the output 31a
In order to obtain an output with high efficiency when there is a difference between the circuit gains of the first and second frequency converters, the signal of the output 21 of the first frequency converter 2 and the output 22 of the second frequency converter 3 are buffered by the buffer amplifier 48,
49, the intermediate value of the resistor R and the common wave extraction output 31a are compared by the differential amplifier 50, and the result is compared with the output 21 of the first frequency conversion circuit 2 and the output 21 of the second frequency conversion circuit 3. It is passed to the negative input of a differential amplifier 44a, 45a which is a combining circuit 44 or 45 for addition to the output 22.

These signals synthesized by the differential amplifiers 44a and 45a are supplied corresponding to the negative input terminals of the differential amplifiers 46a and 47a, respectively, and are connected to the output 21 of the first frequency conversion circuit 2 and the The output 22 of the second frequency conversion circuit 3 is modified.

As described above, according to the present embodiment, the function of removing the non-common wave component remaining in the common wave extraction output,
Regarding the common wave signal eD 1, the signal strength entering the first frequency conversion circuit 2 or the circuit gain from the output 21 to the output 31a and the signal strength entering the second frequency conversion circuit 3 or the output from the output 22 to the output 31a Between the circuit gain
When there is a difference, a function of removing the difference can be realized.

(Embodiment 16) FIG. 18 shows a first embodiment of the present invention.
14 shows a configuration of a sixth embodiment. There is also QPSK as a communication system targeted by the present application, and only the one shown in FIGS. 14, 16 and 17 can extract only the one having the same phase, that is, the I-axis component in QPSK. In the present embodiment, signals having phases different from each other by 180 degrees are extracted. As shown in FIG. 18, the configuration is basically the same as that of FIG. 14, and the secondary side of two transformers is used. Is connected in reverse between the two units. Except for this point, the configuration is the same as that of FIG. Regarding the operation, in FIG. 14, the operation in which the in-phase signals could be generated without interference on the secondary side, but since the polarity of one secondary coil is inverted, the signal without interference has the opposite phase during reception. The signal, ie, the Q signal in QPSK, is of interest. On the secondary coil side, the in-phase signals have a relationship of opposite phases to each other, interfere with each other, and are attenuated.

(Embodiment 17) FIG. 19 shows a first embodiment of the present invention.
This shows a configuration of the seventh embodiment, in which the case where the inverted-phase signal shown in the sixteenth embodiment is targeted is applied to the receiving circuits shown in FIGS. In FIG. 17, the removal of the non-common wave signal component and the improvement of the balance of the in-phase signal are achieved.
The common wave signal is treated so as to obtain the same effect as the opposite phase signal.

(Embodiment 18) FIG. 21 shows a first embodiment of the present invention.
FIG. 28 is a block diagram illustrating a configuration of a receiving circuit according to an eighth embodiment. In this embodiment, a method similar to that of the receiving circuit according to the fifth embodiment of the present invention shown in FIG. 5 is employed as a receiving method. Therefore, FIG.
The same reference numerals are given to the same components as those described above, and the detailed description is omitted. The unique configuration of FIG. 21 will be described below. The local frequency signal generation circuit 4A according to the fifth embodiment is provided with a desired wave carrier frequency signal source 32 for generating a desired wave carrier frequency signal and a parallel relationship with the desired wave carrier frequency signal source 32. An offset frequency signal source 33 for generating an offset frequency signal; a carrier frequency signal phase shift circuit 34 for shifting (ie, delaying) a carrier frequency signal from the desired wave carrier frequency signal source 32; An offset frequency signal phase shift circuit 35 for shifting the phase of the offset frequency signal from the generation source 33;
And a second quadrature modulator 36b.

The first quadrature modulator 36 a multiplies the desired wave carrier frequency signal generated by the desired wave carrier frequency signal source 32 by the offset frequency signal generated by the offset frequency signal source 33. A multiplier 37a that multiplies the desired carrier frequency signal after the phase shift processing by the carrier frequency signal phase shift circuit 34 by the offset frequency signal after the phase shift processing by the offset frequency signal phase shift circuit 35; Multiplier 38a and the first
Is added to the multiplication result of the multiplier 37a and the multiplication result of the second multiplier 38a, and the local frequency on the negative offset side (ωc−ωo) is added.
) Which outputs a negative offset side local frequency output adder 51.

The second quadrature modulator 36b converts the desired wave carrier frequency signal generated by the desired wave carrier frequency signal source 32 and the offset frequency signal subjected to the phase shift processing by the offset frequency signal phase shift circuit 35. A third multiplier 37b for multiplication and a fourth multiplier for multiplying the offset frequency signal generated by the offset frequency signal source 33 by the desired frequency carrier frequency signal after the phase shift processing by the carrier frequency signal phase shift circuit 34. Multiplier 38b and the third
Is added to the multiplication result of the multiplier 37b and the multiplication result of the fourth multiplier 38b, and the positive offset-side local frequency (ωc + ωo)
) And a positive offset-side local frequency output adder 52 that outputs The output of the negative offset side local frequency output adder 51 is output to the second quadrature demodulator 12.
On the other hand, the output of the positive offset side local frequency output adder 52 is sent to the first quadrature demodulation 11.

Next, the operating principle and operation of the eighteenth embodiment will be described. The desired wave carrier frequency signal ωc from the desired wave carrier frequency signal source 32 is supplied to a carrier frequency signal phase shift circuit 34, and the phase thereof is delayed by π / 2 in the desired wave carrier frequency signal. Offset frequency signal ωo from offset frequency signal source 33
Is supplied to the offset frequency signal phase shift circuit 35 to delay the phase by π / 2 in the offset frequency signal. Two multipliers 3 constituting the first quadrature modulator 36a
7a and 38a, the first multiplier 37a includes a desired wave carrier frequency signal cosωct from the desired wave carrier frequency signal source 32 and an offset frequency signal source 33.
And the offset frequency signal cos ωot from The second multiplier 38a delays the phase of the desired wave carrier frequency signal sinωct delayed by π / 2 from the carrier frequency signal phase shift circuit 34 and the phase of π / 2 from the offset frequency signal phase shift circuit 35. The input offset frequency signal sinωot is input. As a result, the output of the adder 51 for local frequency output on the negative offset side of the first quadrature modulator 36a has a frequency of ωc−ωo as shown in the following equation. cosωct × cosωot + sinωct × sinω
ot = cos (ωc−ωo) t

[0160] Of the two multipliers 37b and 38b constituting the second quadrature modulator 36b, the third multiplier 37b includes:
The desired wave carrier frequency signal cosωct from the desired wave carrier frequency signal source 32 and the offset frequency signal sinωot delayed by π / 2 from the offset frequency signal phase shift circuit 35 are input. The fourth multiplier 38b outputs the π /
The desired carrier frequency signal sin delayed in phase by two
ωct and the offset frequency signal cosωot from the offset frequency signal phase shift circuit 35 are input. As a result, the output of the adder 52 for the local frequency output on the negative offset side of the second quadrature modulator 36b has ωc +
ωo is obtained. cosωct × sinωot + sinωct × cosω
ot = sin (ωc + ωo) t

As described above, according to the above embodiment, it is apparent that the complementary local oscillation frequency required by the basic configuration of the present invention can be generated and obtained as an independent output. Further, it is apparent that it is not necessary to use a filter corresponding to each frequency, and even if the carrier frequency of the desired signal is variable, it can cope with no problem.

(Embodiment 19) FIG. 22 shows a first embodiment of the present invention.
FIG. 39 is a block diagram illustrating a configuration of a receiving circuit according to a ninth embodiment. In this embodiment, fc + fo and fc-fo
In order to obtain the above, two phase shifters, one quadrature modulator, two adders, and one polarity inversion circuit are used. As a method of this embodiment, a method similar to that of the receiving circuit according to the fifth embodiment of the present invention shown in FIG. 5 is employed. Therefore, the same components as those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted. The unique configuration of FIG. 21 will be described below. Local frequency signal generation circuit 4 according to the fifth embodiment.
A is a desired wave carrier frequency signal generation source 32 for generating a desired wave carrier frequency signal, and an offset frequency signal generation source 33 provided in parallel with the desired wave carrier frequency signal generation source 32 for generating an offset frequency signal. A carrier frequency signal phase shift circuit 34 for shifting the phase of the carrier frequency signal from the desired carrier frequency signal generator 32.
, An offset frequency signal phase shift circuit 35 which is means for shifting the phase of the offset frequency signal from the offset frequency signal source 33, a quadrature modulator 36a, a polarity inversion circuit 53, and a positive offset side local frequency output adder. 54.

The quadrature modulator 36a has the same configuration as that of the first quadrature modulator in the eighteenth embodiment, and includes the desired wave carrier frequency signal generated by the desired wave carrier frequency signal source 32. A first multiplier 37a for multiplying the offset frequency signal generated by the offset frequency signal generation source 33, and a desired wave carrier frequency signal and an offset frequency signal shifted by the carrier frequency signal phase shift circuit 34; A second multiplier 38a that multiplies the offset frequency signal after the phase shift processing by the phase circuit 35, a multiplication result of the first multiplier 37a and a multiplication result of the second multiplier 38a are added to be negative. And a negative offset side local frequency output adder 51 for outputting the offset side local frequency (ωc−ωo).

The polarity inversion circuit 53 performs a polarity inversion process on the output of the second multiplier 38a. The positive offset side local frequency output adder 54 adds the multiplication result output from the first multiplier 37a and the polarity inversion output from the polarity inversion circuit 53,
Outputs the local frequency on the positive offset side (ωc + ωo). The adder 5 for outputting the local frequency on the negative offset side
1 is sent to the second quadrature demodulation 12, while the output of the positive offset side local frequency output adder 54 is sent to the first quadrature demodulation 11.

Next, the operating principle and operation of the nineteenth embodiment will be described. The desired wave carrier frequency signal ωc from the desired wave carrier frequency signal source 32 is supplied to a carrier frequency signal phase shift circuit 34, and the phase thereof is delayed by π / 2 in the desired wave carrier frequency signal. Offset frequency signal ωo from offset frequency signal source 33
Is supplied to the offset frequency signal phase shift circuit 35 to delay the phase by π / 2 in the offset frequency signal.

The first multiplier 37a of the two multipliers 37a and 38a constituting the quadrature modulator 36a has the desired wave carrier frequency signal cos ωct from the desired wave carrier frequency signal source 32 and the offset frequency signal. Source 3
3 is input. The second multiplier 38a delays the phase of the desired wave carrier frequency signal sinωct delayed by π / 2 from the carrier frequency signal phase shift circuit 34 and the phase of π / 2 from the offset frequency signal phase shift circuit 35. The input offset frequency signal sinωot is input. As a result, the output of the adder 51 for the local frequency output on the negative offset side of the quadrature modulator 36a has a frequency ωc−ωo as shown in the following equation. cosωct × cosωot + sinωct × sinω
ot = cos (ωc−ωo) t

A part of the output of the second multiplier 38a among the outputs of the two multipliers 37a and 38a constituting the quadrature modulator 36a is supplied to the polarity inverting circuit 53, and the inverted output is supplied to the first inverter. The output of the multiplier 37a and the output of the local frequency output adder 54 on the positive offset side are input to the adder 54 as shown in the following equation.
A frequency of ωc + ωo is generated. cosωct × sinωot + (− 1) sinωct ×
cosωot = cos (ωc + ωo) t

As described above, according to the above embodiment, it is clear that the complementary local oscillation frequency required by the basic configuration of the present invention can be generated and obtained as an independent output. Further, it is apparent that it is not necessary to use a filter corresponding to each frequency, and even if the carrier frequency of the desired signal is variable, it can cope with no problem.

(Embodiment 20) FIG. 23 shows a second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a receiving circuit according to an embodiment of the present invention. In this embodiment, fc + fo and fc-fo
In order to obtain the above, two phase shifters, one quadrature modulator, two adders, and one polarity inversion circuit are used. As a method of this embodiment, a method similar to that of the receiving circuit according to the fifth embodiment of the present invention shown in FIG. 5 is employed. Therefore, the same components as those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted. The unique configuration of FIG. 21 will be described below. Local frequency signal generation circuit 4 according to the fifth embodiment.
A is a desired wave carrier frequency signal generation source 32 for generating a desired wave carrier frequency signal, and an offset frequency signal generation source 33 provided in parallel with the desired wave carrier frequency signal generation source 32 for generating an offset frequency signal. A carrier frequency signal phase shift circuit 34 for shifting the phase of the carrier frequency signal from the desired carrier frequency signal generator 32.
, An offset frequency signal phase shift circuit 35 which is means for shifting the phase of the offset frequency signal from the offset frequency signal source 33, a quadrature modulator 36a, a polarity inversion circuit 53, and a positive offset side local frequency output adder. 54.

The quadrature modulator 36a has the same configuration as that of the first quadrature modulator in the eighteenth embodiment. A first multiplier 37a for multiplying the offset frequency signal generated by the offset frequency signal generation source 33, and a desired wave carrier frequency signal and an offset frequency signal shifted by the carrier frequency signal phase shift circuit 34; A second multiplier 38a that multiplies the offset frequency signal after the phase shift processing by the phase circuit 35, a multiplication result of the first multiplier 37a and a multiplication result of the second multiplier 38a are added to be negative. A negative offset side local frequency output adder 51 for outputting the offset side local frequency (ωc−ωo).

The polarity inversion circuit 53 performs a polarity inversion process on the output of the second multiplier 38a. The positive offset side local frequency output adder 54 adds the multiplication result output from the first multiplier 37a and the polarity inversion output from the polarity inversion circuit 53,
Outputs the local frequency on the positive offset side (ωc + ωo). Unlike the nineteenth embodiment, the output of the negative offset side local frequency output adder 51 is sent to the first quadrature demodulation 11, while the output of the positive offset side local frequency output adder 54 is output. Are sent to the second quadrature demodulation 12.

Next, the operating principle and operation of the twentieth embodiment will be described. The desired wave carrier frequency signal ωc from the desired wave carrier frequency signal source 32 is supplied to a carrier frequency signal phase shift circuit 34, and the phase thereof is delayed by π / 2 in the desired wave carrier frequency signal. Offset frequency signal ωo from offset frequency signal source 33
Is supplied to the offset frequency signal phase shift circuit 35 to delay the phase by π / 2 in the offset frequency signal.

The first multiplier 37a of the two multipliers 37a and 38a constituting the quadrature modulator 36a has a desired wave carrier frequency signal cos ωct and an offset frequency signal from the desired wave carrier frequency signal source 32. Source 3
3 is input. The second multiplier 38a delays the phase of the desired wave carrier frequency signal sinωct delayed by π / 2 from the carrier frequency signal phase shift circuit 34 and the phase of π / 2 from the offset frequency signal phase shift circuit 35. The input offset frequency signal sinωot is input. As a result, the output of the adder 51 for the local frequency output on the negative offset side of the quadrature modulator 36a has a frequency ωc−ωo as shown in the following equation. cosωct × cosωot + sinωct × sinω
ot = cos (ωc−ωo) t

A part of the output of the second multiplier 38a among the outputs of the two multipliers 37a and 38a constituting the quadrature modulator 36a is supplied to the polarity inversion circuit 53, and the inverted output is supplied to the first inverter. The output of the multiplier 37a and the output of the local frequency output adder 54 on the positive offset side are input to the adder 54 as shown in the following equation.
A frequency of ωc + ωo is generated. cosωct × sinωot + (− 1) sinωct ×
cosωot = cos (ωc + ωo) t

As described above, according to the above-described embodiment, it is clear that the complementary local oscillation frequency required by the basic configuration of the present invention can be generated and obtained as an independent output. Further, it is apparent that it is not necessary to use a filter corresponding to each frequency, and even if the carrier frequency of the desired signal is variable, it can cope with no problem.

(Embodiment 21) FIG. 24 shows a second embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a receiving circuit according to one embodiment. This embodiment is mainly used in a digital modulation type communication system having a plurality of channels,
An object of the present invention is to reduce the power of a receiving system, simplify a circuit, and reduce power consumption. In FIG.
Reference numeral 1 denotes a first data input line to which data of a first reception signal obtained by a frequency conversion circuit or a quadrature demodulation circuit is input, and 62 denotes a Fourier transform for a signal input from the first data input line 61. A first Fourier transformer that performs
63 denotes a first Fourier transform obtained by the first Fourier transformer 62.
Represents the Fourier transform output of. Reference numeral 64 denotes a second data input line to which data of a second reception signal obtained by the frequency conversion circuit or the quadrature demodulation circuit is input, and 65 denotes a Fourier transform for a signal input from the second data input line 64. A second Fourier transformer 66 performing the transformation represents the second Fourier transform output obtained by the second Fourier transformer 65.

Reference numeral 67 denotes a correlator for receiving the output of each of the frequency components of the first and second Fourier transformers 62 and 65 for each frequency and calculating a correlation coefficient, and 68 denotes a first and second Fourier transformer. An adder for adding the outputs of 62 and 65; 69, an output of the correlator 67; 70, a weighting function unit for receiving the obtained correlator output 69 for weighting;
Is a weighting value multiplier for multiplying the addition output of the adder 68 by the output of the weighting function unit 70, 72 is a post-processing circuit for performing post-processing of the multiplication operation by the weighting value multiplier, 73 is an output of the weighting value multiplier. An inverse Fourier transformer input 74 generated by the post-processing is an inverse Fourier transformer 74 that receives the inverse Fourier transformer input and performs an inverse Fourier transform process, and 75 is an inverse Fourier transform output.

Next, the operating principle and operation of the twenty-first embodiment will be described. The first to thirteenth described above
In the embodiment, the first frequency conversion circuit 2 and the second frequency conversion circuit 3 are provided, the first quadrature demodulation circuit 11 and the second quadrature demodulation circuit are provided, or one frequency conversion circuit It has a basic configuration of whether a conversion circuit and one orthogonal demodulation circuit are provided. With this configuration, in the receiving operation, the receiving circuit obtains the first received signal and the second received signal. In this embodiment, the first received signal is represented by x (t), and the first data input line 61
To enter. The second received signal is represented by y (t),
Is input to the data input line 64. First data input line 6
The first received signal x (t) input to 1 is input to a first Fourier transformer 62, where it is subjected to Fourier transform processing to obtain a first Fourier transform output 63. The second received signal y (t) is input to a second Fourier transformer 65, where it is subjected to Fourier transform processing to obtain a second Fourier transform output 66. These first and second Fourier transformers 62,
By the Fourier transform processing in 65, the data of the input first and second received signals is converted from time axis information to frequency axis information.

The first and second Fourier transform outputs 63,
65 is taken into a correlator 67, and the correlator 67 receives the output of the frequency components of the first and second Fourier transform outputs 63 and 66 for each frequency and calculates a correlation coefficient. On the other hand, the first and second Fourier transform outputs 6
3 and 65 are input to an adder 68 separately from the correlation coefficient calculated by the correlator 67, and the adder 68 adds the output signals that have undergone the Fourier transform. Further, the correlation coefficient output by the correlator 67 is
The data is input to the weighting function unit 70, where the weighting process is performed. Then, the weight value multiplier 71 is added to the adder 68.
And the output of the weighting function unit 70 are multiplied by the quantity output signal. Thereafter, the post-processing circuit 72 performs post-processing of the multiplication operation by the weighting value multiplier, and the post-processing is executed, and the inverse Fourier transformer input 73 generated and received by the inverse Fourier transformer 74 is subjected to the inverse Fourier transform processing. Then, the processing data is returned from the frequency axis information to the time axis information, and a desired wave extraction result is obtained as an inverse Fourier transform output 75.

Next, the principle by which the desired wave is extracted will be described theoretically. First, the theory of the suppression effect on the undesired wave when the desired wave does not arrive will be described. After the undesired waves (which exist independently in time between the two signal systems) are synchronously added, the amplitude component is multiplied by R (R is a correlation coefficient). The arithmetic expression in the correlator is shown below.

[0181]

(Equation 51) Assuming that the power PNO of the undesired wave is a constant value in each averaging window for calculating the correlation coefficient, the power PN of the processing output is expressed by the following equation. PN = (R ² PNO) / 2 where PNO: power of undesired wave R: correlation coefficient

Since the correlation coefficient R is calculated using a finite averaging window, a statistical error occurs and does not match the true correlation coefficient value. Since R is calculated for N independent samples and the true correlation coefficient should be 0, the distribution of R is represented by the following probability density function.

[0183]

(Equation 52) From the above, the average power of the processing output is expressed by the following equation.

[0184]

(Equation 53)

Here, the averaging window for calculating the correlation coefficient is set to the length T
Assuming that it is a rectangular window of c and the length of the Hamming window at the time of performing the Fourier transform is TF, the number N of independent samples existing in the average window is as follows. N = (Tc) / (TF) Therefore, the processing output of the undesired wave when the number N is large can be expressed by the following equation.

[0186]

(Equation 54) That is, it is proportional to 1 / N.

Next, a description will be given of an operation of suppressing a non-desired wave when a desired wave has arrived. When band division is performed on the signal component, it is possible to further distinguish between a section where the desired signal is present and a section where the desired signal is not present. The amplitude of the k-th band component including the desired wave component is output by multiplying by the correlation coefficient R (k) in that band. R (k) can be represented by the following equation.

[0188]

[Equation 55] k, PSO (k) and PNO (k) are set to a constant value PS
When O and PNO are set, the effect of suppressing the undesired wave can be obtained by the following equation.

[0189]

[Equation 56] From this equation, it can be seen that the smaller the number of bands containing the desired wave component, the greater the effect of improving the desired / unwanted wave ratio.

Therefore, according to the present embodiment, the undesired wave is converted into the first received signal and the second Time-independent between the two signal systems with the signal,
By utilizing the property that can be treated as an unbalanced signal, a function of suppressing this undesired wave can be realized.

(Embodiment 22) FIGS. 25 to 33 are diagrams illustrating the configuration and operation principle of a receiving circuit according to a twenty-second embodiment of the present invention. Each of the embodiments described above is a method corresponding to a multiplex digital modulation method such as a quadrature modulation signal. This method requires two quadrature demodulators, which is not the best for reducing power and simplifying the apparatus. The present embodiment is an improvement on this point. Therefore, in the present embodiment, one quadrature demodulator is provided. For this purpose, secondary sampling in the A / D converter is performed to prevent aliasing on the frequency axis. From the A / D conversion output, quadrature demodulation output based on the complementary local oscillation frequency on the defective side which is originally required by digital signal processing is obtained. It is configured to generate.

FIG. 25 is a block diagram showing a configuration of a receiving circuit according to the twenty-second embodiment. In FIG. 25, 1 is an antenna receiving a received signal, 96 is a receiving bandpass filter (bandpass filter) which is a bandpass filter for shaping the waveform of the received signal in a predetermined frequency band, 11 is a quadrature demodulator which receives the received signal, 4 is a local frequency signal generation circuit, 86 is a first low-pass filter that cuts a high-frequency band of one output signal from the quadrature demodulator, and 87 is a second low-pass filter that cuts the other output signal from the quadrature demodulator. 90 is a first A / D converter for A / D converting the output of the first low-pass filter, and 91 is a second A / D converter.
A / D for A / D converting the low-pass filter output of
A converter 92 is provided for the first and second A / D converters 9.
0, 91, a function of generating a clock having a frequency equal to or more than the bandwidth of the received signal, a function of adding a delay pulse train to the sampling clock pulse train, and a sampling clock pulse train and a delay pulse train A sampling signal generation source having a function of providing A / D converters 90 and 91 as sampling pulses, 9
An arithmetic unit 3 extracts a desired reception channel signal from the digital output data of the first and second A / D converters 90 and 91.

In this embodiment, the quadrature demodulator 11
Are a first multiplier 78 for inputting a reception signal from the reception bandpass filter 96 and performing frequency conversion, and a second multiplier 7
9 and a frequency offset circuit 98 for offsetting the local oscillation frequency signal from the local frequency signal generation circuit 4 and inputting it to the second multiplier 79, and performs a frequency conversion process on the received signal.

Next, the operation principle and operation of the twenty-second embodiment will be described. In FIG. 25, antenna 1
After passing through the reception bandpass filter 96 to form a target in-band signal group, the quadrature demodulator 11 extracts an I-axis component and a Q-axis component. This signal is subjected to removal of unnecessary high-frequency components by first and second low-pass filters 86 and 87 and then to first and second A / D signals.
The signals are input to converters 90 and 91. A / D converters 90 and 9
In the A / D conversion operation in 1, the sampling signal from the sampling signal generation source 92 is supplied to A / D converters 90 and 91 to perform the sampling operation. Then, the digital data obtained through this sampling operation is sent to the arithmetic unit 93, where digital signal processing is performed, and a baseband output is obtained. Where A / D
When normal sampling is performed in the converters 90 and 91, aliasing due to sampling is generated, and the digital frequency conversion scheduled thereafter cannot be performed.

FIG. 26 is a diagram for explaining how aliasing occurs as a result of sampling by the A / D converters 90 and 91. First, a signal as shown in FIG. 26A is supplied, and when this signal is passed through a low-pass filter, the signal shown in FIG.
As shown in (B), the signal from which the high frequency component has been removed is obtained.
When this signal is sampled, A in FIG.
An alias occurs as shown in the / D conversion output diagram. Therefore, in the present embodiment, means for preventing aliasing from being generated on the frequency axis is provided. This will be described below using equations.

If the carrier frequency is fc and the QPSK subcarrier frequency is fo, the QPSK radio signal fRF
Is

[0197]

[Equation 57] Can be expressed as Here, the phase signal θ (t) is θ (t) = 0, ± π / 2, π. Consider a situation in a multi-channel communication system such as PDC. FIG. 27 is a diagram illustrating a model (state of arrangement) of reception channels in a multi-channel communication system. Now, as shown in FIG. 27, it is assumed that the channels are arranged at equal intervals in frequency.
Also, the channel interval frequency is set to fb. Then, assuming that N channels enter through the input filter of the receiver, the input signal fIN becomes

[0198]

[Equation 58] In this case, if each channel is in contact, 2fo = fb.

[0199]

[Equation 59] Can be described.

The signal group is subjected to frequency conversion as direct conversion. In general, if the frequency of a signal obtained by performing frequency conversion for lowering the frequency by fLO is fDC, this fDC can be expressed by the following equation.

[0201]

[Equation 60] In the above equation, the latter two terms have a frequency twice as high as the RF frequency, and are usually easily blocked by the frequency characteristics of the circuit.
Therefore, the frequency fDC after the frequency conversion may be expressed as the following equation.

[0202]

[Equation 61]

Here, some channels have a negative fc-fLO. The frequency is negative, which means that the Q axis of the polarity of the phase rotation plane of the QPSK signal is inverted, that is, QPSK.
It only means that the rotation of the signal is reversed.
Therefore, the fact that the polarity of the frequency is negative does not mean that the signal disappears.

Next, this signal is supplied to A / D converters 90 and 91 for digitization. A / D converter 9
In this case, 0 and 91 are equivalent to sampling, and the output is discretized. In the discretization processing, the signal before the processing and the signal after the processing do not always have a one-to-one correspondence. Aliasing occurs in most cases. Therefore, the A / D-converted signal is suppressed to less than Ａ of the A / D conversion frequency so as not to generate an alias, or the conversion signal sequence of the A / D conversion is made plural (higher-order sampling). .

Here, the physical meaning of the negative frequency will be considered. This opens the way to use the negative region of the frequency axis. The following equation is obtained by setting the QPSK carrier to a negative frequency. Equations in which the position of the negative signal is mathematically moved and rewritten into time and function values are listed.

[0206]

(Equation 62)

FIG. 28 is a diagram showing an A / D conversion output having a negative frequency range. The physical meaning of the negative frequency region is not different from the behavior of the positive frequency region as seen from the above equation. However, the expression -fc treats fc as positive and means that the traveling direction on the frequency axis or the direction of the line of sight is exactly opposite. That is, it means that the rotation on the frequency circumference is reversed, and that the frequency is zero means that the rotation has stopped somewhere on the circumference. QPS that behaves θa (t) at that position
Since the K operation is performed, the spectrum indicates the bandwidth of the QPSK information.

For example, the RF signal and the first and second signals
It is considered that the local signals applied to the multipliers 94 and 95 of FIG. 7 have been struggling in the direction of rotation in the respective frequency circles at the time of frequency conversion. In reducing the frequency, they are competing for rotations in opposite directions. As the frequency approaches zero, the speed of rotation slows down and finally stops rotating. As the distance goes further, the reverse rotation speed on the local signal side prevails, and the rotation direction is reversed.

From the above, in the theoretical development here,
A signal spectrum in which the result is a negative frequency region due to frequency conversion or the like is not folded back into a positive region as generally represented, but is expressed using a frequency axis in positive and negative continuity. Its purpose is to enable the representation that the signal itself has information consisting of multiple axes, such as a QPSK signal. In the conventional general expression, the frequency domain is limited to the positive region, and the spectrum is folded to narrow the frequency space, and one degree of freedom in the expression is lost.

On the other hand, it is necessary to decompose the signal itself to form a phase space as a function of time, that is, phase, so that it can be identified in the orthogonal space. FIG. 29 shows a method of decomposing a signal component into orthogonal components using a cosine function (cos function) and a sine function (sin function) using a phase difference of π / 2. In this figure, fI (t)
Is represented by a cos function, so that it is not subject to positive or negative dominance on the frequency axis (it is an even function). fQ (t) is si
Since the function is represented by the n function, the sign of the function value is inverted in an area where the frequency is negative (an odd function).

By using the above two techniques, the conversion frequency (or sampling frequency) fs is generally folded in A / D conversion, and the high frequency side is converted to the conversion frequency fs.
Breaking away from the conventional spectral arrangement of folding below,
The image spectrum can be expressed as it is above the conversion frequency fs.

Next, the two orthogonal signals are A / D converted. The frequency domain of the two orthogonal signals is near the baseband, and the conversion speed may be at least twice the frequency of the target signal according to Shannon's sampling theorem. FIG. 30 shows two orthogonal signals as A
FIG. 31 is a diagram illustrating an example of orthogonal sampling in the case of performing / D conversion. The configuration illustrated in FIG. 30 is the same as the configuration illustrated in FIG. Is shown while clarifying the signal flowing in each part. In FIG. 30, Ts represents a sampling period. In this A / D conversion operation,
The sampling frequency ωs forms a pair of sample sequences fI (t) and fQ (t) when ωs ≧ Wo. In this method, the signal f (t) is sampled as a point on the IQ plane, so that information such as the rotation direction of the signal can be secured and digitized.

Here, considering the frequency offset, which is the gist of the present embodiment, the configuration of FIG. 30 is as shown in FIG. That is, the local frequency is changed from ωc to ωc−ω
In this case, the offset frequency ωo remains in the output signal. Since the signals fI (ωot) and fQ (ωot) supplied to the A / D converters 90 and 91 include the frequency ωo and the frequency offset ωo, which are the transmission speed of the baseband signal, the roll-off rate is 0. For a baseband transmission of 5 or less, it is considered to have a frequency bandwidth of 3ωo around the carrier frequency. Therefore, it is necessary and sufficient if the frequency of the sampling clock is 6ωo or more. Since the signal f (t) is sampled as a point on an IQ orthogonal plane, information such as the rotation direction of the signal can be secured, and the frequency axis Positive and negative continuity can be preserved and digitized.

Therefore, the digital signal output of the receiving circuit can be converted to either positive or negative frequency by digital signal processing. That is, minus 2ω
The signal fI (ω
ot) and fQ (ωot), signals fI (−ωot) and fQ (−ωot) can be obtained. As a result, according to the above method, only one of the dual quadrature demodulators with the complementary local oscillation frequency is required, and the high-frequency circuit can be simplified to about half and the power consumption can be reduced.

FIG. 32 is a diagram for explaining another sampling operation different from the orthogonal sampling (FIGS. 30 and 31) when the above-described A / D conversion operation is performed. This is an application of Shannon's secondary sampling. In this sampling method, as shown in FIG. 32, a signal fb (t) obtained by lowering a high-frequency input signal f (t) to a baseband by frequency conversion is converted into two A / D signals.
Connect to the converter. If such a configuration is adopted, sampling pulses at equal time intervals as shown in FIG.
To obtain a pulse train of two systems. As a result, as shown in FIG. 33, the signal to be sampled is sampled by a double pulse. The sampling frequency is set to a value equal to or larger than the frequency bandwidth of the signal. That is, in the above case, since the transmission speed of the baseband signal fb (t) is ωo, when the roll-off rate is 0.5 or less, the frequency bandwidth is about 3ωo. Therefore, the sampling frequency may be 3ωo. By such sampling, components other than the real axis can be extracted from the phase space at the frequency of the signal to be sampled, so that the obtained information is continuous on the frequency axis in positive and negative directions. However, if the delay amount is set to a value corresponding to π,
Since there is only the real axis component, a phase shift amount other than π must be selected. When this method is applied to the frequency offset type of the present invention, it becomes as shown in FIG.

(Twenty-third Embodiment) FIGS. 34 and 35 are diagrams illustrating a configuration and an operation principle of a receiving circuit according to a twenty-third embodiment of the present invention. The twenty-third embodiment is also based on the same idea as in the twenty-second embodiment, and is intended to reduce the number of quadrature demodulators to one to achieve power reduction and simplification of the device. It is. Therefore, by performing secondary sampling in the A / D converter, aliasing on the frequency axis is prevented, and A / D conversion is performed.
It is configured to generate a frequency conversion output based on the complementary local oscillation frequency of the originally required missing side from the conversion output by digital signal processing.

FIG. 34 is a block diagram showing a configuration of a receiving circuit according to the twenty-third embodiment. In FIG. 34, 1
Is an antenna receiving the received signal, 96 is a reception bandpass filter which is a bandpass filter for shaping the waveform of the received signal in a predetermined frequency band, 11 is a quadrature demodulator which receives the received signal, 4 is a local frequency signal generating circuit, 86 is A first low-pass filter that cuts the high-frequency band of one output signal (I) from the quadrature demodulator 11, and a second low-pass filter 87 cuts the high-frequency band of the one output signal (I) from the quadrature demodulator 11. A low-pass filter; 90, a first A / D converter for A / D-converting the output of the first low-pass filter; 91, a second A / D converter for A / D-converting the output of the second low-pass filter; Are the first and second A / D converters 90,
A sampling signal generation source 91 has a function of generating a clock having a frequency equal to or higher than the bandwidth of the received signal and providing it as a sampling pulse. A sampling signal generator 97 offsets the sampling clock signal from the sampling signal generation source 92 to a second signal. Is a delay circuit supplied to the A / D converter 91. Also, the other output signal Q of the quadrature demodulator 11
Are the filters 86 and 87, the first and second A / D
It is provided to a Q-axis side circuit portion having the same configuration as the I-axis side circuit portion configured by the converters 90 and 91, the sampling signal generation source 92, and the delay circuit 97. Elements that make up the Q-axis side circuit portion are indicated by adding dashes to the reference numbers on the I-axis side. 93 is a first and a second on both the I-axis side and the Q-axis side.
Is a computing unit for extracting a desired reception channel signal from digital output data of the A / D converters 90, 90 ', 91, 91'. The two low-pass filters 86,
Instead of providing 87, a single low-pass filter (eg, low-pass filter 86) is replaced by two A / D converters 90,
The output of the low-pass filter can be connected to the inputs of the A / D converters 90 and 91 so as to be shared with the A / D converter 91.

Next, the operating principle and operation of the twenty-third embodiment will be described. In FIG. 34, antenna 1
After passing through the reception bandpass filter 96 to form a target in-band signal group, the quadrature demodulator 11 extracts an I-axis component and a Q-axis component. The I-axis component signal is supplied to the first and second low-pass filters 86 and 87.
After the unnecessary frequency components in the high frequency band are removed by the above, the signals are input to the first and second A / D converters 90 and 91. In the A / D conversion operation in the A / D converters 90 and 91, the sampling signal from the sampling signal generation source 92 is
The signal is supplied to the first A / D converter 90 as it is, and is supplied to the second A / D converter 91 after being subjected to a frequency offset process to perform a sampling operation. Similar sampling is performed for the Q-axis component. And
The digital data obtained through this sampling operation is sent to a computing unit 93 where digital signal processing is performed, and a baseband output is obtained.

FIG. 35 is a diagram for explaining an example of orthogonal sampling in the case of A / D conversion of two orthogonal signals in the twenty-third embodiment. The configuration shown in FIG. FIG. 9 shows the configuration of the I-axis side circuit portion from the bandpass filter 96 to the first and second A / D converters 90 and 91 while clarifying signals flowing in each portion. Illustration is omitted. FIG.
5, Ts1 represents a sampling period.

In this embodiment, since the frequency conversion includes the offset frequency ωo, the output signal has a residual offset ωo. In this state, as described in the twenty-second embodiment, a signal band of a spectrum having a transmission speed ωo using the offset frequency ωo as a carrier is created. At this time, Shannon's secondary sampling theorem states that the information amount of the original signal can be sampled by adding a pulse train having a sampling frequency equal to or greater than the signal bandwidth and delaying τ. Therefore, when the roll-off rate is 0.5 or less, the frequency bandwidth of the signal fb (t) is about 3ωo, so that the sampling frequency can be set to 3ωo. The delay time τ may be any value other than the phase π of the signal fb (t) as described above. In particular, if τ = π / 2, the output can form an IQ orthogonal plane.

As described above, since the signal f (t) is sampled as a point on the IQ orthogonal plane, information such as the rotation direction of the signal can be secured, and the continuity of the frequency axis can be preserved and digitized. Therefore, the digital signal output of the receiving circuit can be subjected to either positive or negative frequency conversion by digital signal processing. That is,
By performing the digital frequency conversion of minus 2ωo, the signal fI (ωot) and fQ (ωot)
(−ωot) and fQ (−ωot) can be obtained. As a result, according to the above method, only one dual frequency converter using the complementary local oscillation frequency is required, and the high-frequency circuit can be simplified to about half and the power consumption can be reduced. It is needless to say that it is equivalent to use an A / D converter as one unit and supply sampling pulses in an integrated manner. That is, in the example of FIG. 25, the first A / D converter 90 and the second A / D converter 91
Are one A / D converter, and the first A / D converter 90
, And a sampling pulse generated by the delay pulse train of the second A / D converter 91 from a common sampling input unit of one A / D converter, and two digital output data output units are provided. It is also possible to configure a receiving circuit in which the output of digital output data by a sampling pulse that is not delayed and the output of digital output data by a delayed sampling pulse are provided separately.

(Twenty-fourth Embodiment) FIGS. 36 and 37 are diagrams illustrating a configuration and an operation principle of a receiving circuit according to a twenty-fourth embodiment of the present invention. The twenty-fourth embodiment is also based on the same idea as in the eighteenth and twenty-third embodiments, and reduces the number of quadrature demodulators to one to achieve power reduction and simplification of the device. It is assumed that. However, a plurality of (two or more) A / D converters are provided, and by performing secondary sampling in these A / D converters, aliasing on the frequency axis is prevented.
The configuration is such that a frequency conversion output based on the complementary local oscillation frequency of the originally required missing side is generated from the D conversion output by digital signal processing.

FIG. 36 is a block diagram showing a configuration of the receiving circuit according to the twenty-fourth embodiment of the present invention. 36, reference numeral 1 denotes an antenna for receiving a received signal, 9 denotes a reception bandpass filter which is a bandpass filter for shaping the waveform of the received signal in a predetermined frequency band, 11 denotes a quadrature demodulator which receives the received signal, and 4 denotes a local frequency signal. The generating circuit 86 is a quadrature demodulator 1
The first low-pass filters 87a to 87m for cutting the high-frequency band of one output signal (I) from 1 are used to cut the high-frequency band of the one output signal (I) from the quadrature demodulator 11, which will be described later. A plurality of second and subsequent low-pass filters provided in accordance with the number of the second and subsequent A / D converters, and 90 outputs the output of the first low-pass filter 86 to the A / D converter.
A first A / D converter for converting, 91a to 91m, a plurality of second and subsequent A / D converters provided to A / D convert the outputs of the second and subsequent low-pass filters 87a to 87m, 9
2 are the first and second and subsequent A / D converters 90, 9
A sampling signal generation source having a function of generating a clock having a frequency equal to or greater than the bandwidth of the received signal in 1a to 91m and providing the clock as a sampling pulse;
Reference numeral 97m denotes a plurality of delay circuits provided so as to offset the sampling clock signal from the sampling signal generation source 92 and input the offset to the second and subsequent A / D converters 91a to 91m. In FIG. 36 as well, one output (I) of the quadrature demodulator 11 is supplied to the I-axis side circuit portion, and the other output signal (Q) is supplied to the same I-axis side circuit portion as in FIG. It is supplied to the Q-axis side circuit portion 105. 93
Are the first and second and subsequent A / D converters 90 and 91a.
An arithmetic unit for extracting a desired reception channel signal from the digital output data of .about.91 m. In this embodiment, the second and subsequent A / D converters 91a to 91m
Is m. The same applies to other low-pass filters 87 and delay circuits 97.

Next, the operating principle and operation of the twenty-fourth embodiment will be described. In FIG. 36, antenna 1
After passing through the reception bandpass filter 96 to form a target in-band signal group, the quadrature demodulator 11 extracts an I-axis component and a Q-axis component. The I-axis component signal is supplied to the first and second and subsequent low-pass filters 86,
After removing unnecessary high frequency components at 87a-87m, the first and second and subsequent A / D converters 90, 91a-
Input to 91m. A / D converters 90, 91a to 91
m, the sampling signal from the sampling signal source 92 is supplied to the first A / D converter.
The signal is supplied as it is to the D converter 90, and is supplied to the plurality of second and subsequent A / D converters 91a to 91m after being subjected to the frequency offset processing by the corresponding delay circuits 97a to 97m, and then supplied for sampling. Perform the operation.
Similar sampling is performed for the Q-axis component.
Then, the digital data on the I-axis side and the Q-axis side obtained through this sampling operation are sent to the arithmetic unit 93, where digital signal processing is performed, and a baseband output is obtained.

FIG. 37 is a diagram for explaining an example of orthogonal sampling in the case where A / D conversion is performed on two orthogonal signals in the twenty-fourth embodiment. The configuration shown in FIG. 37 is the same as that shown in FIG. The first and second and subsequent A / D converters 90 and 91 in the I-axis side circuit portion below the reception bandpass filter 96
1A to 91 m are shown while clarifying signals flowing in each part. In FIG. 37, Ts1 represents a sampling cycle.

In this embodiment, the (m + 1) -th sampling is performed by (m + 1) A / D converters having different delay times. Therefore, a high-frequency circuit can be simplified for a signal in the case where digital modulation is multiplexed and transmitted. As a result, according to the above method, a dual frequency converter using a complementary local oscillation frequency can cope with a complicatedly multiplexed digital modulation signal with only one of them. Power consumption can be reduced. It is needless to say that it is equivalent to use an A / D converter as one unit and supply sampling pulses in an integrated manner.

(Embodiment 25) FIG. 38 shows a second embodiment of the present invention.
FIG. 21 is a block diagram illustrating a configuration of a receiving circuit according to a fifth embodiment. 38, reference numeral 1 denotes an antenna, 81 denotes a reception input circuit that receives a reception signal received from the antenna 1,
88 is a gain control (AGC) circuit for adjusting the gain of the received signal, 90 is a first A / D converter for A / D converting an output signal from the gain control circuit 88, and 91 is a frequency converter. A second A / D converter, which receives the output signal from 84 as a signal of a different system from the first A / D converter 90 and A / D converts the signal;
Reference numeral 2 denotes a function of generating a clock having a frequency equal to or higher than the bandwidth corresponding to the bandwidth of the received signal to the first and second A / D converters 90 and 91, a function of adding a delay pulse train to a sampling clock pulse train, and a function of sampling. A clock pulse train and a delay pulse train are connected to the first and second A / Ds.
A sampling signal generation source 93 having a function of providing as a sampling pulse of the converters 90 and 91, and extracts a desired reception channel signal from the digital output data of the first and second A / D converters 90 and 91. It is an arithmetic unit. The reception input section 81 includes an amplification circuit 94 and a bandpass filter (reception band) 96. Also,
A phase shifter 99 is provided between the gain control circuit 88 and the second A / D converter 91.

Next, the operation principle and operation of the twenty-fifth embodiment will be described. The signal group received from the antenna 1 is converted into a signal only in the communication channel band by the reception input circuit 81 including the reception band filter 96. This signal is gain-adjusted by the gain control circuit 88 to become a signal of a predetermined level, and is supplied to the first A / D converter 90. Here, n of the frequency ωo is supplied from the sampling signal generation source 92.
A sampling pulse is obtained by combining a pulse group having a double frequency (n is an integer number) with a pulse group having the same frequency delayed. As a result, the received signal becomes the first
A / D converter 90 obtains a secondary sampling operation, converts the data into data centering on a desired channel signal, and supplies the data to a computing unit 93.

The received signal whose gain has been adjusted to a signal of a predetermined level by the gain control circuit 88 is subjected to the phase shift processing operation by the phase shifter 99 through a signal line of another system, and the second A
/ D converter 91. Here, a sampling pulse is obtained from the sampling signal generation source 92 by a pulse group in which a pulse group having a frequency n (n is an integer) times the frequency ωo and a pulse group having the same frequency delayed are combined. As a result, the second A / D converter 91 obtains the secondary sampling function, converts the data into data centering on the desired channel signal, and supplies the data to the arithmetic unit 93. The arithmetic unit 93 generates information when frequency conversion is performed at the frequency ωc−ωo from both data and performs a correlation operation to extract a desired signal as a common wave.

FIG. 39 shows an example of the operation of the sampling signal generation source 92 in the twenty-fifth embodiment in which the configuration shown in FIG. 38 is replaced with one A / D converter (for example, 90) and a sampling signal. FIG. 4 is a schematic block diagram showing a simplified portion other than a source 92 and a computing unit 93. In the example of FIG. 39, a pulse group having a frequency n times the frequency ωo (n is an integer) is generated from the sampling signal generation source 92, and the delay circuit performs a delay operation of τ time on ωo to perform the sampling clock. Add to pulse train from generator.

FIG. 40 is a circuit diagram of the first A / D converter 9 shown in FIG. 38 for explaining another example of the operation of the sampling signal generation source 92 in the twenty-fifth embodiment.
FIG. 2 is a schematic block diagram showing a simplified portion other than a reference numeral 0, a sampling signal source 92, and a computing unit 93. FIG.
In the example of 0, the frequency ω
A pulse group having a frequency n times n (n is an integer) is generated, and the delay circuit performs a delay operation of π / 2 hours with respect to ωo, and adds a pulse train from the sampling clock generator and a delay pulse train. The delay pulse train from the circuit to be used is defined as a phase difference time corresponding to π / 2 of the frequency of the desired channel signal.

FIG. 41 is a circuit diagram of the first A / D converter 9 shown in FIG. 38 for explaining another example of the operation of the sampling signal generation source 92 in the twenty-fifth embodiment.
FIG. 2 is a schematic block diagram showing a simplified portion other than a reference numeral 0, a sampling signal source 92, and a computing unit 93. FIG.
In the example of FIG. 1, the frequency ω
A pulse group having a frequency n times as large as n (n is an integer) is generated, and the delay circuit performs a delay operation of π / 2 time with respect to ωo a plurality of times to obtain a pulse train from the sampling clock generator and a delay pulse train. And a plurality of delay pulses having a phase difference time corresponding to π / 2 of the frequency of the desired channel signal.

As described above, according to the present embodiment, the frequency based on the bandwidth, not the carrier frequency of the received signal, is A / A
By setting the sampling clock frequency of the D converter,
Even if the sampling frequency component leaks into the air, it does not disturb the communication and the received signal input circuit 8
Leakage can be easily prevented by the reception band filter 96 incorporated in the first embodiment. Further, since the sampling frequency is much lower than the carrier frequency, it is clear that the frequency dominating the power consumption of the circuit may be lower. In addition, since the analog frequency conversion circuit does not exist at all in the receiving circuit, no active element or filter element relating to this is required. All of the A / D converters 90 and 91 and the subsequent digital signal processing circuits can be integrated and miniaturized, and the effect of reducing power consumption due to small wiring requirements inside the integrated circuit is large. is there. As described above, the present embodiment can reduce the power of the receiving system, simplify the receiving circuit, and reduce the power consumption without causing communication interference due to leakage of the local oscillation frequency.

(Twenty-Sixth Embodiment) Next, a twenty-sixth embodiment of the present invention will be described. Various improvements have been made to reduce the high-frequency circuit portion and the power consumption of the receiving circuit of the mobile communication device so far, but none of the improvements have been decisive. Here, FIG. 42 shows an overview of the frequency arrangement of the Japanese standard digital car telephone system. In FIG. 42, for example, 810 MHz to 826 MHz of PDC, which is an example of a Japanese standard, includes 640 waves. That is, 120 at 25 KHz
0 channels are arranged. It is extremely wasteful to directly sample in this frequency band. This is because the bandwidth of the channel in which the transmission information is accommodated is 23 KH
z and the amount of information is small. Therefore, the received radio band signal is directly converted to its carrier frequency band of 800 MHz.
If z is sampled for the other party, it is a calculation that requires sampling of several GHz (gigahertz), but the information amount is only 25 KHz, and most of the sampling data is redundant.

The receiving apparatus according to the present embodiment realizes a method of directly adding a received signal to an A / D converter, and enables elimination of a frequency converter.

According to Shannon's sampling theorem, when considering the maximum value of the time interval of the samples necessary for defining an arbitrary time function f (t) in the case of an equal sample, it is expressed by the following equation. This is a well-known oversampling theorem.

[0237]

[Equation 63]

Here, the frequency W is the upper limit of the frequency component included in the time function f (t), that is, 826 MHz in this case.
z. Therefore, the sampling rate is 826 MH
The value is several giga S / s which is twice or more of z. here,
Consider the case where the spectrum is limited from f1 to f2. In this case, the equation using Shannon's quadratic sampling theorem is as follows.

[0239]

[Equation 64] This equation shows that the original signal f (t) can be completely expressed if the values of f (t) and fq (t) are sampled at every sampling interval T = 1 / (f2-f1). Therefore, when f2-f1 = W (Hz), the sampling time interval is 1 / W and f
(T) and fq (t) may be sampled alternately. That is, if the bandwidth of the filter provided in the reception input circuit is 25 kHz, it can be dealt with at a sampling rate of 25 kHz. Since the filter actually provided in the reception input circuit is designed so as to include all adjacent channels, the bandwidth is 826 (MHz) −810 (MHz) = 16 (MHz), that is, the 16 MHz width, and the sampling speed is 15MS /
s. FIG. 43 shows the arrangement of the received signals. FIG. 43 is a schematic view of the channel arrangement of the Japanese standard digital car telephone system.

FIG. 44 is a block diagram showing a configuration of a receiving circuit according to the twenty-sixth embodiment of the present invention. 44, reference numeral 1 denotes an antenna, 81 denotes a reception input circuit that receives a reception signal received from the antenna 1, 88 denotes a gain control circuit that performs gain adjustment on the reception signal, and 90 denotes an output signal from the gain control circuit 88. An A / D converter 92 for performing A / D conversion includes a sampling clock generator 92a for generating a clock having a frequency equal to or higher than the bandwidth of the received signal to the A / D converter 90, and a delay pulse train for the sampling clock pulse train. Delay pulse adding section 92 to be added
b and a pulse adder 92 c for providing a sampling clock pulse train and a delayed pulse train as sampling pulses of the A / D converter 90. This is an arithmetic unit for extracting a desired reception channel signal. The reception input unit 81 includes an amplification circuit 94 and a reception bandpass filter 96.

Next, the operating principle and operation of the twenty-sixth embodiment will be described. The signal group received from the antenna 1 is converted into a signal only in the communication channel band by the reception input circuit 81 including the reception band filter 96. This signal is gain-adjusted by the gain control circuit 88 to become a signal of a predetermined level, and is supplied to the A / D converter 90. here,
From the sampling signal source 92, a sampling pulse is obtained by combining a pulse group having a frequency n times the frequency fo (n is an integer) and a delayed pulse group having the same frequency. As a result, the received signal is converted into data centering on the desired channel signal by the A / D converter 90 by obtaining a secondary sampling operation, and is supplied to the calculator 93. Based on this data, the arithmetic unit 93 calculates the frequency
Generates information when frequency conversion is performed by c-fo, performs correlation calculation, and sets the desired signal as a common wave to the BP
Extract the SK signal.

As described above, according to the present embodiment, a desired wave channel can be received without using a frequency converter in a communication system having a digital modulation system of the BPSK system having a plurality of channels. A receiving circuit capable of reducing power and simplifying a circuit can be realized. In the twenty-sixth embodiment, one A / D converter 90 is used to perform A / D conversion processing. May be supplied separately to obtain a digital signal output and then combined.

(Embodiment 27) FIG. 45 shows a second embodiment of the present invention.
FIG. 21 is a block diagram illustrating a configuration of a receiving circuit according to a seventh embodiment. In FIG. 45, reference numeral 1 denotes an antenna, 81 denotes a reception input circuit that receives a reception signal received from the antenna 1,
88 is a gain control circuit for adjusting the gain of the received signal, 90 is a first A / D converter for A / D converting an output signal from the gain control circuit 88, and 91 is an output from the second gain control circuit 88. A second signal which receives a signal as a signal of a different system from the first A / D converter 90 and A / D-converts the signal.
A / D converter 92 has the first and second A / D converters.
Sampling clock generator 9 for generating a clock having a frequency equal to or higher than the bandwidth of the received signal to converter 90
2a, a delay pulse adding unit 92b for adding a delay pulse train to the sampling clock pulse train, and the A / D converter 9
Pulse adder 9 that provides 0 sampling pulses
2c, and 93 is a sampling signal source having the A
An arithmetic unit 99 for extracting a desired reception channel signal from the digital output data of the / D converter 90 receives the output of the gain control circuit 88, performs a phase shift process, and converts the obtained signal into a second A signal. This is a phase shifter to be sent to the / D converter 92. The reception input unit 81 includes an amplification circuit 94 and a reception bandpass filter 96.

Next, the operation principle and operation of the twenty-seventh embodiment will be described. The signal group received from the antenna 1 is converted into a signal only in the communication channel band by the reception input circuit 81 including the reception band filter 96. This signal is gain-adjusted by the gain control circuit 88 to become a signal of a predetermined level. The output of the gain control circuit 88 is distributed to two systems. One system is input to the first A / D converter 90, and a clock pulse train having a frequency equal to or higher than the frequency corresponding to the bandwidth of the received signal, that is, a frequency (n) times n times the frequency fo
) Is received from the sampling signal generator 92, and sampling is controlled. The first A / D converter 90 generates a digital signal output exactly the same as that of the A / D converter in the twenty-sixth embodiment, and supplies the digital signal output to the arithmetic unit 93.

On the other hand, the output of gain control circuit 88 is distributed to another system (second system). The second system is connected to a phase shifter 99, where the received signal is given a phase change of 90 degrees. This phase-shifted signal is
A clock pulse train input to the second A / D converter 91 and having a frequency equal to or greater than the bandwidth of the received signal, that is, a pulse group having a frequency n times the frequency fo (n is an integer) and a delay are applied. Sampling pulses of the combined pulse group of the same frequency pulse group are received from the sampling signal generator 92 and sampling is controlled. Arithmetic unit 9
In step 3, information is generated when frequency conversion is performed at the frequency fc-fo, and a correlation operation is performed to extract a BPSK signal using the desired signal as a common wave. As a result, from the digital output of the second A / D converter 91, the BPSK signal extracted by the arithmetic unit 93 becomes the first A / D converter.
This is information having a phase difference of 90 degrees from the output of the D converter 90. These two types of information form a QPSK signal system. Therefore, it can be seen from the above that demodulation can be performed on a signal of the QPSK communication system.

As described above, according to the present embodiment, a desired wave channel can be received without using a frequency converter in a communication system having a QPSK digital modulation system having a plurality of channels. A receiving circuit capable of reducing power and simplifying a circuit can be realized.

(Embodiment 28) FIG. 46 shows a second embodiment of the present invention.
FIG. 28 is a block diagram illustrating a configuration of a receiving circuit according to an eighth embodiment. This embodiment is in addition to the local frequency complementary offset type direct frequency conversion system which forms the basis of the present invention, and realizes a space diversity function by a receiving circuit based on a single direct quadrature detection circuit. FIG.
In the figure, reference numeral 1 denotes an antenna, which comprises a plurality of antennas, a first antenna 1a and a second antenna 1b. 81 is a first which receives a first reception signal received from the first antenna 1a.
Is a second reception input circuit for receiving a second reception signal received from the second antenna 1b, and 83 is a reception input circuit for inputting a reception signal from the first reception input circuit 81 to perform frequency conversion. A first frequency converter 84 for performing a frequency conversion by inputting a reception signal from the second reception input circuit 82; and 85 a first and second frequency converter 83, 84 for performing the frequency conversion. , A local oscillator that provides an output at a frequency obtained by applying a frequency offset of a half of a channel spacing frequency to a desired wave carrier frequency, and a local oscillator 86 that cuts a high frequency band of an output signal of the first frequency converter 83. 1 is a low-pass filter, and 87 is a second frequency converter 8
4, a second low-pass filter for cutting the high-frequency band of the output signal; 88, a first gain control (AGC: automatic gain control) circuit for adjusting the gain of the first received signal; 89, a second gain signal; A second gain control circuit that performs gain adjustment, 90 is a first A / D converter that performs A / D conversion of an output signal from the first frequency converter 83, and 91 is a second A / D converter that is output from the second frequency converter 84. A second A / D converter for A / D converting the output signal, 92
And a function of generating a clock having a frequency equal to or higher than the bandwidth of the received signal to the second A / D converters 90 and 91, a function of adding a delay pulse train to the sampling clock pulse train, a sampling clock pulse train and a delay pulse train And the first and second A / D converters 90, 9
A sampling source 93 having a function of providing as one sampling pulse;
This is an arithmetic unit for extracting a desired reception channel signal from digital output data of the D converters 90 and 91. The first and second reception input sections 81 are provided with amplification circuits 94 and 9 respectively.
5 and reception band filter (band-pass filter) 9
6, 97.

Next, the operation principle and operation of the twenty-eighth embodiment will be described. The signal group received from the first antenna 1a is converted into a signal only in the communication channel band by the reception band filter 96, and the frequency is converted by the first frequency converter 83 at the local oscillation frequency fc + fo to which the offset has been added. This local oscillation frequency is equal to the local oscillator 8
Supplied from 5. As a result, the output of the frequency 2fc + fo and the output of the frequency -fo are supplied to the first low-pass filter 86, but the signal of the frequency -fo is extracted by the low-pass characteristic. This signal is converted into a signal of a predetermined level by the first gain control circuit 88, and the first A / D converter 90
Supplied to Here, a sampling pulse is obtained from the sampling source 92 by a pulse group in which a pulse group having a frequency n times the frequency fo (n is an integer) and a delayed pulse group having the same frequency are combined. As a result, the first A / D converter 90 obtains the secondary sampling effect and converts the data into data centering on the desired channel signal.
Supplied to

A signal group received from the second antenna 1b becomes a signal only in the communication channel band by the reception bandpass filter 97, and is frequency-converted by the second frequency converter 84 at the local oscillation frequency fc + fo to which the offset has been added. . This local oscillation frequency is supplied from the local oscillator 85. As a result, the output of the frequency 2fc + fo and the output of the frequency -fo are supplied to the second low-pass filter 87, but the signal of the frequency -fo is extracted by the low-pass characteristic.
This signal becomes a signal of a predetermined level by the second gain control circuit 89 and is supplied to the second A / D converter 91.
Here, a sampling pulse is obtained from the sampling source 92 by a pulse group in which a pulse group having a frequency n times the frequency fo (n is an integer) and a delayed pulse group having the same frequency are combined. Thereby, the second A / D converter 9
1 is converted into data centering on a desired channel signal by obtaining a secondary sampling operation, and is supplied to a computing unit 93.
In the arithmetic unit 93, the frequency fc−
It generates information when frequency conversion is performed by fo and performs a correlation operation to extract a desired signal as a common wave.

(Embodiment 29) FIG. 47 shows a second embodiment of the present invention.
FIG. 39 is a block diagram illustrating a configuration of a receiving circuit according to a ninth embodiment. The receiving circuit according to this embodiment includes the second
Since the receiving apparatus according to the eighth embodiment has almost the same configuration as the receiving apparatus according to the eighth embodiment, the same parts are denoted by the same reference numerals and detailed description thereof will be omitted. In the twenty-ninth embodiment, two local oscillators are provided. One local oscillator 85a is the same as the local oscillator 85 of the twenty-eighth embodiment, and the local oscillator 85a is connected to the first frequency converter 83 and supplies the local oscillator frequency fc + fo to the frequency converter 83. . The other local oscillator 85
b is connected to the second frequency converter 84 to supply the local frequency fc-fo to the frequency converter 84.

Next, the operating principle and operation of the twenty-ninth embodiment will be described. The signal group received from the first antenna 1a is converted into a signal only in the communication channel band by the reception band filter 96, and the frequency is converted by the first frequency converter 83 at the local oscillation frequency fc + fo to which the offset has been added. This local oscillation frequency is equal to the local oscillator 8
5a. As a result, the output of the frequency 2fc + fo and the output of the frequency -fo are supplied to the first low-pass filter 86, but the signal of the frequency -fo is extracted by the low-pass characteristic. This signal is converted into a signal of a predetermined level by the first gain control circuit 88, and the first A / D converter 9
0 is supplied. Here, a pulse group having a frequency n times the frequency fo (n is an integer) from the sampling source 92;
A sampling pulse is obtained by combining the delayed pulse groups of the same frequency. Thereby, the first
A / D converter 90 obtains the secondary sampling function and converts the data into data centering on the desired channel signal.
3 is supplied.

A signal group received from the first antenna 1b is converted into a signal only in the communication channel band by the reception bandpass filter 97, and the signal is converted by the second frequency converter 84 at the local oscillation frequency fc-fo to which the offset is added. Is done. This local oscillation frequency is supplied from the local oscillator 85. As a result, the output of the frequency 2fc-fo and the frequency fo is supplied to the second low-pass filter 87, but the signal of the frequency fo is extracted by the low-pass characteristic. This signal becomes a signal of a predetermined level by the second gain control circuit 89 and is supplied to the second A / D converter 91. Here, a sampling pulse is obtained from the sampling source 92 by a pulse group in which a pulse group having a frequency n times the frequency fo (n is an integer) and a delayed pulse group having the same frequency are combined. As a result, the second A / D converter 91 obtains the secondary sampling function, converts the data into data centering on the desired channel signal, and supplies the data to the arithmetic unit 93. In the arithmetic unit 93, the frequency fc−fo is obtained from both data.
, Generate information when frequency conversion is performed and perform a correlation operation to extract a desired signal as a common wave.

(Embodiment 30) FIG. 48 shows a third embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a receiving circuit according to an embodiment of the present invention. The receiving circuit according to this embodiment includes the second
It has basically the same configuration as the receiving devices according to the eighth and twenty-ninth embodiments, and further simplifies the configuration.
Therefore, the same portions as those of the above-described two embodiments are denoted by the same reference numerals, and the configuration will be simply described.

In FIG. 48, reference numeral 1 denotes an antenna, which comprises a plurality of antennas, a first antenna 1a and a second antenna 1b. 81 is a first reception input circuit that receives a first reception signal received from the first antenna 1a, 82 is a second reception input circuit that receives a second reception signal received from the second antenna 1b, 88 is a first gain control circuit that performs gain adjustment on the first received signal, 89 is a second gain control circuit that performs gain adjustment on the second received signal, and 90 is an output from the first gain control circuit 88 A first A / D converter for A / D converting a signal, 91 is a second gain control circuit 89
A second A / D converter for A / D converting the output signal from
92 is a first and second A / D converter 90, 91
A function of supplying a clock having a frequency equal to or higher than the bandwidth of the received signal, a function of adding a delay pulse train to the sampling clock pulse train, and A sampling source 93 having a function of providing as a sampling pulse of the D converters 90 and 91 extracts a desired reception channel signal from digital output data of the first and second A / D converters 90 and 91. It is an arithmetic unit. The first and second reception input sections 81 include amplification circuits 94 and 95, reception bandpass filters 96,
97.

Next, the operation principle and operation of the thirtieth embodiment will be described. A signal group received from the first antenna 1a is converted into a signal of only the communication channel band by the reception bandpass filter 96, and this signal is converted into a signal of a predetermined level by the first gain control circuit 88.
It is supplied to a converter 90. Here, a sampling pulse is obtained from the sampling source 92 by a pulse group in which a pulse group having a frequency n times the frequency fo (n is an integer) and a delayed pulse group having the same frequency are combined. As a result, the first A / D converter 90 obtains the secondary sampling function and converts the data into data centering on the desired channel signal.
It is supplied to a computing unit 93.

The signal group received from the second antenna 1b is converted into a signal of only the communication channel band by the reception bandpass filter 97, and this signal is converted into a signal of a predetermined level by the second gain control circuit 89. The signal is supplied to the A / D converter 91. Here, a sampling pulse is obtained from the sampling source 92 by a pulse group in which a pulse group having a frequency n times the frequency fo (n is an integer) and a delayed pulse group having the same frequency are combined. Thereby, the second A /
The D converter 91 obtains the secondary sampling function, converts the data into data centering on the desired channel signal, and supplies the data to the calculator 93. The arithmetic unit 93 generates information when frequency conversion is performed at the frequency fc-fo from both data and performs a correlation operation to extract a desired signal as a common wave.

As described above, according to the present embodiment, it is possible to realize a space diversity function in addition to the local frequency complementary offset type frequency conversion system which is the basis of the present invention.

[0258]

As is apparent from the above embodiments, the present invention performs direct frequency conversion using a frequency in a valley between channels of a communication system as a local frequency of a receiver and outputs an output signal thereof. Since it is possible to prevent the resulting frequency offset and mixing of signals of adjacent channels from being mixed, it is possible to reduce the power of the receiving system, simplify the circuit, and reduce the power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a receiving circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a receiving circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a receiving circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a receiving circuit according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a receiving circuit according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a receiving circuit according to a sixth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a receiving circuit according to a seventh embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a receiving circuit according to an eighth embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a receiving circuit according to a ninth embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a receiving circuit according to a tenth embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a receiving circuit according to an eleventh embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a receiving circuit according to a twelfth embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a receiving circuit according to a thirteenth embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a receiving circuit according to a fourteenth embodiment of the present invention.

FIG. 15 is a conceptual diagram of a transformer according to a fourteenth embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of a receiving circuit according to a fifteenth embodiment of the present invention.

FIG. 17 is a block diagram showing a configuration of a receiving circuit according to a fifteenth embodiment of the present invention.

FIG. 18 is a block diagram showing a configuration of a receiving circuit according to a sixteenth embodiment of the present invention.

FIG. 19 is a block diagram showing a configuration of a receiving circuit according to a seventeenth embodiment of the present invention.

FIG. 20 is a schematic diagram for explaining a local frequency setting method in each embodiment of the present invention.

FIG. 21 is a block diagram showing a configuration of a receiving circuit according to an eighteenth embodiment of the present invention.

FIG. 22 is a block diagram showing a configuration of a receiving circuit according to a nineteenth embodiment of the present invention.

FIG. 23 is a block diagram showing a configuration of a receiving circuit according to a twentieth embodiment of the present invention.

FIG. 24 is a block diagram showing a configuration of a receiving circuit according to a twenty-first embodiment of the present invention.

FIG. 25 is a conceptual diagram of a transformer according to a twenty-second embodiment of the present invention.

FIG. 26 shows A / D in a twenty-second embodiment of the present invention.
Diagram illustrating how aliases occur as a result of sampling by a converter

FIG. 27 is a diagram showing a state of a reception channel in the multi-channel communication system used in the present invention.

FIG. 28 is a diagram showing an A / D conversion output having a negative frequency range which appears in the twenty-second embodiment of the present invention.

FIG. 29 shows π / 2 in the twenty-second embodiment of the present invention.
Diagram showing a method of decomposing signal components into orthogonal components using cosine and sine functions using the phase difference of

FIG. 30 is a diagram illustrating an example of a quadrature sampling operation when performing A / D conversion on two orthogonal signals according to the twenty-second embodiment of the present invention;

FIG. 31 is a diagram in a case where an offset is considered in the explanatory diagram of orthogonal sampling in FIG. 30;

32 and FIG. 31 in a case where two orthogonal signals are subjected to A / D conversion in the twenty-second embodiment of the present invention.
The figure which shows an example of another orthogonal sampling operation different from

FIG. 33 is a view showing a state of FIG. 32 according to a twenty-second embodiment of the present invention;
The figure which shows the sampling pulse obtained when performing the orthogonal sampling operation shown in.

FIG. 34 is a block diagram showing a configuration of a receiving circuit according to a twenty-third embodiment of the present invention.

FIG. 35 is a diagram showing an example of a quadrature sampling operation in the case where A / D conversion is performed on two orthogonal signals in the twenty-third embodiment of the present invention;

FIG. 36 is a block diagram showing a configuration of a receiving circuit according to a twenty-fourth embodiment of the present invention.

FIG. 37 is a diagram illustrating an example of a quadrature sampling operation when performing A / D conversion on two orthogonal signals according to the twenty-fourth embodiment of the present invention;

FIG. 38 is a block diagram showing a configuration of a receiving circuit according to a twenty-fifth embodiment of the present invention.

FIG. 39 is a simplified block diagram for explaining one operation of a sampling signal generation source part according to a twenty-fifth embodiment of the present invention;

FIG. 40 is a simplified block diagram for explaining another operation of the sampling signal source portion in the twenty-fifth embodiment of the present invention.

FIG. 41 is a simplified block diagram for explaining still another operation of the sampling signal source portion in the twenty-fifth embodiment of the present invention;

FIG. 42 is an overview of the frequency arrangement of a Japanese standard digital car telephone system used for describing the twenty-sixth embodiment of the present invention.

FIG. 43 is a schematic view of a channel arrangement of the Japanese standard digital car telephone system shown in FIG. 42;

FIG. 44 is a block diagram showing a configuration of a receiving circuit according to a twenty-sixth embodiment of the present invention.

FIG. 45 is a block diagram showing a configuration of a receiving circuit according to a twenty-seventh embodiment of the present invention.

FIG. 46 is a block diagram showing a configuration of a receiving circuit according to a twenty-eighth embodiment of the present invention.

FIG. 47 is a block diagram showing a configuration of a receiving circuit according to a twenty-ninth embodiment of the present invention.

FIG. 48 is a block diagram showing a configuration of a receiving circuit according to a thirtieth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Antenna 2, 3 Frequency conversion circuit 4 Local frequency signal generation circuit 5 Common wave extraction circuit 6 Frequency offset circuit 7 Offset frequency generation circuit 8 Filter 9A, 9B Bandpass filter 10A, 10B A / D converter 11, 12 Quadrature demodulation circuit DESCRIPTION OF SYMBOLS 13 Correlator 14 Filter 15 2nd frequency conversion circuit 16 Digital frequency conversion circuit 17 Digital frequency generation circuit 20 Reception input part 21, 22 Input line 23, 24 Integration circuit 25, 26, 30 Buffer amplifier 27, 28 Transformer 29 Connection point 41, 42 Non-common signal detection circuit 43 Balance monitoring circuit 44, 45 Synthesis circuit 46, 47 Non-common signal removal circuit

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Fujio Sasaki 4-3-1 Tsunashimahigashi, Kohoku-ku, Yokohama-shi, Kanagawa F-term (reference) in Matsushita Communication Industrial Co., Ltd. 5K004 AA01 AA05 AA08 BA02 FG02 FK09 JG01

Claims (10)

[Claims] 1. A reception input means for receiving a reception signal from an antenna, a quadrature demodulator for performing frequency conversion processing on a reception signal from the reception input means to obtain two outputs having different phases, and the quadrature demodulator And a second A / D converter for inputting one of the output signals from the A / D converter and converting an analog signal into a digital signal, and the first and second A / D converters
A first sampling clock generator for generating a clock of twice or more the frequency corresponding to the bandwidth of the received signal to the converter, and a first delay pulse train added to the pulse train from the first sampling clock generator A first delay circuit, a means for providing a pulse train from the first sampling clock generator and the first delay pulse train as sampling pulses for the first and second A / D converters, Third and fourth A / D converters for inputting the other output signal from the quadrature demodulator and converting an analog signal into a digital signal; and the third and fourth A / D converters
A second sampling clock generator for generating a clock of twice or more the frequency corresponding to the bandwidth of the received signal to the converter, and a second delay by delaying a pulse train from the second sampling clock generator A second delay circuit for generating a pulse train, and means for providing a pulse train from the second sampling clock generator and the second delay pulse train as sampling pulses for the third and fourth A / D converters And a means for extracting a quadrature component of a desired reception channel signal from digital output data of the first to fourth A / D converters. 2. The receiving circuit according to claim 1, wherein a delay time of each of said delay circuits is a delay time of a phase difference corresponding to π / 2 in relation to a frequency of said desired channel signal. 3. A reception input means for receiving a reception signal from an antenna, a quadrature demodulator for performing frequency conversion processing on a reception signal from the reception input means to obtain two outputs having different phases, and the quadrature demodulator And a second A / D converter for inputting one of the output signals from the A / D converter and converting an analog signal into a digital signal, and the first and second A / D converters
A first sampling clock generator for generating a clock having a frequency equal to or higher than a frequency corresponding to the bandwidth of the received signal to the converter; and a first for adding a first delay pulse train to the pulse train from the first sampling clock generator. And the pulse train from the first sampling clock generator and the first delayed pulse train are connected to the first and second delay circuits.
Means for providing as a sampling pulse of the A / D converter, and third and fourth A / D converters which receive the other output signal from the quadrature demodulator and convert an analog signal into a digital signal, A second sampling clock generator for generating a clock of twice or more the frequency corresponding to the bandwidth of the received signal to the third and fourth A / D converters; and a second sampling clock generator. To generate a second delayed pulse train by delaying the pulse train of
And the pulse train from the second sampling clock generator and the second delay pulse train are connected to the third
Means for providing a sampling pulse of the fourth A / D converter, and means for extracting a quadrature component of a desired reception channel signal from digital output data of the first to fourth A / D converters. Wherein the delay time of each of the delay circuits is a delay time other than the phase difference corresponding to π in relation to the frequency of the desired channel signal. 4. A reception input means for receiving a reception signal from an antenna, and a first input means for inputting the reception signal and performing A / D conversion.
A / D converter, a second A / D converter, and these A / D converters
A sampling clock generator for generating a clock having a frequency equal to or higher than a bandwidth corresponding to a bandwidth of a received signal to a / D converter, a circuit for adding a delayed pulse train to a pulse train from the sampling clock generator, and a sampling clock generator And a means for providing a pulse train and a delayed pulse train from the A / D converter as sampling pulses of the A / D converter, and a means for extracting a desired reception channel signal from digital output data of the A / D converter. Receiving circuit. 5. The delay time in the circuit for adding the delay pulse train is set to π in relation to the frequency of a desired channel signal.
5. The receiving circuit according to claim 4, wherein the phase difference time corresponds to / 2. 6. A delay means for generating a plurality of delay pulses, and wherein the delay time of the delay pulse is a delay time other than the phase difference corresponding to π, particularly in relation to the frequency of a desired channel signal. The receiving circuit according to claim 4, wherein 7. A reception input means for receiving a reception signal from an antenna, a single A / D converter for inputting the reception signal and performing A / D conversion, and the A / D converter has the reception signal. A sampling clock generator for generating a clock having a frequency equal to or higher than a bandwidth, a circuit for adding a delay pulse train to a pulse train from the sampling clock generator, and a circuit for adding a delay pulse train to a pulse train from the sampling clock generator And the pulse train from the sampling clock generator and the delayed pulse train
Means for providing as a sampling pulse of the D converter;
Means for extracting a desired reception channel signal from digital output data of the A / D converter. 8. A reception input means for receiving a reception signal from an antenna, a quadrature demodulator for performing frequency conversion processing on a reception signal from the reception input means to obtain two outputs having different phases, and the quadrature demodulator , And converts one analog signal into a digital signal by inputting one output signal from
/ D converter, a second A / D converter that receives another output signal from the quadrature demodulator and converts an analog signal into a digital signal, and the first and second A / D converters A sampling clock generator that supplies a clock having a frequency equal to or greater than the bandwidth of the received signal, a delay circuit that delays a pulse train from the sampling clock generator to generate a delayed pulse train, Means for providing both the pulse train of the first and second delay pulse trains as sampling pulses of the first and second A / D converters, and the first and second A / D converters.
Means for extracting a quadrature component of a desired reception channel signal from digital output data of the converter. 9. The receiving circuit according to claim 8, wherein a delay time of said delay circuit is a delay time of a phase difference corresponding to π / 2 in relation to a frequency of said desired channel signal. 10. A reception input means for receiving a reception signal from an antenna, a quadrature demodulator for performing frequency conversion processing on a reception signal from the reception input means to obtain two outputs having different phases, and the quadrature demodulator , A first A / D converter for converting an analog signal into a digital signal by inputting one of the output signals, and converting the analog signal into a digital signal by inputting another output signal from the quadrature demodulator. Second
An A / D converter, a sampling clock generator for supplying a clock having a frequency equal to or higher than a bandwidth corresponding to a bandwidth of a received signal to the first and second A / D converters, A delay circuit for delaying a pulse train to generate a delayed pulse train; and a means for providing both the pulse train from the sampling clock generator and the delayed pulse train as sampling pulses of the first and second A / D converters; The first and second A /
Means for extracting a quadrature component of a desired reception channel signal from digital output data of the D converter, wherein the delay time of the delay circuit is set to a value other than a phase difference corresponding to π in relation to the frequency of the desired channel signal. A receiving circuit having a delay time.