JP2002111718A - Route retrieval apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high speed process and reduce the time required to reform a tree structure when data (namely, route) is changed, although the tree structure database called a Patricia tree is formed when high speed processing is not particularly required, and software processing or its exclusive hardware has been proposed because it is difficult to quickly find out the data matching in the maximum degree with an destination address from many route data. SOLUTION: This route retrieval apparatus comprises a 3-level associative memory for storing a plurality of entry data, a storage means for storing a first data and its attribute data to each entry data, a matching identification means for searching and identifying an external input data and the entry data matching a first data region, and a maximum (or minimum) detecting means for detecting the maximum (or minimum) data of the attribute data by continuously searching for several times the attribute data of the matching entry data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a route search device, and more particularly to a high-speed search device for a network address route using an associative memory device.

[0002]

2. Description of the Related Art Communication data on the Internet is sent to a relay device called a router, a destination address written in the data is detected, a routing table for the address is searched, and the data of the data is searched. The destination is decided. This address consists of two areas: a network node number (network address) and a host number (host address) connected to the node.

The route table stores this network address (the host unit is all 0).
The router cannot know which part of the destination address corresponds to the network address. Therefore, as a rule for determining a route, it is defined that the destination address and the network address in the routing table that match the most will be the correct route.

[0004]

However, it is extremely difficult to find the one that matches the destination address at the highest speed from a large amount of route data. Conventionally, when a high speed is not required, a tree structure database called a Patricia tree is constructed, and software processing or its dedicated hardware has been proposed. However, it is difficult to achieve a sufficiently high speed. That is, there is a problem that much time is required to recreate the tree structure when the path is changed. In view of this problem, the present invention takes advantage of the characteristic that all data of the associative memory device and input data can be compared at once, and provides a high-speed route search device that does not change the data structure even when the route is changed. It is a suggestion.

[0005]

According to the present invention, there is provided a ternary associative memory device for storing a plurality of entry data, storage means for storing first data and its attribute data in each entry data, Match search and identification means for searching for the entry data that matches the input data of the previous entry and the first data area of the previous entry;
A maximum (or minimum) detecting means for detecting the route search.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a typical embodiment of the present invention, in a three-valued associative memory device for storing a plurality of entry data, the first data and its attribute data are separately stored in each entry data. Next, the input data from the outside and the first data area are searched and compared by the matching search identifying means, and the matching entry data is searched and identified.
A path search device that sequentially changes the search data for the attribute data of the matching entry data, searches a plurality of times, and detects the maximum (or minimum) thereof.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below. FIG. 5 is an example of a ternary associative memory device. The operation of detecting the coincidence of one entry will be described. Cell 6 of each memory
1 is wired-connected to the match search line 62. At the time of initial setting, the control signal line 65 becomes low,
The match line 62 is precharged via the MOS transistor 64. Of course, at this time, the search data lines BDa66 and BDb67 are also set to low, and the NMO
The S transistor is turned off, blocking the path for discharging the match line 62. An inverter 63 for detecting the node is formed at the end of the match line 62.

The inside of the cell 61 stores two data MDa and MDb, and is connected to one gate of two NMOS transistors serially connected to each match line 62. A search data line SDa66 (or search data line SDb67) is connected to the other gate. A plurality of entries configured as described above are arranged.

The cell data has three states of 0, 1 and * (don't care), and MDa and M
Db data is set as shown in FIG. FIG.
Is the search data SD and the search data line SDA6 during the search operation.
6 and the relationship between the search data line SDB67.

For example, 1 is stored as cell data,
Consider a case where the search data SD is 1 and the data match. As shown in FIG. 6, MDa is 1 and MDb is 0. On the other hand, from FIG. 7, when the search data SD is 1, the search data line SDa66 is 0 and the search data line SDb67 is 1. In this case, the NMOS 2 of the cell 61 (see FIG. 5)
One of the serial transistors is turned off, and the charge on the match line 62 is not discharged. That is, the bits match.

However, when the search data SD is 0 or the cell data is 0 (the internal data MDa is 0 and MDb is 1), the two serial transistors of the NMOS in the cell 61 are turned on, and the charge of the match line 62 is reduced. Discharged, inverter 6
3 outputs 1; that is, mismatch. This is performed over all cells in the entry, and if any one bit does not match, a mismatch is detected.

However, when the internal data is *, that is, when both MDa and MDb are 0, no charge is discharged in the cell (bit) regardless of the value of the search data. This is called a don't care bit. Also, the search data line is *,
That is, when masking that bit, the search data line S
Since both Da66 and search data line SDb67 become 0, similarly, there is no discharge of the match line 62 at that bit.

A first embodiment in which network addresses are stored in a ternary associative memory utilizing such characteristics is shown in FIG. Here, D5 to D0 correspond to the network address portion 1a, and the host portion of each entry is not filled with 0 but stored as * (that is, don't care bit). Also, from AD2 to AD0
Indicates the length of each network address other than the host part, and is referred to as attribute data 1b. For example,
Entry a) has a network address of 101000
And the length of the network address is 011 (that is, 1
In the case of a 0-base number, it becomes 3), and three bits from D5 to D3 are the length of the network address. Similarly, the length of the network address of entry b) is 2 bits from D5 to D4.

The entry data 1 and the search data 2 are compared, and the result is stored in the hit flag 3. The polarity of the hit flag in this case is opposite to that in FIG. All the entry data are searched at the same time as the search data 2, and the results of all the hit flags 3 are input to the attribute data search control device 4 by wired-OR connection.

First, a search corresponding to D5 to D0 of the entry data 1 is performed. At this time, for example, 10101
It is assumed that 0 is search data 2. Attribute data (AD2 to A
The search of D0) is performed by masking the search data. Then, a match occurs between the two entry data a) and b), which is input to the attribute data search control device 4. That is, there are two entries as network address candidates.

Next, in order to select the one having the longest network address length from these two, only the first bit (that is, AD2) of the attribute data is searched data 1, other AD1 to AD0 are masked, and D5 to D5 are masked. D0 is searched with the same value as the previous time. Then, both entry a) and b) are A
D2 is 0 and does not match. This mismatch information is input to the attribute data search control device 4, and the matching entry A
The value of D2 is found to be 0. Then, when AD2 is set to 0, the value of AD1 is set to 1, and AD0 is masked, a similar search is performed. This time, both entries match, and it is found that AD1 is 1. Further, AD2 is 0, AD1 is 1, A
When a similar search is performed with D0 set to 1, only entry a) matches the longest.

Eventually, the entry that matches the search data 101010 retrieved first first is a), and the matching address length is determined to be 011 (3 in decimal). The position of this entry is encoded and output in the same manner as a normal associative memory. Also, the longest match length is output as needed (not shown). This search is very fast and is performed regardless of the stored location of the entry. That is, there is no need to rearrange data by adding or deleting data as in the related art.

FIG. 2 shows a second embodiment. The difference from FIG. 1 is that the address data section 2a and the attribute data section 2b are separated, and the search circuit and the hit flags 23a,
23b. By doing so, the search for the first search data 101010 needs to be performed only once,
After that, only the search for the attribute data is sufficient, and it is possible to suppress the power consumption due to the unnecessary search of the part where the result is found.

Further, in the first search, the first bit AD2 of the attribute data portion can be searched, and the speed can be further increased. Of course, this is based on the assumption that the result of the hit flag 23a is reflected in the rehit flag 23b of the same entry, and that the result of the hit flag 23a of each entry can be detected by wired-OR connection. It is. Otherwise, even if there is no entry that matches the search data in the entry data, it will not be known until the end of the search. If this penalty is not a problem, the first embodiment can search the first one bit of the attribute data from the beginning.

FIG. 3 shows a third embodiment. This figure details the one-bit portion of the attribute data portion, but differs from the first and second embodiments in that different search input data can be continuously searched. In the first and second embodiments, it is impossible to search for the next network address data until the attribute data value of one network address search data is determined. However, this attribute data search unit is pipelined. This makes it possible to continuously search for different network data.

First, the network address search data and the network address portion of each entry are compared and searched, and a match / mismatch flag signal is input to the hit flag 31. Then the first attribute data (most significant bit) 3
A logical product is calculated with the value of 2 and the value is input to one gate of a serial transistor composed of the NMOS transistors 34a and 34b. The other gate is connected to a control signal line 136, and the two transistors are connected to a match line 137. This circuit is wired-connected for each entry, and when the search data and the entry data match and the attribute data is 1, this match line 137 pre-charged is dropped.

The potential of the match line 137 is detected by the inverter 36a and is input to the attribute match detection circuit 37. If the match line 137 has been debited,
The value of the hit flag 31 is directly input to the next hit flag 39 by the selector circuit 38 controlled by the control line 138. If the match line 137 is dropped, the output of the AND circuit 33 is input to the next hit flag 39 via the selector circuit 38 by the value of the hit flag 31.

Now, it is verified below whether the logic of this circuit is correct. First, when the output from the AND operation 33 of each entry becomes 1, the match line 137 becomes low, and the output from the AND circuit 33 is selected by the selector circuit 38 as the output to the next hit flag. This is a hit, the attribute data is also 1 and the next hit flag is also 1, which is the expected result. On the other hand, when the output of the AND circuit 33 of any entry is 0, the following three combinations of the hit flag and attribute data of each entry data can be considered. 1) Hit flag is 0, attribute data is 0 2) Hit flag is 0, attribute data is 1 3) Hit flag is 1, attribute data is 0 In either case, the value of the hit flag is passed and the next hit flag is passed. , It is possible to detect the next larger attribute that matches. Of course, it is understood that only the case 3) is significant in the next detection, and that the attribute data is 0. In either case, the circuit of FIG. 3 operates correctly.

FIG. 4 shows the timing of this operation.
It is. First, data is taken and output to the hit flag 31 at the rising timing of b) in FIG. After a while, the control signal line 136 of the wired OR circuit becomes low, and the PMOS transistor 3 becomes low.
By 6B, the match line 137 is precharged high. Further, at the rising timing of FIG. 3C, the value of the match line 137 is changed by a wired circuit connected to the output of the hit flag 31 and the output of the AND circuit 33 based on the value of the attribute data 32. The input to the next hit flag 39 is selected by the selector circuit 38, and its value is input at the next rising timing in FIG. At the same time, the search result of the next address data is input to the hit flag 31. In this way, the result is shifted while the hit flag is fetched and compared with the attribute data, thereby making it possible to search for continuous address data.

[0025]

According to the present invention, it is possible for the first time to configure a route search device capable of easily adding / deleting data and performing a high-speed search, which is indispensable for the subsequent high-speed network route search. The industrial value is extremely high.

[Brief description of the drawings]

FIG. 1 is a structural diagram illustrating a data configuration method using a ternary associative memory device according to a first embodiment of the present invention.

FIG. 2 is a structural diagram illustrating a data configuration method using a ternary associative memory device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of an attribute data detecting device according to a third embodiment of the present invention.

FIG. 4 is a timing chart of the third embodiment.

FIG. 5 is an example of a circuit configuration diagram of a ternary associative memory device.

FIG. 6 is an example of a cell data configuration diagram of a ternary associative memory device.

FIG. 7 is an example of a search data configuration diagram of a ternary associative memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Entry data 1a Network address part 1b Attribute data 2 Search data 3 Hit flag 4 Data search control device

Claims (1)

[Claims] 1. A ternary associative memory device for storing a plurality of entry data, storage means for storing first data and its attribute data in each entry data, and externally input data and a first Matching search identification means for searching and identifying entry data matching the data area, and maximum (or minimum) detection means for successively searching the attribute data of the matching entry data a plurality of times and detecting the maximum (or minimum) thereof A route search device characterized by the above-mentioned.