JP2002110941A - Method for manufacturing semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain variations in resistance in a buried strap and prevent influence of the tensile stress on the buried strap. SOLUTION: After a collar oxide film 18 is formed, an amorphous silicon film 19 buried in a trench 14 is annealed at a high temperature. Thereby the impurities in amorphous silicon in the amorphous silicon film 19 are fully diffused, and the concentration of the impurities becomes uniform. As a result, the amorphous silicon film 19 is changed into a polysilicon film 19a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor memory device having a trench capacitor, and more particularly to a process for forming a buried strap for electrically connecting a storage node electrode and a cell transistor diffusion layer. .

[0002]

2. Description of the Related Art In a semiconductor memory device having a trench capacitor, a storage node electrode of the trench capacitor and a diffusion layer of a cell transistor are electrically connected by a buried strap.

FIGS. 13 to 21 are sectional views showing the steps of manufacturing a conventional semiconductor memory device. Hereinafter, a method of forming a buried strap according to the related art will be described.

[0004] First, as shown in FIG.
1, a PadSiO ₂ film 12 is deposited, and the PadS
A PadSiN film 13 is deposited on the SiO ₂ film 12. Next, the PadSiN film 13, the PadSiO ₂ film 12, and the semiconductor substrate 11 are selectively removed by photolithography and dry etching, and a trench 14 is formed in the semiconductor substrate 11. Next, a buried plate electrode 15 is formed in the lower portion of the outer surface of the trench 14 by diffusing an n-type impurity.

[0005] Next, as shown in FIG.
A capacitor dielectric film 16 is deposited on the inner wall of the capacitor. As serving as a storage node electrode is formed on the capacitor dielectric film 16.
A -doped amorphous silicon film (hereinafter, referred to as a storage node) 17 is deposited, and the storage node 17 fills the trench 14. Next, the storage node 17 is etched back to a desired depth. Then, the trench 14 is formed by using a solution such as H ₃ PO _4.
The capacitor dielectric film 16 on the side walls is etched away. Thereafter, a thermal oxide film (not shown) is formed on the semiconductor substrate 11.
Is formed.

[0006] Next, as shown in FIG.
A collar oxide film 18 is deposited on the inner wall of the substrate. The collar oxide film 18 has a function of electrically insulating the buried plate electrode 15 from a diffusion layer (not shown) of the cell transistor. Thereafter, the color oxide film 18 on the surface of the storage node 17 is removed by using a dry etching method in order to make contact between an amorphous silicon film described later and the storage node 17.

[0007] Next, as shown in FIG.
A doped amorphous silicon film 19 is deposited, and the trench 14 is filled with the amorphous silicon film 19.

Next, as shown in FIG. 17, the amorphous silicon film 19 is etched back to a depth necessary for making contact with a cell transistor diffusion layer (not shown).

Next, as shown in FIG. 18, the collar oxide film 18 is removed by, for example, a wet etching method, and a part of the surface of the semiconductor substrate 11 in the trench 14 is exposed. Here, the surface of the color oxide film 18 is located below the surface of the polysilicon film 19a. This forms an opening 20 for the buried strap.

Next, as shown in FIG. 19, an amorphous silicon film 21 for making contact between a diffusion layer (not shown) of the cell transistor and the storage node 17 is deposited, and a buried strap is formed by the amorphous silicon film 21. Opening 20 is embedded. Thereby, the buried strap 20a is formed.

Next, as shown in FIG. 20, STI (Shalloy) is performed by photolithography and dry etching.
w Trench Isolation) A groove 41 is formed. Then, S
The sidewall of the TI groove 41 is oxidized.

Next, as shown in FIG. 21, an insulating film 42 such as an oxide film is formed on the entire surface.
The TI groove 41 is buried. Next, PadSiO ₂ film 1
The insulating film 42 and the PadSiN film 13 are flattened until the surface 2 is exposed, and an active area 45 is formed.

[0013]

By the way, FIG.
As shown in (a) and (b), the amorphous silicon film 19 buried in the trench 14 is a film containing an n-type impurity.
It has a stacked structure in which n-doped amorphous silicon 43 and impurity adsorption layers 44 are alternately deposited. Then, through a heat step of about 900 ° C. or more, the impurities in the amorphous silicon film 19 are diffused to have a uniform impurity distribution. That is, the amorphous silicon is changed to polysilicon in this heat process.

However, in the manufacturing method according to the prior art described above, the high-temperature heating step is first performed on the embedded amorphous silicon film 19 because the oxidation of the side walls of the STI trench 41 before the insulating film 42 is embedded in the STI trench 41. It is a process.

That is, in the above-mentioned prior art, FIG.
As shown in FIG. 8, after the amorphous silicon film 19 is etched back to an appropriate depth, the collar oxide film 18 is removed. At this time, the amorphous silicon film 19 does not change from amorphous silicon to polysilicon, and the impurities in the amorphous silicon film 19 do not diffuse sufficiently and the non-doped amorphous silicon 43
And the impurity adsorption layer 44 are kept in a laminated state. In this state, as shown in FIG.
1 is deposited.

Therefore, before the impurities in the amorphous silicon film 19 are diffused, the amorphous silicon film 19 is cut off by processing such as STI formation in a later step. For this reason, as shown in FIGS.
Disturbance in the shape of the I-groove 41 and misalignment between the STI trench 41 and the trench 14 occur.
The impurity layer (impurity amount) in 21 largely depends on the impurity layer, which promotes the non-uniformity of the impurity concentration. As a result, the resistance value of the embedded strap 20a varies greatly. Therefore, when the impurity concentration varies to the low concentration side, the resistance of the buried strap 20a increases,
This may cause a writing failure or the like. Therefore, problems such as a decrease in Yield due to insufficient writing occur.

Even when the impurity concentration is sufficiently high, the volume shrinkage occurs when the amorphous silicon of the amorphous silicon film 19 is changed to polysilicon by the high-temperature heating step after the STI processing. Therefore, the active area 45 connected to the buried strap 20a
The semiconductor substrate 11 on the side receives tensile stress, and this stress causes distortion, defects, and the like in the buried strap 20a. As a result, there arises a problem that junction leakage increases and retention failure increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of suppressing a variation in resistance value in an embedded strap and preventing an influence of the tensile stress on the embedded strap. An object of the present invention is to provide a method for manufacturing a storage device.

[0019]

The present invention uses the following means to achieve the above object.

According to a first method of manufacturing a semiconductor memory device of the present invention, a step of selectively forming a trench in a semiconductor substrate; a step of forming a plate electrode on an outer surface below the trench; Forming a capacitor dielectric film on the inner wall of the trench, forming a storage node electrode on the capacitor dielectric film, etching back the storage node electrode and the capacitor dielectric film, and forming an inner wall of the trench. Forming a color oxide film on the surface of the storage node electrode, removing the color oxide film on the surface of the storage node electrode, and forming an amorphous silicon film on the entire surface to fill the trench.
Converting the amorphous silicon film into a polysilicon film by performing high-temperature annealing.

According to a second method of manufacturing a semiconductor memory device of the present invention, a step of selectively forming a trench in a semiconductor substrate; a step of forming a plate electrode on an outer surface below the trench; Forming a capacitor dielectric film on the inner wall of the trench, forming a storage node electrode on the capacitor dielectric film, etching back the storage node electrode and the capacitor dielectric film, and forming an inner wall of the trench. Forming a color oxide film on the surface of the storage node electrode, removing the color oxide film on the surface of the storage node electrode, and forming an amorphous silicon film on the entire surface to fill the trench.
The method includes a step of etching back the amorphous silicon film and a step of changing the etched back amorphous silicon film to a polysilicon film by performing high-temperature annealing.

According to a third method of manufacturing a semiconductor memory device of the present invention, a step of selectively forming a trench in a semiconductor substrate; a step of forming a plate electrode on an outer surface below the trench; Forming a capacitor dielectric film on the inner wall of the trench, forming a storage node electrode on the capacitor dielectric film, etching back the storage node electrode and the capacitor dielectric film, and forming an inner wall of the trench. Forming a color oxide film on the surface of the storage node electrode, removing the color oxide film on the surface of the storage node electrode, and forming an amorphous silicon film on the entire surface to fill the trench.
The step of etching back the amorphous silicon film, the step of covering the surface of the etched back amorphous silicon film with an insulating film, and the step of performing high-temperature annealing, so that the etched back amorphous silicon film is made of polysilicon. Converting to a film.

In the first to third methods of manufacturing a semiconductor memory device according to the present invention, it is preferable that the annealing is performed in a non-oxidizing atmosphere.

According to the first to third methods for manufacturing a semiconductor memory device, the amorphous silicon film embedded in the trench is annealed at a high temperature. Thereby, the impurities in the amorphous silicon in the amorphous silicon film are sufficiently diffused, and the impurity concentration becomes uniform. As a result, the amorphous silicon film is changed to a polysilicon film. Thereby, it is possible to suppress the variation of the resistance value in the buried strap and prevent the tensile stress from affecting the buried strap.

Furthermore, when annealing is usually performed in an oxidizing atmosphere, there is a problem that stress is generated when amorphous silicon is oxidized and extra stress is stored. However, according to the present invention, since the high-temperature annealing of the amorphous silicon film is performed in a non-oxidizing atmosphere, the above problem can be avoided.

According to the third method for manufacturing a semiconductor memory device, the surface of the amorphous silicon film is covered with the insulating film when the high-temperature annealing is performed. For this reason, it is possible to prevent the impurities in the amorphous silicon film from being diffused outward and reducing the impurity concentration. In addition, since the impurity moves at the interface between the polysilicon film and the insulating film in the direction in which the impurities are deposited, the impurity concentration near the interface increases.
Thereby, the resistance value of the embedded strap can be reduced.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a process for forming a buried strap for electrically connecting a storage node of a trench capacitor and a diffusion layer of a cell transistor in a semiconductor memory device having a trench capacitor. Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] The first embodiment is characterized in that after a collar oxide film is formed, an amorphous silicon film embedded in a trench is annealed at a high temperature to be changed to polysilicon. I do.

FIGS. 1 to 7 are cross-sectional views showing the steps of manufacturing the semiconductor memory device according to the first embodiment of the present invention. Hereinafter, a method for manufacturing the semiconductor memory device according to the first embodiment will be described.

First, as shown in FIG. 1, a semiconductor substrate (silicon substrate) 11 having a thickness of, for example, 60.degree.
A dSiO ₂ film 12 is deposited, and the PadSiO ₂ film 12
PadSiN film 1 having a thickness of, for example, 2200 °
3 are deposited. Next, the PadSiN film 13 and PadSN are formed by photolithography and dry etching.
the iO ₂ film 12 and the semiconductor substrate 11 are selectively removed,
A trench 14 is formed in the semiconductor substrate 11. next,
The buried plate electrode 15 is formed by diffusing an n-type impurity on the outer surface of the trench 14 in a region deeper than 1.5 μm from the surface of the semiconductor substrate 11.

Next, as shown in FIG. 2, the capacitor dielectric film 1 having a thickness of, for example, 80.degree.
6 is deposited. An As-doped amorphous silicon film (hereinafter, referred to as a storage node) 17 serving as a storage node electrode is deposited on the capacitor dielectric film 16, and the storage node 17 fills the trench 14. Next, the storage node 17 is etched back to a desired depth. Then, using a solution such as H ₃ PO ₄ , the capacitor dielectric film 16 on the side wall of the trench 14 is formed.
Are etched and removed. The depth of the etch back at this time is, for example, about 1.3 μm from the surface of the semiconductor substrate 11.
And from the surface of the semiconductor substrate 11 to 1.0 to 1..
The depth may be about 5 μm. Then, the semiconductor substrate 1
A thermal oxide film (not shown) having a thickness of, for example, 60 ° is formed on 1.

Next, as shown in FIG. 3, a collar oxide film 18 having a thickness of, for example, 400.degree.
Is deposited. The collar oxide film 18 is formed by a buried plate electrode 15 and a diffusion layer (not shown) of a cell transistor.
And has a function of electrically insulating them from each other. Then, in order to make contact between the amorphous silicon film described later and the storage node 17, a dry etching method is used.
The collar oxide film 18 on the surface of the storage node 17 is removed.

Next, as shown in FIG.
An amorphous silicon film 19 is deposited, and the trench 14 is filled with the amorphous silicon film 19. Thereafter, high-temperature annealing is performed, for example, at 1000 ° C. for 10 minutes in a non-oxidizing atmosphere. Thereby, the amorphous silicon film 19 is changed to the polysilicon film 19a.

Next, as shown in FIG. 5, a depth required for making contact with a cell transistor diffusion layer (not shown) (for example, 100 nm from the surface of the semiconductor substrate 11).
The polysilicon film 19a is etched back up to a depth of).

Next, as shown in FIG. 6, the collar oxide film 18 is removed by, for example, a wet etching method, and a part of the surface of the semiconductor substrate 11 in the trench 14 is exposed. Here, the surface of the color oxide film 18 is located below the surface of the polysilicon film 19a. This forms an opening 20 for the buried strap.

Next, as shown in FIG. 7, an amorphous silicon film 21 for making contact between the diffusion layer (not shown) of the cell transistor and the storage node 17 is deposited. Opening 20 is embedded. Thereby, the buried strap 20a is formed.

Thereafter, the semiconductor substrate 11, the color oxide film 18, the polysilicon film 19 are formed in the same manner as in the prior art.
a and the amorphous silicon film 21 are removed.
An element isolation region (not shown) having a (Shallow Trench Isolation) structure is formed. After that, the PadSiO ₂ film 12
The PadSiN film 13 and the like are flattened until the surface is exposed to form an active area.

According to the first embodiment, after the collar oxide film 18 is formed, the amorphous silicon film 19 embedded in the trench 14 is annealed at a high temperature.
Thereby, the impurities in the amorphous silicon in the amorphous silicon film 19 are sufficiently diffused, and the impurity concentration becomes uniform. As a result, the amorphous silicon film 19
Is changed to a polysilicon film 19a.

Thus, even if the etched volume of the polysilicon film 19a varies somewhat in the subsequent STI processing step, the impurity in the polysilicon film 19a has already sufficiently diffused, so that the variation in impurity concentration is reduced. Can be suppressed. Therefore, the embedded strap 20
The variation in the resistance value at the point a can be suppressed. In addition, an increase in the resistance of the buried strap 20a can be suppressed, so that a decrease in Yield due to insufficient writing can be prevented.

In the step of performing high-temperature annealing on the amorphous silicon film 19, a volume contraction occurs when the amorphous silicon film 19 changes to a polysilicon film 19a. Therefore, volume shrinkage occurs before the formation of the buried strap 20a, and no tensile stress is applied to the semiconductor substrate 11 in a later step, so that the influence of the tensile stress on the buried strap 20a can be prevented. As a result, distortion and defects can be prevented from occurring in the buried strap 20a, so that an increase in junction leak and an increase in retention failure can also be prevented.

In general, when annealing is performed in an oxidizing atmosphere, stress is generated when amorphous silicon is oxidized, causing a problem that extra stress is stored. However, according to the first embodiment, since the high-temperature annealing of the amorphous silicon film 19 is performed in a non-oxidizing atmosphere, the above problem can be avoided.

[Second Embodiment] The second embodiment is characterized in that after the amorphous silicon film is etched back, the amorphous silicon film embedded in the trench is annealed at a high temperature to be changed to polysilicon. And

FIGS. 8 and 9 are sectional views showing the steps of manufacturing the semiconductor memory device according to the second embodiment of the present invention. Hereinafter, a method for manufacturing the semiconductor memory device according to the second embodiment will be described. In the second embodiment, the description of the same steps as those in the first embodiment will be simplified, and only different steps will be described.

First, as shown in FIGS. 1 to 3, as in the first embodiment, for example, 400
A color oxide film 18 having a thickness of Å is deposited. After that, the storage node 1 is dry-etched.
The color oxide film 18 on the surface of 7 is removed.

Next, as shown in FIG.
An amorphous silicon film 19 is deposited, and the trench 14 is filled with the amorphous silicon film 19.

Next, as shown in FIG. 9, the depth required to make contact with the cell transistor diffusion layer (not shown) (for example, 1.2 μm from the surface of the semiconductor substrate 11).
The amorphous silicon film 19 is etched back up to a depth of (a). Thereafter, high-temperature annealing is performed, for example, at 1000 ° C. for 10 minutes in a non-oxidizing atmosphere. Thereby, the amorphous silicon film 19 is changed to the polysilicon film 19a.

Next, as shown in FIG. 6, as in the first embodiment, the collar oxide film 18 is removed and the trench 14 is removed.
A part of the surface of the semiconductor substrate 11 inside is exposed. After that, a semiconductor memory device is formed in the same manner as in the first embodiment.

According to the second embodiment, the trench 1 is etched after the amorphous silicon film 19 is etched back.
4 is annealed at a high temperature. Thereby, the impurities in the amorphous silicon in the amorphous silicon film 19 are sufficiently diffused, and the impurity concentration becomes uniform. As a result, the amorphous silicon film 19 is changed to a polysilicon film 19a. Thereby, the same effect as in the first embodiment can be obtained.

[Third Embodiment] In a third embodiment, after an oxide film is deposited on an etched back amorphous silicon film, the amorphous silicon film embedded in the trench is annealed at a high temperature to form a polysilicon. It is characterized by being changed to.

FIGS. 10 to 12 are sectional views showing the steps of manufacturing the semiconductor memory device according to the third embodiment of the present invention. Hereinafter, a method for manufacturing the semiconductor memory device according to the third embodiment will be described. In the third embodiment, the description of the same steps as those in the first and second embodiments will be simplified, and only different steps will be described.

First, as shown in FIGS. 1 to 3, similarly to the first embodiment, for example, 400
A color oxide film 18 having a thickness of Å is deposited. After that, the storage node 1 is dry-etched.
The color oxide film 18 on the surface of 7 is removed.

Next, as shown in FIG.
A doped amorphous silicon film 19 is deposited, and the trench 14 is filled with the amorphous silicon film 19.

Next, as shown in FIG. 11, a depth required to make contact with a cell transistor diffusion layer (not shown) (for example, 1.2 μm from the surface of the semiconductor substrate 11).
(depth of m), the amorphous silicon film 19 is etched back.

Next, as shown in FIG.
An insulating film (for example, an oxide film such as TEOS) 31 having a thickness of Å is deposited, and the surface of the etched back amorphous silicon film 19 is covered. Then, for example, 10
High-temperature annealing is performed at 00 ° C. for 10 minutes in a non-oxidizing atmosphere. Thereby, the amorphous silicon film 19 is changed to the polysilicon film 19a.

Next, as shown in FIG. 6, as in the first embodiment, the collar oxide film 18 is removed and the trench 14 is removed.
A part of the surface of the semiconductor substrate 11 inside is exposed. At this time, since the insulating film 31 is also removed at the same time as the collar oxide film 18, there is no need to add a new removing step. After that, a semiconductor memory device is formed in the same manner as in the first embodiment.

According to the third embodiment, after the oxide film 31 is deposited on the etched back amorphous silicon film 19, the amorphous silicon film 19 embedded in the trench 14 is annealed at a high temperature. Thereby, the impurities in the amorphous silicon in the amorphous silicon film 19 are sufficiently diffused, and the impurity concentration becomes uniform. As a result, the amorphous silicon film 19 is changed to a polysilicon film 19a. Thereby, the same effect as in the first embodiment can be obtained.

Further, when high-temperature annealing is performed, the surface of the amorphous silicon film 19 is covered with the insulating film 31. For this reason, it is possible to prevent the impurities in the amorphous silicon film 19 from being diffused outward and reducing the impurity concentration. In addition, the polysilicon film 19a and the insulating film 31
The interface moves in the direction in which the impurities are precipitated at the interface with the interface, so that the impurity concentration near the interface increases. Thereby, the resistance value itself of the embedded strap 20a can be reduced.

In addition, the present invention is not limited to the above embodiments, and can be variously modified at the stage of implementation without departing from the gist thereof. For example,
The insulating film 31 of the third embodiment may be used in the first embodiment. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent features.
For example, even if some components are deleted from all the components shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effects described in the column of the effect of the invention can be solved. Is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.

[0059]

As described above, according to the present invention, the variation of the resistance value in the buried strap is suppressed,
In addition, it is possible to provide a method of manufacturing a semiconductor memory device capable of preventing the tensile stress from affecting the embedded strap.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing step of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 1;

FIG. 3 is a sectional view showing a manufacturing step of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 2;

FIG. 4 is a sectional view showing a manufacturing step of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 3;

FIG. 5 is a sectional view following FIG. 4 illustrating the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 5;

FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 6;

FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor memory device according to the second embodiment of the present invention, following FIG. 3;

FIG. 9 is a sectional view showing a manufacturing step of the semiconductor memory device according to the second embodiment of the present invention, following FIG. 8;

FIG. 10 is a sectional view illustrating a manufacturing step of the semiconductor memory device according to the third embodiment of the present invention, following FIG. 3;

FIG. 11 is a sectional view showing a manufacturing step of the semiconductor memory device according to the third embodiment of the present invention, following FIG. 10;

FIG. 12 is a sectional view showing a manufacturing step of the semiconductor memory device according to the third embodiment of the present invention, following FIG. 11;

FIG. 13 is a sectional view showing a manufacturing process of a semiconductor memory device according to a conventional technique.

FIG. 14 is a sectional view showing a manufacturing step of a conventional semiconductor memory device, following FIG. 13;

FIG. 15 is a sectional view showing a manufacturing step of the conventional semiconductor memory device, following FIG. 14;

FIG. 16 is a sectional view showing a manufacturing step of a conventional semiconductor memory device, following FIG. 15;

FIG. 17 is a sectional view showing a manufacturing step of a conventional semiconductor memory device, following FIG. 16;

FIG. 18 is a cross-sectional view showing a manufacturing step of the conventional semiconductor memory device, following FIG. 17;

FIG. 19 is a sectional view showing a manufacturing step of the conventional semiconductor memory device, following FIG. 18;

FIG. 20 is a sectional view showing a manufacturing step of a conventional semiconductor memory device, following FIG. 19;

FIG. 21 is a sectional view showing a manufacturing step of a conventional semiconductor memory device, following FIG. 20;

FIG. 22 is a diagram showing a stacked structure of an amorphous silicon film.

FIG. 23 shows ST in a conventional semiconductor memory device;
The figure which shows the disorder of I groove shape.

[Explanation of symbols]

 Reference Signs List 11: semiconductor substrate (silicon substrate), 12: Pad oxide film, 13: Pad nitride film, 14: trench, 15: buried plate electrode, 16: capacitor dielectric film, 17: storage node amorphous silicon film, 18: color oxide film 19, an amorphous silicon film, 19a, a polysilicon film, 20, an opening of a buried strap, 20a, a buried strap, 21, an amorphous silicon film, 31, an insulating film (an oxide film such as TEOS).

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hideaki Aochi 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in Toshiba Yokohama Office 5F083 AD17 NA01 PR07 PR33 PR39

Claims (4)

[Claims] A step of selectively forming a trench in a semiconductor substrate; a step of forming a plate electrode on an outer surface of a lower portion of the trench; and a step of forming a capacitor dielectric film on an inner wall of the trench. Forming a storage node electrode on the capacitor dielectric film; etching back the storage node electrode and the capacitor dielectric film; forming a collar oxide film on an inner wall of the trench; Removing the collar oxide film on the surface of the substrate, forming an amorphous silicon film over the entire surface and filling the trench, and performing high-temperature annealing to convert the amorphous silicon film into a polysilicon film. A method of manufacturing a semiconductor memory device, the method comprising: 2. A step of selectively forming a trench in a semiconductor substrate; a step of forming a plate electrode on an outer surface below the trench; and a step of forming a capacitor dielectric film on an inner wall of the trench. Forming a storage node electrode on the capacitor dielectric film; etching back the storage node electrode and the capacitor dielectric film; forming a collar oxide film on an inner wall of the trench; A step of removing the collar oxide film on the surface of the substrate, a step of forming an amorphous silicon film on the entire surface and filling the trench, a step of etching back the amorphous silicon film, and a high-temperature annealing is performed. This changes the etched back amorphous silicon film to a polysilicon film Method of manufacturing a semiconductor memory device which comprises a step to. A step of selectively forming a trench in the semiconductor substrate; a step of forming a plate electrode on an outer surface below the trench; and a step of forming a capacitor dielectric film on an inner wall of the trench. Forming a storage node electrode on the capacitor dielectric film; etching back the storage node electrode and the capacitor dielectric film; forming a collar oxide film on an inner wall of the trench; Removing the color oxide film on the surface of the substrate, forming an amorphous silicon film over the entire surface and filling the trench, and etching back the amorphous silicon film. A process in which the surface of the amorphous silicon film is covered with an insulating film and a high-temperature annealing process are performed. Converting the etched back amorphous silicon film into a polysilicon film. 4. The method according to claim 1, wherein the annealing is performed in a non-oxidizing atmosphere.